path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.207291                       # Number of seconds simulated
sim_ticks                                1207290627000                       # Number of ticks simulated
final_tick                               1207290627000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 965295                       # Simulator instruction rate (inst/s)
host_op_rate                                  1230212                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            18956490102                       # Simulator tick rate (ticks/s)
host_mem_usage                                 382720                       # Number of bytes of host memory used
host_seconds                                    63.69                       # Real time elapsed on the host
sim_insts                                    61477134                       # Number of instructions simulated
sim_ops                                      78349023                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               56                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           56                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              56                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd     52642784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           394084                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4718772                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           323100                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4791152                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62870404                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       394084                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       323100                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          717184                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4105920                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7133264                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6580348                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             12376                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             73803                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5130                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             74888                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6746553                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           64155                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               820991                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43604069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           106                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              326420                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3908563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           212                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              267624                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             3968516                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52075617                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         326420                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         267624                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             594044                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3400938                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              14081                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2493471                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5908490                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3400938                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43604069                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          106                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             326420                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3922645                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          212                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             267624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            6461987                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               57984106                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         69267                       # number of replacements
system.l2c.tagsinuse                     52917.687101                       # Cycle average of tags in use
system.l2c.total_refs                         1645693                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        134464                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         12.238912                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        40124.661917                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       0.000403                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.001466                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          3720.854167                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          4213.259554                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker       2.746626                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.itb.walker       0.001732                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          2800.295591                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          2055.865645                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.612254                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.056776                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.064289                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000042                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.042729                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.031370                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.807460                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         4114                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         1841                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             402307                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             205875                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5723                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1959                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             449970                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             144091                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1215880                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          572580                       # number of Writeback hits
system.l2c.Writeback_hits::total               572580                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1130                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             572                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1702                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           212                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           104                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               316                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            56723                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            53017                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109740                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4114                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          1841                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              402307                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              262598                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5723                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1959                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              449970                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              197108                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1325620                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4114                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         1841                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             402307                       # number of overall hits
system.l2c.overall_hits::cpu0.data             262598                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5723                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1959                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             449970                       # number of overall hits
system.l2c.overall_hits::cpu1.data             197108                       # number of overall hits
system.l2c.overall_hits::total                1325620                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             5744                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             7874                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             5043                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             3639                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22308                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          4704                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3584                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8288                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          569                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          485                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1054                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          67193                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72340                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139533                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5744                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             75067                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5043                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             75979                       # number of demand (read+write) misses
system.l2c.demand_misses::total                161841                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5744                       # number of overall misses
system.l2c.overall_misses::cpu0.data            75067                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5043                       # number of overall misses
system.l2c.overall_misses::cpu1.data            75979                       # number of overall misses
system.l2c.overall_misses::total               161841                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        52000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       104000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    298939500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    409670500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       208500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        52500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    263172000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    189494500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1161693500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     30053000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     27343000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     57396000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3692000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6036000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      9728000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3494513965                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3764719994                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7259233959                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker        52000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       104000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    298939500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3904184465                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       208500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        52500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    263172000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3954214494                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8420927459                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker        52000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       104000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    298939500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3904184465                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       208500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        52500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    263172000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3954214494                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8420927459                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         4115                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         1843                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         408051                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         213749                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5727                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1960                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         455013                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         147730                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1238188                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       572580                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           572580                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         5834                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4156                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            9990                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          781                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          589                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1370                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       123916                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       125357                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           249273                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         4115                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         1843                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          408051                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          337665                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5727                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1960                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          455013                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          273087                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1487461                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         4115                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         1843                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         408051                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         337665                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5727                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1960                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         455013                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         273087                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1487461                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000243                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001085                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.014077                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036838                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000510                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.011083                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.024633                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.018017                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.806308                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.862368                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.829630                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.728553                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.823430                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.769343                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.542246                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.577072                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.559760                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000243                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.001085                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.014077                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.222312                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000510                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011083                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.278223                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.108804                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000243                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.001085                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.014077                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.222312                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000510                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011083                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.278223                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.108804                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52043.784819                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52028.257557                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52125                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52185.603807                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52073.234405                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52075.197239                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6388.818027                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7629.185268                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6925.193050                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6488.576450                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12445.360825                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  9229.601518                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.113315                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52042.023694                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52025.212380                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52043.784819                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52009.331197                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52185.603807                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52043.518525                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52032.102242                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52043.784819                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52009.331197                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52185.603807                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52043.518525                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52032.102242                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               64155                       # number of writebacks
system.l2c.writebacks::total                    64155                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         5743                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         7874                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         5043                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         3639                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22307                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         4704                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3584                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8288                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          569                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          485                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1054                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        67193                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72340                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139533                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         5743                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        75067                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5043                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        75979                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           161840                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         5743                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        75067                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5043                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        75979                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          161840                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    229995000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    315180000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    202652000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    145824000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    893971000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    188550000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    143713000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    332263000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22778000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19436000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     42214000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2688153000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2896625000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5584778000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    229995000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   3003333000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        40000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    202652000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3042449000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6478749000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    229995000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   3003333000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        40000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    202652000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3042449000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6478749000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12448669498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365762499                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167083912997                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1128303000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30843801500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  31972104500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13576972498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209563999                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 199056017497                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000243                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001085                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014074                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036838                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000510                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011083                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024633                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.018016                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.806308                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.862368                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.829630                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.728553                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.823430                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.769343                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.542246                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.577072                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.559760                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000243                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001085                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014074                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.222312                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000510                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011083                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.278223                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.108803                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000243                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001085                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014074                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.222312                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000510                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011083                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.278223                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.108803                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40047.884381                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.940056                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40184.810629                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.782668                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40047.884381                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40008.698896                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40184.810629                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40031.815373                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40047.884381                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40008.698896                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40184.810629                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40031.815373                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7076084                       # DTB read hits
system.cpu0.dtb.read_misses                      3743                       # DTB read misses
system.cpu0.dtb.write_hits                    5660386                       # DTB write hits
system.cpu0.dtb.write_misses                      804                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1791                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 7079827                       # DTB read accesses
system.cpu0.dtb.write_accesses                5661190                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         12736470                       # DTB hits
system.cpu0.dtb.misses                           4547                       # DTB misses
system.cpu0.dtb.accesses                     12741017                       # DTB accesses
system.cpu0.itb.inst_hits                    29574655                       # ITB inst hits
system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1332                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                29576860                       # ITB inst accesses
system.cpu0.itb.hits                         29574655                       # DTB hits
system.cpu0.itb.misses                           2205                       # DTB misses
system.cpu0.itb.accesses                     29576860                       # DTB accesses
system.cpu0.numCycles                      2414581254                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   28876799                       # Number of instructions committed
system.cpu0.committedOps                     37228975                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             33114839                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
system.cpu0.num_func_calls                    1241592                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4354316                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    33114839                       # number of integer instructions
system.cpu0.num_fp_insts                         3860                       # number of float instructions
system.cpu0.num_int_register_reads          190147140                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          36238708                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     13404188                       # number of memory refs
system.cpu0.num_load_insts                    7413537                       # Number of load instructions
system.cpu0.num_store_insts                   5990651                       # Number of store instructions
system.cpu0.num_idle_cycles              2267023582.330122                       # Number of idle cycles
system.cpu0.num_busy_cycles              147557671.669878                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.061111                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.938889                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   46683                       # number of quiesce instructions executed
system.cpu0.icache.replacements                408135                       # number of replacements
system.cpu0.icache.tagsinuse               509.469782                       # Cycle average of tags in use
system.cpu0.icache.total_refs                29165991                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                408647                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 71.372091                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           75845657000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   509.469782                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.995058                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.995058                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     29165991                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       29165991                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     29165991                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        29165991                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     29165991                       # number of overall hits
system.cpu0.icache.overall_hits::total       29165991                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       408647                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       408647                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       408647                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        408647                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       408647                       # number of overall misses
system.cpu0.icache.overall_misses::total       408647                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6096279000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6096279000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   6096279000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6096279000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   6096279000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6096279000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     29574638                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     29574638                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     29574638                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     29574638                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     29574638                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     29574638                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013817                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.013817                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013817                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.013817                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013817                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.013817                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.203241                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.203241                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.203241                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14918.203241                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.203241                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14918.203241                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       408647                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       408647                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       408647                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       408647                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       408647                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       408647                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4869493500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4869493500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4869493500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4869493500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4869493500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4869493500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    351814000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    351814000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013817                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013817                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013817                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.013817                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013817                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.013817                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11916.136666                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11916.136666                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11916.136666                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11916.136666                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11916.136666                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11916.136666                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                330734                       # number of replacements
system.cpu0.dcache.tagsinuse               459.649702                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                12280871                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                331246                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 37.074775                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle             664264000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   459.649702                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.897753                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.897753                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6605687                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6605687                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5355220                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5355220                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147939                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       147939                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149683                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       149683                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11960907                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11960907                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11960907                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11960907                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       228053                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       228053                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       141722                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       141722                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9325                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9325                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7497                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7497                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       369775                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        369775                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       369775                       # number of overall misses
system.cpu0.dcache.overall_misses::total       369775                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3443058000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   3443058000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4918727500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4918727500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100897000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    100897000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     74611000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     74611000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8361785500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   8361785500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8361785500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   8361785500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6833740                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6833740                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5496942                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5496942                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157264                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       157264                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157180                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       157180                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12330682                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12330682                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12330682                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12330682                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033372                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.033372                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025782                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.025782                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059295                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059295                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047697                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047697                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029988                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.029988                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029988                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029988                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.622044                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.622044                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34706.873315                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34706.873315                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.053619                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.053619                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9952.114179                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9952.114179                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.171523                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22613.171523                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.171523                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22613.171523                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       306480                       # number of writebacks
system.cpu0.dcache.writebacks::total           306480                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       228053                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       228053                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141722                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       141722                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9325                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9325                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7489                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7489                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       369775                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       369775                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       369775                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       369775                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2758303642                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2758303642                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4493366071                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4493366071                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72896006                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72896006                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     52131016                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     52131016                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1001                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1001                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7251669713                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7251669713                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7251669713                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   7251669713                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13559876000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13559876000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1253192500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1253192500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14813068500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14813068500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033372                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033372                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025782                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025782                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059295                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059295                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047646                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047646                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029988                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029988                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029988                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029988                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7817.266059                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7817.266059                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6961.011617                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6961.011617                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     8318170                       # DTB read hits
system.cpu1.dtb.read_misses                      3663                       # DTB read misses
system.cpu1.dtb.write_hits                    5832653                       # DTB write hits
system.cpu1.dtb.write_misses                     1435                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1968                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   142                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 8321833                       # DTB read accesses
system.cpu1.dtb.write_accesses                5834088                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         14150823                       # DTB hits
system.cpu1.dtb.misses                           5098                       # DTB misses
system.cpu1.dtb.accesses                     14155921                       # DTB accesses
system.cpu1.itb.inst_hits                    33211066                       # ITB inst hits
system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1495                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                33213237                       # ITB inst accesses
system.cpu1.itb.hits                         33211066                       # DTB hits
system.cpu1.itb.misses                           2171                       # DTB misses
system.cpu1.itb.accesses                     33213237                       # DTB accesses
system.cpu1.numCycles                      2413083038                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   32600335                       # Number of instructions committed
system.cpu1.committedOps                     41120048                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             37342001                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
system.cpu1.num_func_calls                     963082                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3716244                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    37342001                       # number of integer instructions
system.cpu1.num_fp_insts                         6793                       # number of float instructions
system.cpu1.num_int_register_reads          213831809                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          39482622                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
system.cpu1.num_mem_refs                     14689113                       # number of memory refs
system.cpu1.num_load_insts                    8640454                       # Number of load instructions
system.cpu1.num_store_insts                   6048659                       # Number of store instructions
system.cpu1.num_idle_cycles              1863361359.722463                       # Number of idle cycles
system.cpu1.num_busy_cycles              549721678.277537                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.227809                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.772191                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   43948                       # number of quiesce instructions executed
system.cpu1.icache.replacements                455071                       # number of replacements
system.cpu1.icache.tagsinuse               479.019014                       # Cycle average of tags in use
system.cpu1.icache.total_refs                32755479                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                455583                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 71.897940                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           94151388000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   479.019014                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.935584                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.935584                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst     32755479                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       32755479                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     32755479                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        32755479                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     32755479                       # number of overall hits
system.cpu1.icache.overall_hits::total       32755479                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       455583                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       455583                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       455583                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        455583                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       455583                       # number of overall misses
system.cpu1.icache.overall_misses::total       455583                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6728250000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   6728250000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   6728250000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   6728250000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   6728250000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   6728250000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     33211062                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     33211062                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     33211062                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     33211062                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     33211062                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     33211062                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013718                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.013718                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013718                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.013718                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013718                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.013718                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 14768.439560                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 14768.439560                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       455583                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       455583                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       455583                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       455583                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       455583                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       455583                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5360597500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5360597500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5360597500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5360597500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5360597500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5360597500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5250000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      5250000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013718                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013718                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013718                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.013718                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013718                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.013718                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.456387                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.456387                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.456387                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.456387                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.456387                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.456387                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                292605                       # number of replacements
system.cpu1.dcache.tagsinuse               473.034237                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                11973075                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                292945                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 40.871409                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           85130110000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   473.034237                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.923895                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.923895                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      6952995                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        6952995                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4831955                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4831955                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81928                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        81928                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82891                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        82891                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     11784950                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        11784950                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     11784950                       # number of overall hits
system.cpu1.dcache.overall_hits::total       11784950                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       170988                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       170988                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       150171                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       150171                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11121                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        11121                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10078                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10078                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       321159                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        321159                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       321159                       # number of overall misses
system.cpu1.dcache.overall_misses::total       321159                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2374362000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2374362000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5137708000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   5137708000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    106370500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    106370500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     87843000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     87843000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   7512070000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   7512070000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   7512070000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   7512070000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      7123983                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      7123983                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4982126                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4982126                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93049                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        93049                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92969                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        92969                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     12106109                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     12106109                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     12106109                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     12106109                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.024002                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.024002                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030142                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030142                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119518                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119518                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108402                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108402                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026529                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.026529                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026529                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.026529                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13886.132360                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13886.132360                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.384548                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.384548                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9564.832299                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9564.832299                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8716.312760                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8716.312760                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23390.501278                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23390.501278                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23390.501278                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 23390.501278                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       266100                       # number of writebacks
system.cpu1.dcache.writebacks::total           266100                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170988                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       170988                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150171                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       150171                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11121                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11121                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10070                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10070                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       321159                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       321159                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       321159                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       321159                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1860790612                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1860790612                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4686951190                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4686951190                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72983005                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     72983005                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     57622011                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     57622011                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6547741802                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   6547741802                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6547741802                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   6547741802                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39932204000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39932204000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024002                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.024002                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030142                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030142                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119518                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119518                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108316                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108316                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026529                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026529                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026529                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026529                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6562.629710                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6562.629710                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5722.146077                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5722.146077                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 574279130811                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------