path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.871806                       # Number of seconds simulated
sim_ticks                                2871806231000                       # Number of ticks simulated
final_tick                               2871806231000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 717242                       # Simulator instruction rate (inst/s)
host_op_rate                                   867543                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            15665668571                       # Simulator tick rate (ticks/s)
host_mem_usage                                 616200                       # Number of bytes of host memory used
host_seconds                                   183.32                       # Real time elapsed on the host
sim_insts                                   131483712                       # Number of instructions simulated
sim_ops                                     159036662                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1158756                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1268260                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8634112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           151380                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           543380                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       351296                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12108656                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1158756                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       151380                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1310136                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8536192                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8553756                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26559                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20336                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134908                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2520                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8511                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5489                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198346                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          133378                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               137769                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           134                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              403494                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              441625                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3006509                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52712                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              189212                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       122326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4216390                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         403494                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52712                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             456206                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2972412                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6102                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2978528                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2972412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          134                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             403494                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             447727                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3006509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52712                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             189226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       122326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7194919                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198346                       # Number of read requests accepted
system.physmem.writeReqs                       137769                       # Number of write requests accepted
system.physmem.readBursts                      198346                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     137769                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12684736                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8566272                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12108656                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8553756                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11680                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11729                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12020                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11779                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20245                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11824                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12521                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12818                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12201                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12749                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11883                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11375                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11512                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11780                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10986                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11097                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8306                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8598                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8866                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8386                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7973                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8273                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8936                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8926                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8615                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9047                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8395                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8237                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8245                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7999                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7661                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7385                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          23                       # Number of times write queue was full causing retry
system.physmem.totGap                    2871805791000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  188586                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 133378                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    139268                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15633                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8733                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6919                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5418                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4551                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3807                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3363                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       59                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6471                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8498                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8700                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       81                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        87931                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      241.677497                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     136.342742                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     304.582310                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46815     53.24%     53.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17415     19.81%     73.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6112      6.95%     80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3386      3.85%     83.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2470      2.81%     86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1473      1.68%     88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          853      0.97%     89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          929      1.06%     90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8478      9.64%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          87931                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6424                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.852584                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      590.448326                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6422     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6424                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6424                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.835616                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.963518                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.817635                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5349     83.27%     83.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             441      6.86%     90.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              73      1.14%     91.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              47      0.73%     92.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              38      0.59%     92.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              25      0.39%     92.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              52      0.81%     93.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              19      0.30%     94.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             115      1.79%     95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              11      0.17%     96.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              10      0.16%     96.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.16%     96.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              81      1.26%     97.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.14%     97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     97.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              28      0.44%     98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              75      1.17%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               5      0.08%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.05%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.05%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.16%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.11%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6424                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4482627455                       # Total ticks spent queuing
system.physmem.totMemAccLat                8198858705                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    990995000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       22616.80                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  41366.80                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.42                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.22                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165480                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     78635                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  58.74                       # Row buffer hit rate for writes
system.physmem.avgGap                      8544116.72                       # Average gap between requests
system.physmem.pageHitRate                      73.51                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  342929160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  187114125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 816004800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                442350720                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187572184800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            85984866225                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1647656379000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1923001828830                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.614852                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2740877422516                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95895800000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35029624984                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  321829200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  175601250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 729939600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                424984320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187572184800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85018582845                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1648503996000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1922747118015                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.526158                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2742296701194                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95895800000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     33613567806                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     8733                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                8733                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1652                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7081                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         8733                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           8733    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         8733                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7215                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12160.221760                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11349.326630                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6137.175819                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767         7184     99.57%     99.57% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           27      0.37%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            3      0.04%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7215                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1809726500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5610     77.75%     77.75% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1605     22.25%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7215                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8733                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8733                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7215                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7215                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        15948                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25746594                       # DTB read hits
system.cpu0.dtb.read_misses                      7520                       # DTB read misses
system.cpu0.dtb.write_hits                   19247313                       # DTB write hits
system.cpu0.dtb.write_misses                     1213                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3753                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1863                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      321                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25754114                       # DTB read accesses
system.cpu0.dtb.write_accesses               19248526                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         44993907                       # DTB hits
system.cpu0.dtb.misses                           8733                       # DTB misses
system.cpu0.dtb.accesses                     45002640                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3674                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3674                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3354                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3674                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3674    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3674                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12667.119565                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11857.484982                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6117.849264                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2266     87.97%     87.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          279     10.83%     98.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           28      1.09%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-180223            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1809154500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2256     87.58%     87.58% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          320     12.42%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2576                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2576                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2576                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6250                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   121577578                       # ITB inst hits
system.cpu0.itb.inst_misses                      3674                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2371                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               121581252                       # ITB inst accesses
system.cpu0.itb.hits                        121577578                       # DTB hits
system.cpu0.itb.misses                           3674                       # DTB misses
system.cpu0.itb.accesses                    121581252                       # DTB accesses
system.cpu0.numCycles                      5743612462                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1891                       # number of quiesce instructions executed
system.cpu0.committedInsts                  117761026                       # Number of instructions committed
system.cpu0.committedOps                    142319020                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            125932364                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                 11483                       # Number of float alu accesses
system.cpu0.num_func_calls                   12772321                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     16008283                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   125932364                       # number of integer instructions
system.cpu0.num_fp_insts                        11483                       # number of float instructions
system.cpu0.num_int_register_reads          231711074                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          87448067                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                8771                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2716                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           515452324                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           53494266                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     46150372                       # number of memory refs
system.cpu0.num_load_insts                   26005626                       # Number of load instructions
system.cpu0.num_store_insts                  20144746                       # Number of store instructions
system.cpu0.num_idle_cycles              5456042423.958100                       # Number of idle cycles
system.cpu0.num_busy_cycles              287570038.041900                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050068                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949932                       # Percentage of idle cycles
system.cpu0.Branches                         29545974                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2315      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 99839256     68.33%     68.33% # Class of executed instruction
system.cpu0.op_class::IntMult                  112113      0.08%     68.41% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8315      0.01%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::MemRead                26005626     17.80%     86.21% # Class of executed instruction
system.cpu0.op_class::MemWrite               20144746     13.79%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 146112371                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           733230                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          488.702331                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           44081285                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           733742                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            60.077364                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1836359000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   488.702331                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.954497                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.954497                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         90665231                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        90665231                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     24440591                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       24440591                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     18493820                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18493820                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       326163                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       326163                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374037                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374037                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371586                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       371586                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     42934411                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        42934411                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     43260574                       # number of overall hits
system.cpu0.dcache.overall_hits::total       43260574                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       418663                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       418663                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       337563                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       337563                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133473                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       133473                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22401                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22401                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19896                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19896                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       756226                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        756226                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       889699                       # number of overall misses
system.cpu0.dcache.overall_misses::total       889699                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5670544000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5670544000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6922080500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6922080500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    345375500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    345375500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    506120500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    506120500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1857000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1857000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  12592624500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  12592624500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  12592624500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  12592624500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24859254                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24859254                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18831383                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18831383                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       459636                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       459636                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396438                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       396438                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391482                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       391482                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     43690637                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     43690637                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     44150273                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     44150273                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016841                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016841                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017926                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017926                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.290388                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.290388                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056506                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056506                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050822                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050822                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017309                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.017309                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020152                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.020152                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13544.411615                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13544.411615                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20506.040354                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20506.040354                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.860810                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.860810                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25438.304182                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25438.304182                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16651.932756                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16651.932756                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       733230                       # number of writebacks
system.cpu0.dcache.writebacks::total           733230                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25285                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25285                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15695                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15695                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25286                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25286                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25286                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25286                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       393378                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       393378                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337562                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       337562                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106333                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       106333                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6706                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6706                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19896                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19896                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       730940                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       730940                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       837273                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       837273                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31817                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31817                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60316                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60316                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4848200000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4848200000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6584514000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6584514000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1737943000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1737943000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103994500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103994500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    486281500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    486281500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1800000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1800000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11432714000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  11432714000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13170657000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13170657000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6628843000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6628843000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6628843000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6628843000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015824                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015824                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017926                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017926                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231342                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.231342                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016916                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016916                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050822                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050822                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016730                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016730                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018964                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018964                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12324.532638                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12324.532638                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19506.087771                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19506.087771                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16344.342772                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16344.342772                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15507.679690                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15507.679690                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24441.169079                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24441.169079                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          1147026                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.321434                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          120430031                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1147538                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           104.946443                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14862010000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321434                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998675                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998675                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        244302703                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       244302703                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    120430031                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      120430031                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    120430031                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       120430031                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    120430031                       # number of overall hits
system.cpu0.icache.overall_hits::total      120430031                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1147547                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1147547                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1147547                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1147547                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1147547                       # number of overall misses
system.cpu0.icache.overall_misses::total      1147547                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12241983500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  12241983500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  12241983500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  12241983500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  12241983500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  12241983500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    121577578                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    121577578                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    121577578                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    121577578                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    121577578                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    121577578                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009439                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009439                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009439                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009439                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009439                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009439                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10667.958262                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10667.958262                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10667.958262                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10667.958262                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10667.958262                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1147026                       # number of writebacks
system.cpu0.icache.writebacks::total          1147026                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1147547                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1147547                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1147547                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1147547                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1147547                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1147547                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11668210000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11668210000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11668210000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11668210000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11668210000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11668210000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009439                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009439                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009439                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009439                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009439                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009439                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10167.958262                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10167.958262                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1935584                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1935659                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           66                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       246453                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          273594                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16077.204583                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3064483                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          289692                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           10.578418                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14597.123435                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.512757                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.144663                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1477.423728                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.890938                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000153                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000009                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.090175                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981275                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1029                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15061                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          254                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          333                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          432                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3292                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7648                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3847                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062805                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.919250                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        62842008                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       62842008                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        11176                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4956                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         16132                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       502092                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       502092                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1349261                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1349261                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data            1                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       238948                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       238948                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1101688                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1101688                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       411953                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       411953                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        11176                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4956                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1101688                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       650901                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1768721                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        11176                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4956                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1101688                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       650901                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1768721                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          156                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           75                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          231                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55191                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55191                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19886                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19886                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           10                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total           10                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43422                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43422                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        45859                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        45859                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94464                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        94464                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          156                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker           75                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        45859                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       137886                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       183976                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          156                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker           75                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        45859                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       137886                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       183976                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4297500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2025500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total      6323000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    162363000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    162363000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     41658000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     41658000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1712496                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1712496                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2783886000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2783886000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3283750500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3283750500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3241501500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3241501500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4297500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2025500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3283750500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6025387500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   9315461000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4297500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2025500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3283750500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6025387500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   9315461000                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        11332                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5031                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        16363                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       502092                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       502092                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1349261                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1349261                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55192                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55192                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19886                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19886                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           10                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       282370                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       282370                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1147547                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1147547                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       506417                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       506417                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        11332                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5031                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1147547                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       788787                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1952697                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        11332                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5031                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1147547                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       788787                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1952697                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.013766                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.014908                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.014117                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.153777                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.153777                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.039963                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.039963                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186534                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186534                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.013766                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.014908                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.039963                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.174808                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.094216                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.013766                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.014908                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.039963                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.174808                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.094216                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27548.076923                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27006.666667                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27372.294372                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2941.838343                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2941.838343                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2094.840591                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2094.840591                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 171249.600000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 171249.600000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64112.339367                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64112.339367                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71605.366449                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71605.366449                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34314.675432                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34314.675432                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27548.076923                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27006.666667                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71605.366449                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43698.326879                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 50634.109884                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27548.076923                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27006.666667                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71605.366449                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43698.326879                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 50634.109884                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10692                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       231848                       # number of writebacks
system.cpu0.l2cache.writebacks::total          231848                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1793                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1793                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           59                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           59                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1852                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1852                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1852                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1852                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          156                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           75                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          231                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264648                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       264648                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55191                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55191                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19886                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19886                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           10                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41629                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41629                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        45859                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        45859                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94405                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94405                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          156                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           75                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        45859                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136034                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       182124                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          156                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           75                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        45859                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136034                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264648                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       446772                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31817                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40839                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60316                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69338                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3361500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1575500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      4937000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20425308140                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20425308140                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1407414000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1407414000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    337427000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    337427000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1370496                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1370496                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2353646000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2353646000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3008596500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3008596500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2668850500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2668850500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3361500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1575500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3008596500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5022496500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8036030000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3361500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1575500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3008596500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5022496500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20425308140                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  28461338140                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6373893500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7560105000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6373893500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7560105000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.013766                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.014908                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.014117                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999982                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.147427                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.147427                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.039963                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.039963                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186418                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.186418                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.013766                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.014908                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.039963                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.172460                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093268                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.013766                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.014908                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.039963                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.172460                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228797                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21372.294372                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77179.151703                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25500.788172                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25500.788172                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16968.067988                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16968.067988                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 137049.600000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 137049.600000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56538.614908                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.614908                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65605.366449                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65605.366449                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28270.224035                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28270.224035                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65605.366449                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36920.891101                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44123.948519                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      3905427                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1969134                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        28903                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       319838                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       316964                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         2874                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq         63699                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1766064                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       734457                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1378164                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       189732                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       311664                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        85807                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41981                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112714                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       301438                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       298033                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1147547                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       575765                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3263                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3460164                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2683424                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12059                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27146                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6182793                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    146888760                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    101708758                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        20124                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        45328                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         248662970                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     986506                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      2981817                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.122538                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.330833                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2619305     87.84%     87.84% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            359638     12.06%     99.90% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              2874      0.10%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2981817                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3886437494                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115091926                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1730342500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1266858980                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7028000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     15821984                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     2347                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                2347                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          475                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1872                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         2347                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           2347    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         2347                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1701                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11647.854203                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11021.395784                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  4763.004778                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-4095            3      0.18%      0.18% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::4096-8191          360     21.16%     21.34% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-12287          989     58.14%     79.48% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::12288-16383          206     12.11%     91.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-20479           34      2.00%     93.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::20480-24575           60      3.53%     97.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-28671           28      1.65%     98.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::28672-32767           11      0.65%     99.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-36863            1      0.06%     99.47% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::36864-40959            2      0.12%     99.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-45055            3      0.18%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-53247            3      0.18%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-61439            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1701                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1207257828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1207257828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1207257828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1226     72.08%     72.08% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          475     27.92%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1701                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2347                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2347                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1701                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1701                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         4048                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3334777                       # DTB read hits
system.cpu1.dtb.read_misses                      1951                       # DTB read misses
system.cpu1.dtb.write_hits                    2915290                       # DTB write hits
system.cpu1.dtb.write_misses                      396                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1652                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   260                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      124                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3336728                       # DTB read accesses
system.cpu1.dtb.write_accesses                2915686                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6250067                       # DTB hits
system.cpu1.dtb.misses                           2347                       # DTB misses
system.cpu1.dtb.accesses                      6252414                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1376                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1376                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          134                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1242                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1376                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1376    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1376                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          819                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11302.540712                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5121.103483                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          113     13.80%     13.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          572     69.84%     83.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383           87     10.62%     94.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            7      0.85%     95.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.12%     95.24% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           23      2.81%     98.05% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            8      0.98%     99.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            4      0.49%     99.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.24%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          819                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1208095828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1208095828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1208095828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          685     83.64%     83.64% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          134     16.36%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          819                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1376                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1376                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          819                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          819                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2195                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    13921759                       # ITB inst hits
system.cpu1.itb.inst_misses                      1376                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     883                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                13923135                       # ITB inst accesses
system.cpu1.itb.hits                         13921759                       # DTB hits
system.cpu1.itb.misses                           1376                       # DTB misses
system.cpu1.itb.accesses                     13923135                       # DTB accesses
system.cpu1.numCycles                      5742672703                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2702                       # number of quiesce instructions executed
system.cpu1.committedInsts                   13722686                       # Number of instructions committed
system.cpu1.committedOps                     16717642                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             15156242                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     915130                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1497977                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    15156242                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads           27539507                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          10698774                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            61342237                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            5194989                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      6464220                       # number of memory refs
system.cpu1.num_load_insts                    3439445                       # Number of load instructions
system.cpu1.num_store_insts                   3024775                       # Number of store instructions
system.cpu1.num_idle_cycles              5696078911.641530                       # Number of idle cycles
system.cpu1.num_busy_cycles              46593791.358469                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.008114                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.991886                       # Percentage of idle cycles
system.cpu1.Branches                          2464409                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   24      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 10544854     61.90%     61.90% # Class of executed instruction
system.cpu1.op_class::IntMult                   24300      0.14%     62.04% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3186      0.02%     62.06% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.06% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.06% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.06% # Class of executed instruction
system.cpu1.op_class::MemRead                 3439445     20.19%     82.25% # Class of executed instruction
system.cpu1.op_class::MemWrite                3024775     17.75%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  17036584                       # Class of executed instruction
system.cpu1.dcache.tags.replacements           148452                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          468.602887                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6022671                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           148794                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            40.476572                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     106290860000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   468.602887                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.915240                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.915240                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          342                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           36                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.667969                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12680857                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12680857                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3066042                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3066042                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2748534                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2748534                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41898                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        41898                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69885                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        69885                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61599                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        61599                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5814576                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5814576                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      5856474                       # number of overall hits
system.cpu1.dcache.overall_hits::total        5856474                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       112908                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       112908                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        79472                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        79472                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24389                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24389                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16600                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16600                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23097                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23097                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       192380                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        192380                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       216769                       # number of overall misses
system.cpu1.dcache.overall_misses::total       216769                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1761858500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1761858500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2707072000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2707072000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    321180000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    321180000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    626224500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    626224500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5032000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5032000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4468930500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4468930500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4468930500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4468930500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3178950                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3178950                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2828006                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2828006                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66287                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        66287                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86485                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        86485                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84696                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        84696                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      6006956                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      6006956                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6073243                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6073243                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035517                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035517                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028102                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.028102                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.367930                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.367930                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.191941                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.191941                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.272705                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.272705                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.032026                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.032026                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035692                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035692                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.372587                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15604.372587                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34063.217234                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34063.217234                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19348.192771                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19348.192771                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27112.806858                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27112.806858                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23229.704231                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23229.704231                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       148452                       # number of writebacks
system.cpu1.dcache.writebacks::total           148452                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          223                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          223                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11671                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11671                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          223                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          223                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          223                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          223                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       112685                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       112685                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79472                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        79472                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23925                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        23925                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4929                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4929                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23097                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23097                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       192157                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       192157                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       216082                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       216082                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3082                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3082                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5505                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5505                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1634927500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1634927500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2627600000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2627600000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    437401500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    437401500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     91610500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     91610500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    603174500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    603174500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4985000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4985000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4262527500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4262527500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4699929000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4699929000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    439527500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    439527500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    439527500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    439527500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035447                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035447                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028102                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028102                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.360930                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.360930                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056993                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056993                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.272705                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.272705                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031989                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031989                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035579                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035579                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14508.829924                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14508.829924                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33063.217234                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33063.217234                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18282.194357                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18282.194357                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18586.021505                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18586.021505                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26114.841754                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26114.841754                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.replacements           463484                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.310914                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           13457758                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           463996                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            29.004039                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     106358922000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.310914                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973264                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973264                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         28307504                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        28307504                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     13457758                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       13457758                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     13457758                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        13457758                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     13457758                       # number of overall hits
system.cpu1.icache.overall_hits::total       13457758                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       463996                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       463996                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       463996                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        463996                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       463996                       # number of overall misses
system.cpu1.icache.overall_misses::total       463996                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4214067500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4214067500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4214067500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4214067500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4214067500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4214067500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     13921754                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     13921754                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     13921754                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     13921754                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     13921754                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     13921754                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033329                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.033329                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033329                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.033329                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033329                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.033329                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9082.120320                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9082.120320                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9082.120320                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9082.120320                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9082.120320                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9082.120320                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       463484                       # number of writebacks
system.cpu1.icache.writebacks::total           463484                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463996                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       463996                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       463996                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       463996                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       463996                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       463996                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3982069500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3982069500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3982069500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3982069500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3982069500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3982069500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     23546500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     23546500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033329                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.033329                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.033329                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8582.120320                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8582.120320                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8582.120320                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8582.120320                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8582.120320                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8582.120320                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.num_hwpf_issued       117918                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       117936                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           16                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        50208                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           31332                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14956.481117                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1042665                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           46454                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           22.445107                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14460.199894                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.270812                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.044709                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   491.965701                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.882581                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000139                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000125                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.030027                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.912871                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          960                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           31                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14131                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          920                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           25                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          423                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1663                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12045                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.058594                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001892                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.862488                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        21157161                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       21157161                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2444                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1492                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          3936                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        91966                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        91966                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       509880                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       509880                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18290                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        18290                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       455220                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       455220                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        77690                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        77690                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2444                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1492                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       455220                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data        95980                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         555136                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2444                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1492                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       455220                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data        95980                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        555136                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          348                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          298                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          646                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29049                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29049                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23092                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23092                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32133                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32133                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst         8776                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total         8776                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        63849                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        63849                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          348                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          298                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         8776                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        95982                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       105404                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          348                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          298                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         8776                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        95982                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       105404                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6985500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5943500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     12929000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     63798000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     63798000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     54501000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     54501000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      4914000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      4914000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1634363000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1634363000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    528873500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    528873500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1442259000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1442259000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6985500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5943500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    528873500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3076622000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3618424500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6985500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5943500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    528873500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3076622000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3618424500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         2792                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1790                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         4582                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        91966                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        91966                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       509880                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       509880                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29049                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29049                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23092                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23092                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50423                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50423                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       463996                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       463996                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       141539                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       141539                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         2792                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1790                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       463996                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       191962                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       660540                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         2792                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1790                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       463996                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       191962                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       660540                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.124642                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.166480                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.140986                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.637269                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.637269                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018914                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018914                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.451105                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.451105                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.124642                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.166480                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018914                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.500005                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.159572                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.124642                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.166480                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018914                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.500005                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.159572                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20073.275862                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19944.630872                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20013.931889                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2196.220180                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2196.220180                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2360.168024                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2360.168024                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       982800                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       982800                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50862.446706                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50862.446706                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60263.616682                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60263.616682                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22588.591834                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22588.591834                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20073.275862                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19944.630872                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60263.616682                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32054.155988                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34329.100414                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20073.275862                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19944.630872                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60263.616682                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32054.155988                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34329.100414                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             502                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        26072                       # number of writebacks
system.cpu1.l2cache.writebacks::total           26072                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           73                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           73                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           73                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           73                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           73                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           73                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          348                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          298                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          646                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20991                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        20991                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29049                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29049                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23092                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23092                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32060                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32060                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst         8776                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8776                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63849                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        63849                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          348                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          298                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         8776                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        95909                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       105331                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          348                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          298                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         8776                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        95909                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        20991                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       126322                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3082                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3259                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5505                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5682                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4897500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4155500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9053000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    927478543                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    927478543                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    578238500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    578238500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    429963000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    429963000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      4632000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4632000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1434110000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1434110000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    476217500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    476217500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1059165000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1059165000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4897500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4155500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    476217500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2493275000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2978545500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4897500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4155500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    476217500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2493275000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    927478543                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3906024043                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    414523000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    436742000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    414523000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    436742000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.124642                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.166480                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.140986                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.635821                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.635821                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018914                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018914                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.451105                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451105                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.124642                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.166480                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018914                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.499625                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159462                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.124642                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.166480                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018914                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.499625                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191241                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14013.931889                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44184.581154                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19905.624978                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19905.624978                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18619.565217                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18619.565217                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       926400                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       926400                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44732.064878                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44732.064878                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54263.616682                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54263.616682                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16588.591834                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16588.591834                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54263.616682                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25996.256868                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28277.957107                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1324952                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       669028                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10089                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       168501                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       166697                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1804                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         10096                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       652859                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2423                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2423                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       119114                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       519969                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        86535                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        25223                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        70168                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40922                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        84814                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           62                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57641                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        55180                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       463996                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       214635                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           32                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1391830                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       722434                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4408                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7011                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2125683                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     59359428                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24498524                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          83876280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     355270                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples       998881                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.185518                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.393336                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            815375     81.63%     81.63% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            181702     18.19%     99.82% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              1804      0.18%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total        998881                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1279425500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79453408                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    696171000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    318356500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      2618000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      4219000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31021                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31021                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48736000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               319500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                32500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                93000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               609000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               23500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6160500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            32043500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187096722                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36461                       # number of replacements
system.iocache.tags.tagsinuse               14.380038                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36477                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         290749964000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.380038                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898752                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898752                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36479                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
system.iocache.overall_misses::total            36479                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32883377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32883377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4577110345                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4577110345                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4609993722                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4609993722                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4609993722                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4609993722                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36479                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36479                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36479                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36479                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128954.419608                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126373.906138                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126373.906138                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126373.906138                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126373.906138                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            24                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs           12                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36479                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20133377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20133377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2764215832                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2764215832                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2784349209                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2784349209                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2784349209                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2784349209                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76327.454398                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76327.454398                       # average overall mshr miss latency
system.l2c.tags.replacements                   124374                       # number of replacements
system.l2c.tags.tagsinuse                62971.222447                       # Cycle average of tags in use
system.l2c.tags.total_refs                     421293                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   188431                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.235795                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13456.936548                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.884029                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.161578                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7408.035333                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2772.307356                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35669.502662                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1440.723489                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      421.652649                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1798.018803                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.205337                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000059                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.113038                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042302                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.544273                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.021984                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.006434                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.027436                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.960865                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32172                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        31879                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          296                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5261                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        26614                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          368                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2433                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29060                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.490906                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.486435                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5838028                       # Number of tag accesses
system.l2c.tags.data_accesses                 5838028                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       257920                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          257920                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32259                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1955                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               34214                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2096                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           941                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3037                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4136                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1368                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5504                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           86                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           68                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        28311                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        47114                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        47400                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           25                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           16                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst         6412                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         5086                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3327                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           137845                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker            86                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            68                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               28311                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51250                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        47400                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            25                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            16                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                6412                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                6454                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3327                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  143349                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           86                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           68                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              28311                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51250                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        47400                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           25                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           16                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               6412                       # number of overall hits
system.l2c.overall_hits::cpu1.data               6454                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3327                       # number of overall hits
system.l2c.overall_hits::total                 143349                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9332                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2240                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11572                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          606                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1282                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1888                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11165                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7705                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              18870                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            6                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17548                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8846                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       135065                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2364                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          796                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5489                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         170116                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17548                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20011                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       135065                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2364                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8501                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5489                       # number of demand (read+write) misses
system.l2c.demand_misses::total                188986                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17548                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20011                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       135065                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2364                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8501                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5489                       # number of overall misses
system.l2c.overall_misses::total               188986                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     27811000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      6496500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     34307500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      5695500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2358500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      8054000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1626743500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1013044000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2639787500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       809500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       272000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2308407000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1204319000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19595366985                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    315452500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    119571000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    851586047                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  24395784032                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       809500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       272000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2308407000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2831062500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19595366985                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    315452500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1132615000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    851586047                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     27035571532                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       809500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       272000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2308407000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2831062500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19595366985                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    315452500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1132615000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    851586047                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    27035571532                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       257920                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       257920                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        41591                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4195                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45786                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2702                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2223                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4925                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15301                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9073                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24374                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           92                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           70                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        45859                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        55960                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       182465                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           25                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           16                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst         8776                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         5882                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8816                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       307961                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker           92                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           70                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           45859                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           71261                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       182465                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           16                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            8776                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           14955                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8816                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              332335                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker           92                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           70                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          45859                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          71261                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       182465                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           16                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           8776                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          14955                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8816                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             332335                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.224375                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.533969                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.252741                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.224278                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.576698                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.383350                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.729691                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.849223                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.774186                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.065217                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.028571                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.382651                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.158077                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.740224                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.269371                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.135328                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.622618                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.552395                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.065217                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.028571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.382651                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.280813                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.740224                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.269371                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.568439                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.622618                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.568661                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.065217                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.028571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.382651                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.280813                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.740224                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.269371                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.568439                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.622618                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.568661                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2980.175739                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2900.223214                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2964.699274                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  9398.514851                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1839.703588                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4265.889831                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145700.268697                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131478.780013                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 139893.349232                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 134916.666667                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       136000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131548.153636                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136142.776396                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133440.143824                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 150214.824121                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 143406.757930                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 134916.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 131548.153636                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 141475.313578                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 133440.143824                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 133233.149041                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 143055.948758                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 134916.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 131548.153636                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 141475.313578                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 133440.143824                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 133233.149041                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 143055.948758                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               97172                       # number of writebacks
system.l2c.writebacks::total                    97172                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            9                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           13                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         2825                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         2825                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9332                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2240                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11572                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          606                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1282                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1888                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11165                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7705                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         18870                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            6                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17544                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8846                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       135065                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2355                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          796                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5489                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       170103                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17544                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20011                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       135065                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2355                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8501                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5489                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           188973                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17544                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20011                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       135065                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2355                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8501                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5489                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          188973                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31817                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3079                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44095                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30922                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60316                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5502                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        75017                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    678754000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    162023000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    840777000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     45192500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     94781500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    139974000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1515091017                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    935989514                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2451080531                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       749500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       252000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2132646516                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1115857006                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  18244681120                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    291145013                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    111607507                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    796678627                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  22693617289                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       749500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       252000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2132646516                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2630948023                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  18244681120                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    291145013                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1047597021                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    796678627                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  25144697820                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       749500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       252000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2132646516                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2630948023                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18244681120                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    291145013                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1047597021                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    796678627                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  25144697820                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5801182501                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    359054501                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7203084502                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5801182501                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    359054501                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   7203084502                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.224375                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.533969                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.252741                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.224278                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.576698                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.383350                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.729691                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.849223                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.774186                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.065217                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.028571                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.382564                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158077                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740224                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.268345                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.135328                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.622618                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.552352                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.065217                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.028571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.382564                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.280813                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740224                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.268345                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.568439                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.622618                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.568622                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.065217                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.028571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.382564                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.280813                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.740224                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.268345                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.568439                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.622618                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.568622                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72734.033433                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72331.696429                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72656.152783                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74575.082508                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73932.527301                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74138.771186                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135700.046305                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121478.197794                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129892.979915                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121559.878933                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126142.550983                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123628.455626                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 140210.435930                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133411.035014                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121559.878933                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131475.089851                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123628.455626                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123232.210446                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 133059.737740                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121559.878933                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131475.089851                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123628.455626                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 133059.737740                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305                       # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq               44095                       # Transaction distribution
system.membus.trans_dist::ReadResp             214453                       # Transaction distribution
system.membus.trans_dist::WriteReq              30922                       # Transaction distribution
system.membus.trans_dist::WriteResp             30922                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       133378                       # Transaction distribution
system.membus.trans_dist::CleanEvict            14958                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            73332                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          39852                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39426                       # Transaction distribution
system.membus.trans_dist::ReadExResp            18801                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        170358                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13764                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       651465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       773197                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72955                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72955                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 846152                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18344268                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18534678                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20852822                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           120859                       # Total snoops (count)
system.membus.snoop_fanout::samples            582572                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  582572    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              582572                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88269500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11360500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           969988933                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1109172490                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1385877                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       961097                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       519247                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       138785                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20683                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        19864                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          819                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              44098                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            467805                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30922                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30922                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       391320                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          106223                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          107477                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         42889                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         150366                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          104                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          104                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50473                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50473                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       423722                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1241271                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       253131                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1494402                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34264962                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3773844                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               38038806                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          438960                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           896783                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.336520                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.474448                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 595817     66.44%     66.44% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 300147     33.47%     99.91% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    819      0.09%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             896783                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          864823852                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360123                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         645977888                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         202227821                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------