path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.866929                       # Number of seconds simulated
sim_ticks                                2866929256000                       # Number of ticks simulated
final_tick                               2866929256000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 703930                       # Simulator instruction rate (inst/s)
host_op_rate                                   851474                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            15295798763                       # Simulator tick rate (ticks/s)
host_mem_usage                                 599572                       # Number of bytes of host memory used
host_seconds                                   187.43                       # Real time elapsed on the host
sim_insts                                   131939289                       # Number of instructions simulated
sim_ops                                     159593891                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.realview.nvmem.bytes_read::cpu0.inst           24                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           52                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            76                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           24                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           52                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           76                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            6                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           13                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             19                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           18                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               27                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           18                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           18                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              27                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           234148                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data           830144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      9620672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            49876                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           440928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      1365312                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12542872                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       234148                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        49876                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          284024                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6392960                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8729040                       # Number of bytes written to this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             12112                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             13497                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       150323                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               934                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              6913                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        21333                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                205140                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           99890                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               140550                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               81672                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              289559                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3355741                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            89                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               17397                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              153798                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       476228                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4375020                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          81672                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          17397                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              99069                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2229898                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          808648                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6175                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3044735                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2229898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          808983                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              81672                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             295734                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3355741                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           89                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              17397                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             153812                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       476228                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7419755                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        205141                       # Number of read requests accepted
system.physmem.writeReqs                       140550                       # Number of write requests accepted
system.physmem.readBursts                      205141                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     140550                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 13114752                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     14272                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8743552                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12542936                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8729040                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      223                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3913                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          15151                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12845                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12298                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13022                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12754                       # Per bank write bursts
system.physmem.perBankRdBursts::4               21257                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12515                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12829                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12945                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12057                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12100                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12212                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11004                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11810                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12145                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11734                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11391                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8757                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8655                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9184                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8823                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8606                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8736                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8840                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8881                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8404                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8549                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8595                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8133                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8369                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8306                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8199                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7581                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    2866928814500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9742                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  195371                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 136114                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    121124                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     21708                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13339                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     11204                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      9572                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      8231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      7040                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      6218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      5357                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      142                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       64                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       45                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5630                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9843                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        80974                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      269.941463                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     151.852686                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     318.869933                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          39277     48.51%     48.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16073     19.85%     68.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6267      7.74%     76.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3406      4.21%     80.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3201      3.95%     84.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1947      2.40%     86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1140      1.41%     88.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1004      1.24%     89.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8659     10.69%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          80974                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6724                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.475461                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      574.843547                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6723     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6724                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6724                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.317965                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.827449                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.656598                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5486     81.59%     81.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             426      6.34%     87.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              82      1.22%     89.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             201      2.99%     92.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             197      2.93%     95.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              21      0.31%     95.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              19      0.28%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              16      0.24%     95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              29      0.43%     96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               5      0.07%     96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               3      0.04%     96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             175      2.60%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.12%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.10%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.06%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.10%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               6      0.09%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             4      0.06%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             3      0.04%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.12%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6724                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5972474500                       # Total ticks spent queuing
system.physmem.totMemAccLat                9814687000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1024590000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29145.68                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47895.68                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.57                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.04                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.28                       # Average write queue length when enqueuing
system.physmem.readRowHits                     175001                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     85560                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   85.40                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  62.62                       # Row buffer hit rate for writes
system.physmem.avgGap                      8293327.90                       # Average gap between requests
system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2731384342500                       # Time in different power states
system.physmem.memoryStateTime::REF       95733040000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       39811853000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 323167320                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 288996120                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 176331375                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 157686375                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                861627000                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                736725600                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               456723360                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               428561280                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          187253826240                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          187253826240                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           82374692850                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           81185757210                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1647898682250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1648941608250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1919345050395                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1918993161075                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.477790                       # Core power per rank (mW)
system.physmem.averagePower::1             669.355049                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq              228441                       # Transaction distribution
system.membus.trans_dist::ReadResp             228440                       # Transaction distribution
system.membus.trans_dist::WriteReq              31177                       # Transaction distribution
system.membus.trans_dist::WriteResp             31177                       # Transaction distribution
system.membus.trans_dist::Writeback             99890                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            85859                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41212                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15151                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq             28398                       # Transaction distribution
system.membus.trans_dist::ReadExResp            11478                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107964                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           38                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14560                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678158                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       800720                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72716                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72716                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 873436                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162847                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           76                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18952616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19144659                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21463955                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           129081                       # Total snoops (count)
system.membus.snoop_fanout::samples            475718                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  475718    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              475718                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88161999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               20500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12079498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1514580499                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1969894164                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38592409                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   132728                       # number of replacements
system.l2c.tags.tagsinuse                64199.829322                       # Cycle average of tags in use
system.l2c.tags.total_refs                     489645                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   197292                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.481829                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12574.713731                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     4.829645                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.043526                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1158.059566                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     1408.624866                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38786.462390                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.540569                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.007801                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      536.338892                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      908.008157                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8820.200180                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.191875                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000074                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.017671                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.021494                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.591834                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000039                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.008184                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.013855                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.134586                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.979612                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        44718                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        19841                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          168                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5098                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        39452                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          202                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1574                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        18054                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.682343                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.302750                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6148253                       # Number of tag accesses
system.l2c.tags.data_accesses                 6148253                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          127                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker          159                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              10419                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              29225                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       168428                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           62                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           50                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst               4147                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              10318                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        47800                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 270735                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          240561                       # number of Writeback hits
system.l2c.Writeback_hits::total               240561                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            9666                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1017                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               10683                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           240                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           136                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               376                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4189                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             2493                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 6682                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           127                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           159                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               10419                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               33414                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       168428                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            62                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            50                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                4147                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12811                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        47800                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  277417                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          127                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          159                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              10419                       # number of overall hits
system.l2c.overall_hits::cpu0.data              33414                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       168428                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           62                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           50                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               4147                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12811                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        47800                       # number of overall hits
system.l2c.overall_hits::total                 277417                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             3095                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6926                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       150324                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              769                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1418                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        21333                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               183878                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8558                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4221                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12779                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          889                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1310                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2199                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data           6118                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           5533                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              11651                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              3095                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             13044                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       150324                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               769                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              6951                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        21333                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195529                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             3095                       # number of overall misses
system.l2c.overall_misses::cpu0.data            13044                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       150324                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              769                       # number of overall misses
system.l2c.overall_misses::cpu1.data             6951                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        21333                       # number of overall misses
system.l2c.overall_misses::total               195529                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       510000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    268587999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    563686749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  15024629496                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       328000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        94250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     70493000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    122227750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   2328609330                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    18379241574                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      8946128                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     10070574                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     19016702                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1175950                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2179907                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3355857                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    485246640                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    404862686                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total    890109326                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       510000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    268587999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1048933389                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  15024629496                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       328000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        94250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     70493000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    527090436                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   2328609330                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19269350900                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       510000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    268587999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1048933389                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  15024629496                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       328000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        94250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     70493000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    527090436                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   2328609330                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19269350900                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          134                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker          160                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          13514                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          36151                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       318752                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           66                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           51                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst           4916                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          11736                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        69133                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             454613                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       240561                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           240561                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        18224                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5238                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           23462                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1129                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1446                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2575                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        10307                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         8026                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            18333                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          134                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          160                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           13514                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           46458                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       318752                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           66                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           51                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            4916                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           19762                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        69133                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              472946                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          134                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          160                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          13514                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          46458                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       318752                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           66                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           51                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           4916                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          19762                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        69133                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             472946                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.052239                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.006250                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.229022                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.191585                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.060606                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.156428                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.120825                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.404471                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.469601                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.805842                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.544668                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787422                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.905947                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.853981                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.593577                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.689385                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.635521                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.052239                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.006250                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.229022                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.280770                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.060606                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.156428                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.351736                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.413428                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.052239                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.006250                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.229022                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.280770                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.060606                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.019608                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.156428                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.351736                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.413428                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 72857.142857                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 86781.259774                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 81387.055876                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        94250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 91668.400520                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 86197.284908                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 99953.455954                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1045.352652                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2385.826581                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1488.121293                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1322.778403                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1664.051145                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1526.083220                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79314.586466                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73172.363275                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76397.676251                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 72857.142857                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 86781.259774                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 80415.009890                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        94250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 91668.400520                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 75829.439793                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 98549.836086                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 72857.142857                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 86781.259774                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 80415.009890                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 99948.308294                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        94250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 91668.400520                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 75829.439793                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109155.267895                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 98549.836086                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               99890                       # number of writebacks
system.l2c.writebacks::total                    99890                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         3095                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6926                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       150324                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          769                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1418                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        21333                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          183878                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8558                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4221                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12779                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          889                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1310                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2199                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data         6118                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         5533                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         11651                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         3095                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        13044                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       150324                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          769                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         6951                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        21333                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195529                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         3095                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        13044                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       150324                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          769                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         6951                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        21333                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195529                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       423500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    230146499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    477536249                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13155934996                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       278000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        81250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     60929000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    104521250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2067966830                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  16097880074                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     86272013                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     42559203                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    128831216                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8927886                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     13175305                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     22103191                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    408771858                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    334873814                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total    743645672                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       423500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    230146499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data    886308107                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  13155934996                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       278000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        81250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     60929000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    439395064                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   2067966830                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16841525746                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       423500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    230146499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data    886308107                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13155934996                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       278000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        81250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     60929000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    439395064                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2067966830                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16841525746                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    476853500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4797337250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      9261250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    814340500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6097792500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3540127500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    712608500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4252736000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    476853500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8337464750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      9261250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1526949000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10350528500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.052239                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.006250                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.229022                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.191585                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.060606                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.019608                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.156428                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.120825                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.404471                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.469601                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.805842                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.544668                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787422                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.905947                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.853981                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.593577                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.689385                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.635521                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.052239                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.006250                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.229022                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.280770                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.060606                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.019608                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.156428                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.351736                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.413428                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.052239                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.006250                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.229022                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.280770                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.471602                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.060606                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.019608                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.156428                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.351736                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308579                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.413428                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        60500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74360.742811                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68948.346665                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        69500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        81250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79231.469441                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73710.331453                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 87546.525816                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10080.861533                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10082.729922                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.478676                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.616423                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.484733                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10051.473852                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66814.622099                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60523.009940                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63826.767831                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        60500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74360.742811                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67947.570301                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        69500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        81250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79231.469441                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63213.215940                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 86133.134962                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        60500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74360.742811                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67947.570301                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87517.196163                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        69500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        81250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79231.469441                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63213.215940                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96937.459804                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 86133.134962                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq             633918                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            633902                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31177                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31177                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           240561                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           96369                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41588                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         137957                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            39943                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           39943                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1258028                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       400059                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1658087                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     37640280                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8288315                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               45928595                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          305065                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1044371                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.034928                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.183598                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1007893     96.51%     96.51% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36478      3.49%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1044371                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1521180751                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1071000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2136308825                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         850635338                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31019                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31019                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59408                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           32                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          844                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107964                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180918                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          446                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162847                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484103                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               503000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           326676322                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84748000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36842591                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    24353899                       # DTB read hits
system.cpu0.dtb.read_misses                      6408                       # DTB read misses
system.cpu0.dtb.write_hits                   18126722                       # DTB write hits
system.cpu0.dtb.write_misses                     1115                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3404                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1442                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24360307                       # DTB read accesses
system.cpu0.dtb.write_accesses               18127837                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         42480621                       # DTB hits
system.cpu0.dtb.misses                           7523                       # DTB misses
system.cpu0.dtb.accesses                     42488144                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   115074724                       # ITB inst hits
system.cpu0.itb.inst_misses                      3350                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2152                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               115078074                       # ITB inst accesses
system.cpu0.itb.hits                        115074724                       # DTB hits
system.cpu0.itb.misses                           3350                       # DTB misses
system.cpu0.itb.accesses                    115078074                       # DTB accesses
system.cpu0.numCycles                      5733858512                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  111430460                       # Number of instructions committed
system.cpu0.committedOps                    134719109                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            119427816                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
system.cpu0.num_func_calls                   12527987                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14980229                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   119427816                       # number of integer instructions
system.cpu0.num_fp_insts                         9755                       # number of float instructions
system.cpu0.num_int_register_reads          220379706                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          83050844                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           488414813                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           49991768                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     43590115                       # number of memory refs
system.cpu0.num_load_insts                   24600281                       # Number of load instructions
system.cpu0.num_store_insts                  18989834                       # Number of store instructions
system.cpu0.num_idle_cycles              5477713409.888090                       # Number of idle cycles
system.cpu0.num_busy_cycles              256145102.111911                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.044672                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.955328                       # Percentage of idle cycles
system.cpu0.Branches                         28216928                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2272      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 94734127     68.43%     68.43% # Class of executed instruction
system.cpu0.op_class::IntMult                  104105      0.08%     68.51% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              7381      0.01%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::MemRead                24600281     17.77%     86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               18989834     13.72%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 138438000                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    2074                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements          1061133                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.483144                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          114013070                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1061645                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           107.392838                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      12807152500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.483144                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998991                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998991                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        231211102                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       231211102                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    114013070                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      114013070                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    114013070                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       114013070                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    114013070                       # number of overall hits
system.cpu0.icache.overall_hits::total      114013070                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1061654                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1061654                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1061654                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1061654                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1061654                       # number of overall misses
system.cpu0.icache.overall_misses::total      1061654                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9000777256                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   9000777256                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   9000777256                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   9000777256                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   9000777256                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   9000777256                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    115074724                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115074724                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    115074724                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115074724                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    115074724                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115074724                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009226                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009226                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009226                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009226                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009226                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009226                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8478.070309                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8478.070309                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8478.070309                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8478.070309                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8478.070309                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8478.070309                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1061654                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1061654                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1061654                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1061654                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1061654                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1061654                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   7407609744                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   7407609744                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   7407609744                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   7407609744                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   7407609744                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   7407609744                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    719278000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    719278000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    719278000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    719278000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009226                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009226                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009226                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6977.423665                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6977.423665                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6977.423665                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  6977.423665                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6977.423665                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  6977.423665                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      9923568                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       227909                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      9246862                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          529                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           49                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       448219                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       778472                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          358131                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16113.840521                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1936015                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          374364                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.171477                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6748.405331                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.298352                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.117074                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   799.968206                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1087.232896                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7475.818663                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.411890                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000140                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.048826                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.066359                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.456288                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.983511                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         7939                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8291                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           41                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          127                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1966                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4890                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          915                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2895                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4675                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          536                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.484558                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.506042                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        38026831                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       38026831                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         6990                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3189                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1045942                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       372788                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       1428909                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       483936                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       483936                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        10087                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        10087                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2033                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2033                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212805                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       212805                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         6990                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3189                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1045942                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       585593                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1641714                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         6990                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3189                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1045942                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       585593                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1641714                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          263                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          219                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        15712                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        83577                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        99771                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        29878                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        29878                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19321                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19321                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            7                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44921                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44921                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          263                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          219                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        15712                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       128498                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       144692                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          263                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          219                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        15712                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       128498                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       144692                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      6061000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4899500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    598206723                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2260687668                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   2869854891                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    524614292                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    524614292                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    377658880                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    377658880                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1333497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1333497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1506710587                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1506710587                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      6061000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4899500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst    598206723                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   3767398255                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   4376565478                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      6061000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4899500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst    598206723                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   3767398255                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   4376565478                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7253                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3408                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1061654                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       456365                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      1528680                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       483936                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       483936                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        39965                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        39965                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21354                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        21354                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       257726                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       257726                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7253                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3408                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1061654                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       714091                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1786406                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7253                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3408                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1061654                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       714091                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1786406                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.036261                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.064261                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.014800                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.183136                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.065266                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.747604                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.747604                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.904795                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.904795                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.174298                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174298                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.036261                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.064261                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.014800                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.179946                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.080996                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.036261                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.064261                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.014800                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.179946                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.080996                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23045.627376                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22372.146119                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38073.238480                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27049.160271                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28764.419430                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17558.547828                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17558.547828                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19546.549350                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.549350                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 190499.571429                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 190499.571429                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33541.341177                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33541.341177                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23045.627376                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22372.146119                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38073.238480                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29318.730681                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 30247.459970                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23045.627376                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22372.146119                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38073.238480                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29318.730681                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 30247.459970                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         5815                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              76                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    76.513158                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       205462                       # number of writebacks
system.cpu0.l2cache.writebacks::total          205462                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         2206                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         2737                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         4943                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1219                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1219                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         2206                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3956                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6162                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         2206                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3956                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6162                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          263                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          219                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        13506                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        80840                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        94828                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       448214                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       448214                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        29878                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        29878                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19321                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19321                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43702                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43702                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          263                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          219                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        13506                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       124542                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       138530                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          263                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          219                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        13506                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       124542                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       448214                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       586744                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4219000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3366500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    457538021                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   1656533968                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2121657489                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17785493022                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17785493022                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    490939499                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    490939499                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    261550596                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    261550596                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1060497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1060497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1074359119                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1074359119                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4219000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3366500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    457538021                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   2730893087                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   3196016608                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4219000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3366500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    457538021                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   2730893087                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17785493022                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  20981509630                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    647388500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5328873750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5976262250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3987021005                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3987021005                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    647388500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9315894755                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9963283255                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.036261                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.064261                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012722                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.177139                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.062033                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.747604                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.747604                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.904795                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.904795                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.169568                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.169568                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.036261                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.064261                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012722                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.174406                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.077547                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.036261                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.064261                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012722                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.174406                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.328449                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 33876.648971                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20491.513706                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22373.744980                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39680.806539                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16431.471283                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16431.471283                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13537.114849                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13537.114849                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 151499.571429                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 151499.571429                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24583.751750                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24583.751750                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33876.648971                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21927.487008                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23070.934873                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16041.825095                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15372.146119                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33876.648971                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21927.487008                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39680.806539                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35759.223154                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           658799                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          485.164758                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           41683742                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           659311                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            63.223186                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1016179000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.164758                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.947587                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.947587                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         85573160                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        85573160                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     23155425                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23155425                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17431620                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17431620                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       323179                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       323179                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       358328                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       358328                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       353864                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       353864                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     40587045                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        40587045                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     40910224                       # number of overall hits
system.cpu0.dcache.overall_hits::total       40910224                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       360428                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       360428                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       297691                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       297691                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       106192                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       106192                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21416                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21416                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21370                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21370                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       658119                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        658119                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       764311                       # number of overall misses
system.cpu0.dcache.overall_misses::total       764311                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4473033768                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4473033768                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4445222415                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4445222415                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    335592501                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    335592501                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    473344116                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    473344116                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1450500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1450500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8918256183                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   8918256183                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8918256183                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   8918256183                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     23515853                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23515853                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17729311                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17729311                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       429371                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       429371                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       379744                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       379744                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       375234                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       375234                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     41245164                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     41245164                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     41674535                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     41674535                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.015327                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.015327                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016791                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.016791                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.247320                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.247320                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056396                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056396                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056951                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056951                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.015956                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.015956                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018340                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018340                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12410.339286                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12410.339286                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14932.337273                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14932.337273                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15670.176550                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15670.176550                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22149.935236                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22149.935236                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13551.130089                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13551.130089                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11668.360370                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11668.360370                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       483937                       # number of writebacks
system.cpu0.dcache.writebacks::total           483937                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7364                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total         7364                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15075                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15075                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data         7364                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total         7364                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data         7364                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total         7364                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       353064                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       353064                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       297691                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       297691                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        96960                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        96960                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6341                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6341                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21361                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        21361                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       650755                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       650755                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       747715                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       747715                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3674066732                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3674066732                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3839615585                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3839615585                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1190903244                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1190903244                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     89864249                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89864249                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    429815884                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    429815884                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1372500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1372500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7513682317                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7513682317                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8704585561                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   8704585561                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5564939750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5564939750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4183945995                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4183945995                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9748885745                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9748885745                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015014                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015014                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016791                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.016791                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225819                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225819                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016698                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016698                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056927                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056927                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015778                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015778                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.017942                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.017942                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10406.234371                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10406.234371                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12897.990148                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12897.990148                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12282.417946                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12282.417946                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14171.936445                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14171.936445                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20121.524460                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20121.524460                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11546.100018                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11546.100018                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11641.582101                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11641.582101                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       1734717                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1628862                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        26256                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26256                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       483936                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       598763                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        81012                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43653                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       101651                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       279403                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       269117                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2141354                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2250253                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9809                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        20976                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          4422392                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     67981948                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80932636                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        29012                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         148957228                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     991588                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3219253                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.272771                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.445384                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           2341135     72.72%     72.72% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            878118     27.28%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3219253                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1700320883                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115643997                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1603955756                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1150860061                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6401000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     13723500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4827395                       # DTB read hits
system.cpu1.dtb.read_misses                      2744                       # DTB read misses
system.cpu1.dtb.write_hits                    4131070                       # DTB write hits
system.cpu1.dtb.write_misses                      524                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2012                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   437                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4830139                       # DTB read accesses
system.cpu1.dtb.write_accesses                4131594                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          8958465                       # DTB hits
system.cpu1.dtb.misses                           3268                       # DTB misses
system.cpu1.dtb.accesses                      8961733                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    20889672                       # ITB inst hits
system.cpu1.itb.inst_misses                      1747                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1149                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20891419                       # ITB inst accesses
system.cpu1.itb.hits                         20889672                       # DTB hits
system.cpu1.itb.misses                           1747                       # DTB misses
system.cpu1.itb.accesses                     20891419                       # DTB accesses
system.cpu1.numCycles                      5732950771                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   20508829                       # Number of instructions committed
system.cpu1.committedOps                     24874782                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             22190598                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
system.cpu1.num_func_calls                    1209607                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2572400                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    22190598                       # number of integer instructions
system.cpu1.num_fp_insts                         1792                       # number of float instructions
system.cpu1.num_int_register_reads           39855869                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          15449003                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            90462747                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            8862782                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      9247846                       # number of memory refs
system.cpu1.num_load_insts                    4946569                       # Number of load instructions
system.cpu1.num_store_insts                   4301277                       # Number of store instructions
system.cpu1.num_idle_cycles              5671538888.273010                       # Number of idle cycles
system.cpu1.num_busy_cycles              61411882.726990                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010712                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989288                       # Percentage of idle cycles
system.cpu1.Branches                          3892747                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   67      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 16017837     63.30%     63.30% # Class of executed instruction
system.cpu1.op_class::IntMult                   33571      0.13%     63.44% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4039      0.02%     63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.45% # Class of executed instruction
system.cpu1.op_class::MemRead                 4946569     19.55%     83.00% # Class of executed instruction
system.cpu1.op_class::MemWrite                4301277     17.00%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  25303360                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2751                       # number of quiesce instructions executed
system.cpu1.icache.tags.replacements           565233                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.685358                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           20323921                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           565745                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            35.924173                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     115078716000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.685358                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973995                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973995                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          400                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          109                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         42345080                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        42345080                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     20323921                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       20323921                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     20323921                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        20323921                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     20323921                       # number of overall hits
system.cpu1.icache.overall_hits::total       20323921                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       565746                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       565746                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       565746                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        565746                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       565746                       # number of overall misses
system.cpu1.icache.overall_misses::total       565746                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4684636281                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4684636281                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4684636281                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4684636281                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4684636281                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4684636281                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     20889667                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     20889667                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     20889667                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     20889667                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     20889667                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     20889667                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.027083                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.027083                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.027083                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.027083                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.027083                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.027083                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8280.458511                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8280.458511                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8280.458511                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8280.458511                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8280.458511                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8280.458511                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       565746                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       565746                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       565746                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       565746                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       565746                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       565746                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3835844219                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3835844219                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3835844219                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3835844219                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3835844219                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3835844219                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14025750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14025750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14025750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     14025750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027083                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027083                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027083                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.027083                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027083                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.027083                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6780.152611                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6780.152611                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6780.152611                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6780.152611                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6780.152611                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6780.152611                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4613211                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        23452                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4471751                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          253                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           21                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       117734                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       522133                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements           85099                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15602.150946                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            830949                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs          100297                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.284884                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    2855978416500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  4730.109881                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     5.755019                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.314200                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   871.040386                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1529.848587                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  8465.082873                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.288703                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000351                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000019                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.053164                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.093375                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.516668                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.952280                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9308                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5882                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           64                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         1130                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         8114                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1134                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4474                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.568115                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.359009                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        16690228                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       16690228                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3013                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1699                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       560147                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       123235                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        688094                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       134926                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       134926                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1530                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1530                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          889                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          889                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        39290                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        39290                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3013                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1699                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       560147                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       162525                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         727384                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3013                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1699                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       560147                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       162525                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        727384                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          347                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          282                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5599                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        70297                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        76525                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29432                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29432                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22334                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22334                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33500                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        33500                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          347                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          282                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         5599                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       103797                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       110025                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          347                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          282                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         5599                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       103797                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       110025                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      7263500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5687750                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    191326469                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1549353898                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1753631617                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    537113129                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    537113129                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    436542574                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    436542574                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1696500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1696500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1074535378                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1074535378                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      7263500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5687750                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    191326469                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2623889276                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   2828166995                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      7263500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5687750                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    191326469                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2623889276                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   2828166995                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3360                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1981                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       565746                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       193532                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       764619                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       134926                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       134926                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30962                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30962                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23223                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23223                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        72790                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        72790                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3360                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1981                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       565746                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       266322                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       837409                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3360                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1981                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       565746                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       266322                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       837409                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.103274                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.142352                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009897                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.363232                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.100083                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950585                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950585                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.961719                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.961719                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.460228                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.460228                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.103274                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.142352                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009897                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.389742                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.131387                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.103274                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.142352                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009897                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.389742                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.131387                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20932.276657                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20169.326241                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34171.542954                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22040.114059                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22915.800287                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18249.290874                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18249.290874                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19546.098952                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19546.098952                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       565500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       565500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 32075.682925                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 32075.682925                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20932.276657                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20169.326241                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34171.542954                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25279.047333                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 25704.767053                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20932.276657                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20169.326241                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34171.542954                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25279.047333                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 25704.767053                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         1025                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              35                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    29.285714                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        35099                       # number of writebacks
system.cpu1.l2cache.writebacks::total           35099                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          685                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           96                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          781                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          214                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          214                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          685                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          310                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          995                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          685                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          310                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          995                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          347                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          282                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         4914                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        70201                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        75744                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       117733                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       117733                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29432                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29432                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22334                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22334                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33286                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        33286                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          347                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          282                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4914                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103487                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       109030                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          347                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          282                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4914                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103487                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       117733                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       226763                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4833500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3713250                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    143751774                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1055636432                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1207934956                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3298666709                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3298666709                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    431077198                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    431077198                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    306544179                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306544179                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1430500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1430500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    820609092                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    820609092                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4833500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3713250                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    143751774                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   1876245524                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2028544048                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4833500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3713250                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    143751774                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   1876245524                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3298666709                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   5327210757                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12612250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    916010500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    928622750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    796474001                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    796474001                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12612250                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1712484501                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1725096751                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.103274                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.142352                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.008686                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.362736                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.099061                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950585                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950585                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.961719                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.961719                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.457288                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.457288                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.103274                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.142352                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.008686                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.388578                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.130199                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.103274                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.142352                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.008686                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.388578                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.270791                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29253.515263                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15037.341804                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15947.599229                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 28018.199732                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14646.547907                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14646.547907                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13725.449046                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13725.449046                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 476833.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 476833.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24653.280418                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24653.280418                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29253.515263                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18130.253307                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18605.375108                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13929.394813                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13167.553191                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29253.515263                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18130.253307                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 28018.199732                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23492.416122                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           218932                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          479.958616                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            8645395                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           219287                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            39.425023                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     104115576500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   479.958616                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.937419                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.937419                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          298                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           57                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.693359                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         18161929                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        18161929                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      4463105                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        4463105                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3919326                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3919326                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        64192                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        64192                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87200                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        87200                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79632                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        79632                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      8382431                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         8382431                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      8446623                       # number of overall hits
system.cpu1.dcache.overall_hits::total        8446623                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       155171                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       155171                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       103752                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       103752                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34196                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        34196                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17931                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17931                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23276                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23276                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       258923                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        258923                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       293119                       # number of overall misses
system.cpu1.dcache.overall_misses::total       293119                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2220270266                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2220270266                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2272762314                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2272762314                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325809000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    325809000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    538454705                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    538454705                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1810500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1810500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4493032580                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4493032580                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4493032580                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4493032580                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      4618276                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4618276                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4023078                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4023078                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        98388                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        98388                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105131                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       105131                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102908                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       102908                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      8641354                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      8641354                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      8739742                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      8739742                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.033599                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.033599                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.025789                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.025789                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.347563                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.347563                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.170559                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.170559                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.226183                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.226183                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029963                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.029963                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033539                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.033539                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14308.538748                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14308.538748                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21905.720507                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21905.720507                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18170.152250                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18170.152250                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23133.472461                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23133.472461                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17352.775072                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17352.775072                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15328.356674                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15328.356674                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       134926                       # number of writebacks
system.cpu1.dcache.writebacks::total           134926                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          299                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          299                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12328                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12328                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          299                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          299                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          299                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          299                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       154872                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       154872                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       103752                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       103752                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33057                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        33057                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5603                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5603                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23226                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23226                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       258624                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       258624                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       291681                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       291681                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1901749734                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1901749734                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2059007686                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2059007686                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    496678249                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    496678249                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84335500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     84335500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    490783295                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    490783295                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1734500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1734500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3960757420                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3960757420                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4457435669                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4457435669                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    961034499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    961034499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    833382499                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    833382499                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1794416998                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1794416998                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033535                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033535                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025789                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025789                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.335986                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.335986                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.053295                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053295                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225697                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225697                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029929                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029929                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033374                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033374                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12279.493608                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12279.493608                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19845.474651                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19845.474651                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15024.903924                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15024.903924                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15051.847225                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15051.847225                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21130.771334                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21130.771334                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15314.732662                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15314.732662                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15281.885584                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15281.885584                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1206103                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       816776                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         4921                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         4921                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       134926                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       169865                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        86284                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42512                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        89712                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        91056                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        78188                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1131848                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       880488                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5306                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9281                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2026923                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     36208456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     28775795                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7924                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          65005615                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     818131                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1761210                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.414931                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.492710                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1030430     58.51%     58.51% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            730780     41.49%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1761210                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     658102724                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     89600499                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    848922781                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    438669538                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3325250                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      5921500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36443                       # number of replacements
system.iocache.tags.tagsinuse               14.446814                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36459                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         277160524000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.446814                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.902926                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.902926                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328549                       # Number of tag accesses
system.iocache.tags.data_accesses              328549                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          253                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              253                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           32                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           32                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          253                       # number of demand (read+write) misses
system.iocache.demand_misses::total               253                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          253                       # number of overall misses
system.iocache.overall_misses::total              253                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31609377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31609377                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31609377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31609377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31609377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31609377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          253                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            253                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36256                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36256                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          253                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             253                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          253                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            253                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000883                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000883                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124938.249012                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124938.249012                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124938.249012                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      36224                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide          253                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          253                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          253                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          253                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          253                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          253                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18452377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18452377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2247085536                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2247085536                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18452377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18452377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18452377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18452377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------