path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.182882                       # Number of seconds simulated
sim_ticks                                1182882156500                       # Number of ticks simulated
final_tick                               1182882156500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 184229                       # Simulator instruction rate (inst/s)
host_op_rate                                   234741                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             3546252898                       # Simulator tick rate (ticks/s)
host_mem_usage                                 402168                       # Number of bytes of host memory used
host_seconds                                   333.56                       # Real time elapsed on the host
sim_insts                                    61450993                       # Number of instructions simulated
sim_ops                                      78299715                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           41                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           41                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           41                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           393572                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4715764                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           323164                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4806320                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62143780                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       393572                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       323164                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          716736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4114688                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7142032                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             12368                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             73756                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5131                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             75125                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6654451                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           64292                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               821128                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43879698                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           108                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              332723                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3986673                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           216                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              273201                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4063228                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52535901                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         332723                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         273201                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             605923                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3478527                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              14372                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2544923                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6037822                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3478527                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43879698                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          108                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             332723                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            4001044                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          216                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             273201                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            6608151                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               58573723                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6654451                       # Total number of read requests seen
system.physmem.writeReqs                       821128                       # Total number of write requests seen
system.physmem.cpureqs                         272784                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                    425884864                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52552192                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               62143780                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7142032                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      132                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite              11751                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                415571                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                415750                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                415458                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                415468                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                415552                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                415207                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                415303                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                415263                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                422360                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                415431                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               415464                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               415652                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               415419                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               415645                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               415452                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               415324                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                 50727                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                 50837                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                 50611                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 50656                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                 51686                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                 51413                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                 51505                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 51451                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                 51696                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                 51531                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                51439                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                51528                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                51471                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                51659                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                51507                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                51411                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1182877668000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                    6825                       # Categorize read packet sizes
system.physmem.readPktSize::3                 6488064                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  159562                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                 756836                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  64292                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                11751                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    574129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    411417                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    411845                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    427327                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1182593                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1193140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2312606                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     25343                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15031                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     14611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    14622                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    26114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    14563                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    25574                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     2767                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     2575                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       62                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     35697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     35702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     35702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     35702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    35701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                   123719908904                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              159121708904                       # Sum of mem lat for all requests
system.physmem.totBusLat                  26617276000                       # Total cycles spent in databus access
system.physmem.totBankLat                  8784524000                       # Total cycles spent in bank access
system.physmem.avgQLat                       18592.42                       # Average queueing delay per request
system.physmem.avgBankLat                     1320.12                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  23912.55                       # Average memory access latency
system.physmem.avgRdBW                         360.04                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          44.43                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  52.54                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.04                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           2.53                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.13                       # Average read queue length over time
system.physmem.avgWrQLen                        15.12                       # Average write queue length over time
system.physmem.readRowHits                    6628163                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    789308                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  96.12                       # Row buffer hit rate for writes
system.physmem.avgGap                       158232.25                       # Average gap between requests
system.l2c.replacements                         69442                       # number of replacements
system.l2c.tagsinuse                     53039.972087                       # Cycle average of tags in use
system.l2c.total_refs                         1672967                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        134589                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         12.430191                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        40188.045356                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       0.000405                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.001414                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          3727.182104                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          4237.001170                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker       2.742163                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          2823.633866                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          2061.365608                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.613221                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.056872                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.064652                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000042                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.043085                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.031454                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.809326                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         4055                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         1843                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             419673                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             206158                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5342                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1844                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             464150                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             143311                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1246376                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          571308                       # number of Writeback hits
system.l2c.Writeback_hits::total               571308                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1277                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             564                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1841                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           215                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           104                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               319                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            56678                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            52482                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109160                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4055                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          1843                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              419673                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              262836                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5342                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1844                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              464150                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              195793                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1355536                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4055                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         1843                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             419673                       # number of overall hits
system.l2c.overall_hits::cpu0.data             262836                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5342                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1844                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             464150                       # number of overall hits
system.l2c.overall_hits::cpu1.data             195793                       # number of overall hits
system.l2c.overall_hits::total                1355536                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             5736                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             7863                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             5044                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             3621                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22271                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          4685                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3595                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8280                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          564                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          469                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1033                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          67153                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72577                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139730                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5736                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             75016                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5044                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             76198                       # number of demand (read+write) misses
system.l2c.demand_misses::total                162001                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5736                       # number of overall misses
system.l2c.overall_misses::cpu0.data            75016                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5044                       # number of overall misses
system.l2c.overall_misses::cpu1.data            76198                       # number of overall misses
system.l2c.overall_misses::total               162001                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        69000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        67500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    282793000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    402090500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       247500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    256949000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    210391000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1152607500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     12566496                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     11726999                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     24293495                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1712000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2362500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      4074500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   2978330461                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3439869494                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6418199955                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker        69000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        67500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    282793000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3380420961                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       247500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    256949000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   3650260494                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      7570807455                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker        69000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        67500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    282793000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3380420961                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       247500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    256949000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   3650260494                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     7570807455                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         4056                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         1845                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         425409                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         214021                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5346                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1844                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         469194                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         146932                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1268647                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       571308                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           571308                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         5962                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4159                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10121                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          779                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          573                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1352                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       123831                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       125059                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           248890                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         4056                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         1845                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          425409                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          337852                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5346                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1844                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          469194                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          271991                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1517537                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         4056                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         1845                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         425409                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         337852                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5346                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1844                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         469194                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         271991                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1517537                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000247                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001084                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013483                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036739                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000748                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010750                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.024644                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017555                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.785810                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.864390                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.818101                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.724005                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.818499                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.764053                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.542296                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.580342                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.561413                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000247                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.001084                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013483                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.222038                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000748                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010750                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.280149                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.106753                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000247                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.001084                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013483                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.222038                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000748                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010750                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.280149                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.106753                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        69000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        33750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 49301.429568                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 51137.034211                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        61875                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50941.514671                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 58103.010218                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 51753.738045                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2682.283031                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3262.030320                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2933.996981                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3035.460993                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5037.313433                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3944.336883                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 44351.413355                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 47396.137812                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 45932.870214                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        69000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        33750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 49301.429568                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 45062.666111                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        61875                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 50941.514671                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 47904.938371                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 46733.090876                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        69000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        33750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 49301.429568                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 45062.666111                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        61875                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 50941.514671                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 47904.938371                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 46733.090876                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               64292                       # number of writebacks
system.l2c.writebacks::total                    64292                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         5735                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         7863                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         5044                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         3621                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22270                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         4685                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3595                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8280                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          564                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          469                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1033                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        67153                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72577                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139730                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         5735                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        75016                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5044                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        76198                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           162000                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         5735                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        75016                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5044                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        76198                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          162000                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        56002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        42004                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    209968387                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    301307132                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       196008                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    192920490                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    164158147                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    868648170                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     47014106                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     36048563                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     83062669                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5661057                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4707461                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10368518                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2133484234                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2513381312                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4646865546                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        56002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        42004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    209968387                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2434791366                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       196008                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    192920490                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2677539459                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   5515513716                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        56002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        42004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    209968387                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2434791366                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       196008                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    192920490                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2677539459                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   5515513716                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    197971583                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12453767609                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3031674                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154319820043                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 166974590909                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1000478250                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8214527645                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   9215005895                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    197971583                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13454245859                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3031674                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162534347688                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 176189596804                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000247                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001084                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013481                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036739                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000748                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010750                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024644                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017554                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785810                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.864390                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.818101                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.724005                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.818499                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.764053                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.542296                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.580342                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.561413                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000247                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001084                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013481                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.222038                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000748                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010750                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.280149                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.106752                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000247                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001084                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013481                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.222038                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000748                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010750                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.280149                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.106752                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        56002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        21002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36611.750131                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38319.614905                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        49002                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38247.519826                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45335.030931                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 39005.306242                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.027962                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.416690                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.723309                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.335106                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.230277                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10037.287512                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31770.497729                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34630.548411                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33256.033393                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        56002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        21002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36611.750131                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32456.960728                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        49002                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38247.519826                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 34046.380963                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        56002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        21002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        49002                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 34046.380963                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7070111                       # DTB read hits
system.cpu0.dtb.read_misses                      3764                       # DTB read misses
system.cpu0.dtb.write_hits                    5656042                       # DTB write hits
system.cpu0.dtb.write_misses                      804                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1807                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   143                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 7073875                       # DTB read accesses
system.cpu0.dtb.write_accesses                5656846                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         12726153                       # DTB hits
system.cpu0.dtb.misses                           4568                       # DTB misses
system.cpu0.dtb.accesses                     12730721                       # DTB accesses
system.cpu0.itb.inst_hits                    29570310                       # ITB inst hits
system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1332                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                29572515                       # ITB inst accesses
system.cpu0.itb.hits                         29570310                       # DTB hits
system.cpu0.itb.misses                           2205                       # DTB misses
system.cpu0.itb.accesses                     29572515                       # DTB accesses
system.cpu0.numCycles                      2365764313                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   28872367                       # Number of instructions committed
system.cpu0.committedOps                     37211047                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             33098187                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
system.cpu0.num_func_calls                    1241715                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4373222                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    33098187                       # number of integer instructions
system.cpu0.num_fp_insts                         3860                       # number of float instructions
system.cpu0.num_int_register_reads          190047206                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          36225366                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     13394441                       # number of memory refs
system.cpu0.num_load_insts                    7407672                       # Number of load instructions
system.cpu0.num_store_insts                   5986769                       # Number of store instructions
system.cpu0.num_idle_cycles              2224997657.358119                       # Number of idle cycles
system.cpu0.num_busy_cycles              140766655.641881                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.059502                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.940498                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   46700                       # number of quiesce instructions executed
system.cpu0.icache.replacements                425445                       # number of replacements
system.cpu0.icache.tagsinuse               509.616014                       # Cycle average of tags in use
system.cpu0.icache.total_refs                29144335                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                425957                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 68.420838                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           74931906000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   509.616014                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.995344                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.995344                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     29144335                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       29144335                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     29144335                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        29144335                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     29144335                       # number of overall hits
system.cpu0.icache.overall_hits::total       29144335                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       425958                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       425958                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       425958                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        425958                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       425958                       # number of overall misses
system.cpu0.icache.overall_misses::total       425958                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5792188000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5792188000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5792188000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5792188000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5792188000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5792188000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     29570293                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     29570293                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     29570293                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     29570293                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     29570293                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     29570293                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014405                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014405                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014405                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014405                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014405                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014405                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13598.026096                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13598.026096                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425958                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       425958                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       425958                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       425958                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       425958                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       425958                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4940272000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   4940272000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4940272000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   4940272000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4940272000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   4940272000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    288882000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    288882000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    288882000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    288882000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014405                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014405                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014405                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014405                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014405                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014405                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                330355                       # number of replacements
system.cpu0.dcache.tagsinuse               453.331528                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                12270860                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                330867                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 37.086987                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle             462692000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   453.331528                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.885413                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.885413                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      6599943                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6599943                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5351121                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5351121                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147941                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       147941                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149661                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       149661                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11951064                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11951064                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11951064                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11951064                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       227863                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       227863                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       141515                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       141515                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9301                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9301                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7492                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7492                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       369378                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        369378                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       369378                       # number of overall misses
system.cpu0.dcache.overall_misses::total       369378                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3130112000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   3130112000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4103795500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4103795500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     87984000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     87984000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44508500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     44508500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   7233907500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   7233907500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   7233907500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   7233907500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6827806                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6827806                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5492636                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5492636                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157242                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       157242                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157153                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       157153                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12320442                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12320442                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12320442                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12320442                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033373                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.033373                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025764                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.025764                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059151                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059151                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047673                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047673                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029981                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.029981                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029981                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029981                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9459.627997                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9459.627997                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5940.803524                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5940.803524                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19584.023683                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19584.023683                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19584.023683                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 19584.023683                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       306206                       # number of writebacks
system.cpu0.dcache.writebacks::total           306206                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227863                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       227863                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141515                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       141515                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9301                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9301                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7489                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7489                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       369378                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       369378                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       369378                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       369378                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2674386000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2674386000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3820765500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3820765500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69382000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69382000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29532500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29532500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6495151500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   6495151500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6495151500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   6495151500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13561363000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13561363000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1128479500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1128479500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14689842500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14689842500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033373                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033373                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025764                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025764                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059151                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059151                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047654                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047654                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029981                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029981                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029981                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029981                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7459.627997                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7459.627997                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3943.450394                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3943.450394                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     8310545                       # DTB read hits
system.cpu1.dtb.read_misses                      3643                       # DTB read misses
system.cpu1.dtb.write_hits                    5827351                       # DTB write hits
system.cpu1.dtb.write_misses                     1434                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1965                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   140                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 8314188                       # DTB read accesses
system.cpu1.dtb.write_accesses                5828785                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         14137896                       # DTB hits
system.cpu1.dtb.misses                           5077                       # DTB misses
system.cpu1.dtb.accesses                     14142973                       # DTB accesses
system.cpu1.itb.inst_hits                    33189113                       # ITB inst hits
system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1495                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                33191284                       # ITB inst accesses
system.cpu1.itb.hits                         33189113                       # DTB hits
system.cpu1.itb.misses                           2171                       # DTB misses
system.cpu1.itb.accesses                     33191284                       # DTB accesses
system.cpu1.numCycles                      2364318212                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   32578626                       # Number of instructions committed
system.cpu1.committedOps                     41088668                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             37313171                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
system.cpu1.num_func_calls                     962009                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3732639                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    37313171                       # number of integer instructions
system.cpu1.num_fp_insts                         6793                       # number of float instructions
system.cpu1.num_int_register_reads          213663418                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          39454743                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
system.cpu1.num_mem_refs                     14675641                       # number of memory refs
system.cpu1.num_load_insts                    8632449                       # Number of load instructions
system.cpu1.num_store_insts                   6043192                       # Number of store instructions
system.cpu1.num_idle_cycles              1868258895.232782                       # Number of idle cycles
system.cpu1.num_busy_cycles              496059316.767218                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.209811                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.790189                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   43883                       # number of quiesce instructions executed
system.cpu1.icache.replacements                469194                       # number of replacements
system.cpu1.icache.tagsinuse               478.783096                       # Cycle average of tags in use
system.cpu1.icache.total_refs                32719403                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                469706                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 69.659325                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           92023963500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   478.783096                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.935123                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.935123                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst     32719403                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       32719403                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     32719403                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        32719403                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     32719403                       # number of overall hits
system.cpu1.icache.overall_hits::total       32719403                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       469706                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       469706                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       469706                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        469706                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       469706                       # number of overall misses
system.cpu1.icache.overall_misses::total       469706                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6343605000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   6343605000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   6343605000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   6343605000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   6343605000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   6343605000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     33189109                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     33189109                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     33189109                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     33189109                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     33189109                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     33189109                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014152                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014152                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014152                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014152                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014152                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014152                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13505.480024                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13505.480024                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       469706                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       469706                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       469706                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       469706                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       469706                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       469706                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5404193000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5404193000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5404193000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5404193000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5404193000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5404193000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      4406000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      4406000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      4406000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      4406000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014152                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014152                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014152                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.014152                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014152                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.014152                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                292054                       # number of replacements
system.cpu1.dcache.tagsinuse               471.972808                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                11961234                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                292426                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 40.903456                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           83625409000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   471.972808                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.921822                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.921822                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      6946091                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        6946091                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4827134                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4827134                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81752                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        81752                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82714                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        82714                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     11773225                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        11773225                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     11773225                       # number of overall hits
system.cpu1.dcache.overall_hits::total       11773225                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       170515                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       170515                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       149924                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       149924                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11068                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        11068                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10031                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10031                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       320439                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        320439                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       320439                       # number of overall misses
system.cpu1.dcache.overall_misses::total       320439                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2149232000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2149232000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4527081500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   4527081500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     92245500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     92245500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     51683000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     51683000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   6676313500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   6676313500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   6676313500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   6676313500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      7116606                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      7116606                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4977058                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4977058                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92820                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        92820                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92745                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        92745                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     12093664                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     12093664                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     12093664                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     12093664                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023960                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.023960                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030123                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030123                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119242                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119242                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108157                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108157                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026496                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.026496                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026496                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.026496                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8334.432598                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8334.432598                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5152.327784                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5152.327784                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20834.896813                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       265102                       # number of writebacks
system.cpu1.dcache.writebacks::total           265102                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170515                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       170515                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       149924                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       149924                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11068                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11068                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10026                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10026                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       320439                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       320439                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       320439                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       320439                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1808202000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1808202000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4227233500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4227233500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     70109500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     70109500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31633000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31633000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6035435500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   6035435500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6035435500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   6035435500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  17673871500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  17673871500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023960                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023960                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030123                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030123                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119242                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119242                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108103                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108103                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026496                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026496                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026496                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026496                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6334.432598                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6334.432598                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3155.096748                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3155.096748                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 479634051298                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------