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|
---------- Begin Simulation Statistics ----------
sim_seconds 1.195756 # Number of seconds simulated
sim_ticks 1195756323500 # Number of ticks simulated
final_tick 1195756323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 469394 # Simulator instruction rate (inst/s)
host_op_rate 598174 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9145402965 # Simulator tick rate (ticks/s)
host_mem_usage 398732 # Number of bytes of host memory used
host_seconds 130.75 # Real time elapsed on the host
sim_insts 61373013 # Number of instructions simulated
sim_ops 78210923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 463908 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 6634996 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 256412 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2903984 # Number of bytes read from this memory
system.physmem.bytes_read::total 62164260 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 463908 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 256412 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 720320 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4143232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 7170576 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 13467 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 103744 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 4088 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 45401 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6654771 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 64738 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 821574 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 43407265 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 387962 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 5548786 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 214435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2428575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51987398 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 387962 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 214435 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 602397 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3464947 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 2531706 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 5996687 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3464947 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 43407265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 387962 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 8080492 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 214435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2428609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 57984085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 6654771 # Number of read requests accepted
system.physmem.writeReqs 821574 # Number of write requests accepted
system.physmem.readBursts 6654771 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 821574 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 425880832 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 24512 # Total number of bytes read from write queue
system.physmem.bytesWritten 7300224 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 62164260 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7170576 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 383 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 707506 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 10656 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 415729 # Per bank write bursts
system.physmem.perBankRdBursts::1 415559 # Per bank write bursts
system.physmem.perBankRdBursts::2 414962 # Per bank write bursts
system.physmem.perBankRdBursts::3 415336 # Per bank write bursts
system.physmem.perBankRdBursts::4 422370 # Per bank write bursts
system.physmem.perBankRdBursts::5 415375 # Per bank write bursts
system.physmem.perBankRdBursts::6 415451 # Per bank write bursts
system.physmem.perBankRdBursts::7 415289 # Per bank write bursts
system.physmem.perBankRdBursts::8 415350 # Per bank write bursts
system.physmem.perBankRdBursts::9 415631 # Per bank write bursts
system.physmem.perBankRdBursts::10 415265 # Per bank write bursts
system.physmem.perBankRdBursts::11 414898 # Per bank write bursts
system.physmem.perBankRdBursts::12 415464 # Per bank write bursts
system.physmem.perBankRdBursts::13 416088 # Per bank write bursts
system.physmem.perBankRdBursts::14 415829 # Per bank write bursts
system.physmem.perBankRdBursts::15 415792 # Per bank write bursts
system.physmem.perBankWrBursts::0 7314 # Per bank write bursts
system.physmem.perBankWrBursts::1 7200 # Per bank write bursts
system.physmem.perBankWrBursts::2 6696 # Per bank write bursts
system.physmem.perBankWrBursts::3 6864 # Per bank write bursts
system.physmem.perBankWrBursts::4 7395 # Per bank write bursts
system.physmem.perBankWrBursts::5 6961 # Per bank write bursts
system.physmem.perBankWrBursts::6 7170 # Per bank write bursts
system.physmem.perBankWrBursts::7 6990 # Per bank write bursts
system.physmem.perBankWrBursts::8 6985 # Per bank write bursts
system.physmem.perBankWrBursts::9 7249 # Per bank write bursts
system.physmem.perBankWrBursts::10 6972 # Per bank write bursts
system.physmem.perBankWrBursts::11 6687 # Per bank write bursts
system.physmem.perBankWrBursts::12 7224 # Per bank write bursts
system.physmem.perBankWrBursts::13 7527 # Per bank write bursts
system.physmem.perBankWrBursts::14 7429 # Per bank write bursts
system.physmem.perBankWrBursts::15 7403 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1195751937000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 6825 # Read request sizes (log2)
system.physmem.readPktSize::3 6488064 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 159882 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 756836 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 64738 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 632405 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 479192 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 479926 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1578313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1129029 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1122994 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1119651 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 25389 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 24020 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 9298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 9280 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 9200 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 8958 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 8876 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 8828 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 8796 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 75043 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 5772.432765 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 392.553072 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 13030.260865 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71 26180 34.89% 34.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135 15268 20.35% 55.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199 3440 4.58% 59.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263 2311 3.08% 62.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327 1510 2.01% 64.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391 1328 1.77% 66.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455 1040 1.39% 68.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519 1132 1.51% 69.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583 816 1.09% 70.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647 593 0.79% 71.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711 586 0.78% 72.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775 709 0.94% 73.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839 314 0.42% 73.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903 269 0.36% 73.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967 220 0.29% 74.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031 291 0.39% 74.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095 182 0.24% 74.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159 143 0.19% 75.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223 140 0.19% 75.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287 157 0.21% 75.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415 2241 2.99% 78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479 115 0.15% 78.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543 232 0.31% 79.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607 71 0.09% 79.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671 55 0.07% 79.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735 54 0.07% 79.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799 56 0.07% 79.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863 28 0.04% 79.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927 28 0.04% 79.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991 21 0.03% 79.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055 107 0.14% 79.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119 143 0.19% 79.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183 11 0.01% 79.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247 15 0.02% 79.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311 43 0.06% 79.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375 9 0.01% 79.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439 16 0.02% 79.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503 18 0.02% 79.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567 98 0.13% 80.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631 8 0.01% 80.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695 10 0.01% 80.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759 12 0.02% 80.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823 36 0.05% 80.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887 9 0.01% 80.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951 5 0.01% 80.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015 10 0.01% 80.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079 168 0.22% 80.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143 11 0.01% 80.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207 9 0.01% 80.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271 4 0.01% 80.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335 161 0.21% 80.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463 6 0.01% 80.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591 16 0.02% 80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655 2 0.00% 80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719 6 0.01% 80.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783 30 0.04% 80.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847 86 0.11% 80.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911 3 0.00% 80.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039 9 0.01% 80.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103 188 0.25% 81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231 2 0.00% 81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295 2 0.00% 81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359 22 0.03% 81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487 1 0.00% 81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551 3 0.00% 81.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615 27 0.04% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679 2 0.00% 81.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743 2 0.00% 81.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807 4 0.01% 81.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871 207 0.28% 81.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999 1 0.00% 81.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063 13 0.02% 81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127 90 0.12% 81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319 1 0.00% 81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383 76 0.10% 81.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447 12 0.02% 81.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511 206 0.27% 82.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639 11 0.01% 82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703 1 0.00% 82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895 30 0.04% 82.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959 1 0.00% 82.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023 2 0.00% 82.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087 2 0.00% 82.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151 144 0.19% 82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215 2 0.00% 82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407 86 0.11% 82.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663 18 0.02% 82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727 1 0.00% 82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919 5 0.01% 82.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175 166 0.22% 82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431 24 0.03% 82.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687 69 0.09% 82.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8007 1 0.00% 82.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071 1 0.00% 82.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199 161 0.21% 83.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8327 2 0.00% 83.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455 26 0.03% 83.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711 70 0.09% 83.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967 24 0.03% 83.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095 2 0.00% 83.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223 167 0.22% 83.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479 10 0.01% 83.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735 21 0.03% 83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9863 1 0.00% 83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9927 1 0.00% 83.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991 83 0.11% 83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10055 1 0.00% 83.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247 148 0.20% 83.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10311 1 0.00% 83.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503 31 0.04% 83.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10567 1 0.00% 83.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10631 2 0.00% 83.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759 9 0.01% 83.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10951 1 0.00% 83.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015 75 0.10% 84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271 96 0.13% 84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527 79 0.11% 84.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783 29 0.04% 84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11975 1 0.00% 84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039 17 0.02% 84.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12167 1 0.00% 84.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295 176 0.23% 84.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551 83 0.11% 84.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807 12 0.02% 84.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12999 1 0.00% 84.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063 24 0.03% 84.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13255 1 0.00% 84.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319 154 0.21% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13447 2 0.00% 84.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575 30 0.04% 84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13639 1 0.00% 84.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831 90 0.12% 85.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959 1 0.00% 85.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087 16 0.02% 85.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343 91 0.12% 85.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14471 1 0.00% 85.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599 14 0.02% 85.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14663 1 0.00% 85.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14727 2 0.00% 85.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855 154 0.21% 85.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111 12 0.02% 85.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367 76 0.10% 85.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623 82 0.11% 85.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879 16 0.02% 85.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135 19 0.03% 85.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263 4 0.01% 85.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391 270 0.36% 86.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519 1 0.00% 86.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16583 1 0.00% 86.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647 20 0.03% 86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16768-16775 2 0.00% 86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903 17 0.02% 86.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159 84 0.11% 86.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415 77 0.10% 86.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671 12 0.02% 86.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17799 2 0.00% 86.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927 156 0.21% 86.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183 14 0.02% 86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247 1 0.00% 86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439 92 0.12% 86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18496-18503 1 0.00% 86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18560-18567 1 0.00% 86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695 12 0.02% 86.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951 95 0.13% 86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19079 1 0.00% 86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207 30 0.04% 86.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19264-19271 1 0.00% 86.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463 153 0.20% 87.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719 23 0.03% 87.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975 10 0.01% 87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20032-20039 1 0.00% 87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231 83 0.11% 87.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359 1 0.00% 87.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20416-20423 1 0.00% 87.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487 180 0.24% 87.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20544-20551 2 0.00% 87.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615 1 0.00% 87.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743 18 0.02% 87.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20800-20807 1 0.00% 87.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999 25 0.03% 87.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21184-21191 1 0.00% 87.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255 75 0.10% 87.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21440-21447 1 0.00% 87.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511 92 0.12% 87.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767 72 0.10% 87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21952-21959 1 0.00% 87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023 14 0.02% 87.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279 35 0.05% 87.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535 142 0.19% 88.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22656-22663 1 0.00% 88.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791 87 0.12% 88.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22912-22919 1 0.00% 88.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22976-22983 1 0.00% 88.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047 13 0.02% 88.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303 4 0.01% 88.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559 166 0.22% 88.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23616-23623 1 0.00% 88.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815 23 0.03% 88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071 66 0.09% 88.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327 30 0.04% 88.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455 1 0.00% 88.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583 147 0.20% 88.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839 27 0.04% 88.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095 68 0.09% 89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351 24 0.03% 89.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479 1 0.00% 89.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607 171 0.23% 89.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863 5 0.01% 89.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119 19 0.03% 89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26304-26311 1 0.00% 89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375 83 0.11% 89.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631 139 0.19% 89.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887 34 0.05% 89.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143 12 0.02% 89.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27264-27271 1 0.00% 89.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399 75 0.10% 89.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27456-27463 1 0.00% 89.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527 1 0.00% 89.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591 2 0.00% 89.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655 88 0.12% 89.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27776-27783 2 0.00% 89.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911 75 0.10% 89.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28096-28103 1 0.00% 89.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167 24 0.03% 90.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28352-28359 1 0.00% 90.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423 21 0.03% 90.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679 180 0.24% 90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28807 2 0.00% 90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935 82 0.11% 90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191 10 0.01% 90.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447 24 0.03% 90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29504-29511 1 0.00% 90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703 153 0.20% 90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29888-29895 1 0.00% 90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959 28 0.04% 90.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215 92 0.12% 90.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30336-30343 1 0.00% 90.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471 14 0.02% 90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727 87 0.12% 90.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983 12 0.02% 90.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31111 2 0.00% 90.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239 151 0.20% 91.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495 11 0.01% 91.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31552-31559 1 0.00% 91.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623 1 0.00% 91.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751 72 0.10% 91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007 84 0.11% 91.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135 1 0.00% 91.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263 15 0.02% 91.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32391 1 0.00% 91.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519 24 0.03% 91.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775 273 0.36% 91.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031 27 0.04% 91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33152-33159 2 0.00% 91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287 28 0.04% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543 83 0.11% 92.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799 70 0.09% 92.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055 13 0.02% 92.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311 153 0.20% 92.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567 13 0.02% 92.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823 85 0.11% 92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079 13 0.02% 92.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335 90 0.12% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591 32 0.04% 92.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847 150 0.20% 92.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36032-36039 1 0.00% 92.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103 24 0.03% 92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359 9 0.01% 92.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36736-36743 1 0.00% 92.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871 172 0.23% 93.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127 19 0.03% 93.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37184-37191 1 0.00% 93.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37248-37255 2 0.00% 93.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383 23 0.03% 93.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37440-37447 1 0.00% 93.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511 1 0.00% 93.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639 70 0.09% 93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895 89 0.12% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37952-37959 2 0.00% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38016-38023 1 0.00% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151 74 0.10% 93.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38272-38279 1 0.00% 93.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407 12 0.02% 93.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663 31 0.04% 93.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919 140 0.19% 93.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175 81 0.11% 93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39232-39239 1 0.00% 93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431 14 0.02% 93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687 5 0.01% 93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943 169 0.23% 94.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071 1 0.00% 94.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199 23 0.03% 94.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455 67 0.09% 94.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711 29 0.04% 94.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967 152 0.20% 94.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223 26 0.03% 94.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479 66 0.09% 94.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735 22 0.03% 94.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41920-41927 1 0.00% 94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991 165 0.22% 94.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247 4 0.01% 94.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42368-42375 1 0.00% 94.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503 13 0.02% 94.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42560-42567 1 0.00% 94.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759 87 0.12% 95.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015 139 0.19% 95.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271 32 0.04% 95.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527 12 0.02% 95.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43584-43591 1 0.00% 95.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783 72 0.10% 95.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039 92 0.12% 95.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44096-44103 1 0.00% 95.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295 72 0.10% 95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44352-44359 1 0.00% 95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551 22 0.03% 95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44736-44743 1 0.00% 95.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44992-44999 1 0.00% 95.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063 169 0.23% 95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45120-45127 1 0.00% 95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319 83 0.11% 96.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45504-45511 1 0.00% 96.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575 7 0.01% 96.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831 22 0.03% 96.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087 150 0.20% 96.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46208-46215 1 0.00% 96.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46272-46279 1 0.00% 96.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343 27 0.04% 96.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599 96 0.13% 96.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855 12 0.02% 96.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-46983 2 0.00% 96.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47040-47047 1 0.00% 96.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111 92 0.12% 96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47168-47175 1 0.00% 96.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47232-47239 3 0.00% 96.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367 18 0.02% 96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47488-47495 2 0.00% 96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623 154 0.21% 96.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751 1 0.00% 96.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47808-47815 1 0.00% 96.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879 17 0.02% 96.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943 2 0.00% 96.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135 94 0.13% 96.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48192-48199 2 0.00% 96.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48320-48327 3 0.00% 96.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391 97 0.13% 97.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647 12 0.02% 97.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775 14 0.02% 97.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903 17 0.02% 97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967 9 0.01% 97.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031 6 0.01% 97.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095 6 0.01% 97.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159 2103 2.80% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49792-49799 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 75043 # Bytes accessed per row activation
system.physmem.totQLat 159590177750 # Total ticks spent queuing
system.physmem.totMemAccLat 202588661500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 33271940000 # Total ticks spent in databus transfers
system.physmem.totBankLat 9726543750 # Total ticks spent accessing banks
system.physmem.avgQLat 23982.70 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1461.67 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30444.37 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 356.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 6.11 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.99 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 6.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.83 # Data bus utilization in percentage
system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
system.physmem.avgWrQLen 12.10 # Average write queue length when enqueuing
system.physmem.readRowHits 6598517 # Number of row buffer hits during reads
system.physmem.writeRowHits 94894 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 83.19 # Row buffer hit rate for writes
system.physmem.avgGap 159938.04 # Average gap between requests
system.physmem.pageHitRate 98.89 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 4.89 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 59999152 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 7703168 # Transaction distribution
system.membus.trans_dist::ReadResp 7703168 # Transaction distribution
system.membus.trans_dist::WriteReq 767205 # Transaction distribution
system.membus.trans_dist::WriteResp 767205 # Transaction distribution
system.membus.trans_dist::Writeback 64738 # Transaction distribution
system.membus.trans_dist::UpgradeReq 27605 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 16481 # Transaction distribution
system.membus.trans_dist::UpgradeResp 10656 # Transaction distribution
system.membus.trans_dist::ReadExReq 137900 # Transaction distribution
system.membus.trans_dist::ReadExResp 137428 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382570 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8870 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967038 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4359426 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 17335554 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17740 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17430324 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 19839854 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 71744366 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 71744366 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1219669500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 7974500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 9159249500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 5040906450 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
system.membus.respLayer2.occupancy 14657427498 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
system.l2c.tags.replacements 69764 # number of replacements
system.l2c.tags.tagsinuse 53155.979727 # Cycle average of tags in use
system.l2c.tags.total_refs 1654767 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 134953 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 12.261802 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 40044.748185 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667732 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4637.745622 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5787.407955 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001664 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1927.694562 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 755.712463 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.611034 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.070766 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.088309 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.029414 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.011531 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.811096 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 4686 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1510 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 483170 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 242041 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 3562 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1809 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 372569 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 110996 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1220343 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 576824 # number of Writeback hits
system.l2c.Writeback_hits::total 576824 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1289 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 452 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1741 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 268 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 366 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 65622 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 45295 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 110917 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4686 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1510 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 483170 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 307663 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 3562 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1809 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 372569 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 156291 # number of demand (read+write) hits
system.l2c.demand_hits::total 1331260 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4686 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1510 # number of overall hits
system.l2c.overall_hits::cpu0.inst 483170 # number of overall hits
system.l2c.overall_hits::cpu0.data 307663 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 3562 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1809 # number of overall hits
system.l2c.overall_hits::cpu1.inst 372569 # number of overall hits
system.l2c.overall_hits::cpu1.data 156291 # number of overall hits
system.l2c.overall_hits::total 1331260 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6835 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 9720 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 4001 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1892 # number of ReadReq misses
system.l2c.ReadReq_misses::total 22455 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 3383 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 7371 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 866 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 95249 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 44598 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 139847 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6835 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 104969 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 4001 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 46490 # number of demand (read+write) misses
system.l2c.demand_misses::total 162302 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6835 # number of overall misses
system.l2c.overall_misses::cpu0.data 104969 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 4001 # number of overall misses
system.l2c.overall_misses::cpu1.data 46490 # number of overall misses
system.l2c.overall_misses::total 162302 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 302000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 491601250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 735185497 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 283983750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 151633750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1662931247 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 11383008 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 12410968 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 23793976 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1839921 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117953 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 2957874 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 6545912193 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3449006386 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9994918579 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 302000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 491601250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 7281097690 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 283983750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3600640136 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 11657849826 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 302000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 491601250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 7281097690 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 283983750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3600640136 # number of overall miss cycles
system.l2c.overall_miss_latency::total 11657849826 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4690 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1512 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 490005 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 251761 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 3562 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1810 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 376570 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 112888 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1242798 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 576824 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 576824 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 5277 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3835 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 9112 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 655 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1232 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 160871 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 89893 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 250764 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 4690 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 1512 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 490005 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 412632 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 3562 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1810 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 376570 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 202781 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1493562 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 4690 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 1512 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 490005 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 412632 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 3562 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1810 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 376570 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 202781 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1493562 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001323 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013949 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.038608 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000552 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010625 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.016760 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.018068 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.755732 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.882138 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.808933 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.590840 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.830156 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.702922 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.592083 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.496123 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.557684 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001323 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.013949 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.254389 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.000552 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000853 # miss rate for overall accesses
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system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu0.data 75636.368004 # average ReadReq miss latency
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system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70978.192952 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 80144.688161 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 74056.167758 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2854.314945 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3668.627845 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 3228.052639 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4754.317829 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2333.931106 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 3415.558891 # average SCUpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77335.449706 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 71470.382482 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency
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system.l2c.demand_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71828.134133 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu0.data 69364.266498 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu1.inst 70978.192952 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77449.777070 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71828.134133 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 64738 # number of writebacks
system.l2c.writebacks::total 64738 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
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system.l2c.ReadReq_mshr_misses::total 22454 # number of ReadReq MSHR misses
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system.l2c.UpgradeReq_mshr_misses::cpu1.data 3383 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 7371 # number of UpgradeReq MSHR misses
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system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 479 # number of SCUpgradeReq MSHR misses
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system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33964367 # number of UpgradeReq MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::total 167080044240 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486212000 # number of WriteReq MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28921064653 # number of overall MSHR uncacheable cycles
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system.l2c.overall_mshr_uncacheable_latency::total 183838462402 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038608 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016760 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.018067 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.755732 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.882138 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.808933 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.590840 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.830156 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.702922 # mshr miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.496123 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.557684 # mshr miss rate for ReadExReq accesses
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system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::total 0.108667 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000853 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001323 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013947 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.254389 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000552 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010625 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.229262 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.108667 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63169.701337 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67697.542283 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 61549.990959 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.407974 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10039.718297 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10024.942342 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.501292 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.611691 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10016.009238 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56187.238680 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64785.004126 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 58929.114754 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59373.792801 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56833.806114 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58422.456886 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64903.535470 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 59291.707432 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 118413539 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2505894 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2505894 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 767205 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 767205 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 576824 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 26927 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 16847 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 262598 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 262598 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 994053 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951842 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5908 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15091 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 754073 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2881163 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6136 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11790 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7620056 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31386872 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53739672 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6048 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18760 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24100876 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 28000722 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7240 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 14248 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 137274438 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 137274438 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 4319300 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4769236119 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2218068983 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 2472016836 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 10401000 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 1698781961 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 2209782432 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 4326000 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 8228499 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 45405912 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 7671403 # Transaction distribution
system.iobus.trans_dist::ReadResp 7671403 # Transaction distribution
system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8066 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2382570 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 15358698 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16132 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 54294406 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 4039000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374624000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17778330502 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 9652613 # DTB read hits
system.cpu0.dtb.read_misses 3746 # DTB read misses
system.cpu0.dtb.write_hits 7596890 # DTB write hits
system.cpu0.dtb.write_misses 1582 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 9656359 # DTB read accesses
system.cpu0.dtb.write_accesses 7598472 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 17249503 # DTB hits
system.cpu0.dtb.misses 5328 # DTB misses
system.cpu0.dtb.accesses 17254831 # DTB accesses
system.cpu0.itb.inst_hits 43298526 # ITB inst hits
system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 43300731 # ITB inst accesses
system.cpu0.itb.hits 43298526 # DTB hits
system.cpu0.itb.misses 2205 # DTB misses
system.cpu0.itb.accesses 43300731 # DTB accesses
system.cpu0.numCycles 2391512647 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 42571581 # Number of instructions committed
system.cpu0.committedOps 53301862 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 48058821 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
system.cpu0.num_func_calls 1403638 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 5582830 # number of instructions that are conditional controls
system.cpu0.num_int_insts 48058821 # number of integer instructions
system.cpu0.num_fp_insts 3860 # number of float instructions
system.cpu0.num_int_register_reads 272440712 # number of times the integer registers were read
system.cpu0.num_int_register_writes 52270303 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
system.cpu0.num_mem_refs 18019009 # number of memory refs
system.cpu0.num_load_insts 10036459 # Number of load instructions
system.cpu0.num_store_insts 7982550 # Number of store instructions
system.cpu0.num_idle_cycles 2151176097.904201 # Number of idle cycles
system.cpu0.num_busy_cycles 240336549.095799 # Number of busy cycles
system.cpu0.not_idle_fraction 0.100496 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.899504 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 51331 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 490259 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.365280 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 42807737 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 490771 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 87.225482 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 76178400000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.365280 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994854 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.994854 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 42807737 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 42807737 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 42807737 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 42807737 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 42807737 # number of overall hits
system.cpu0.icache.overall_hits::total 42807737 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 490772 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 490772 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 490772 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 490772 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 490772 # number of overall misses
system.cpu0.icache.overall_misses::total 490772 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6820513233 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6820513233 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6820513233 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6820513233 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6820513233 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6820513233 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 43298509 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 43298509 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 43298509 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 43298509 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 43298509 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 43298509 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011335 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011335 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011335 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011335 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011335 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011335 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.519078 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.519078 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13897.519078 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.519078 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13897.519078 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490772 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 490772 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 490772 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 490772 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 490772 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 490772 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5836336767 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5836336767 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5836336767 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5836336767 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5836336767 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5836336767 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 436393250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 436393250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 436393250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 436393250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011335 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.011335 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011335 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.011335 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11892.155149 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11892.155149 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11892.155149 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 407019 # number of replacements
system.cpu0.dcache.tags.tagsinuse 470.951702 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 15966189 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 407531 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 39.177852 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 666436250 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.951702 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919828 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.919828 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 9136364 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 9136364 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 6494337 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 6494337 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156491 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 156491 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158920 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 158920 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 15630701 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 15630701 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 15630701 # number of overall hits
system.cpu0.dcache.overall_hits::total 15630701 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 264039 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 264039 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 176698 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 176698 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9925 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9925 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7429 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7429 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 440737 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 440737 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 440737 # number of overall misses
system.cpu0.dcache.overall_misses::total 440737 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3925412746 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 3925412746 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7893125788 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 7893125788 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98805250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 98805250 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40843887 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 40843887 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 11818538534 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 11818538534 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 11818538534 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 11818538534 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 9400403 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 9400403 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671035 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6671035 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166416 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 166416 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166349 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 166349 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 16071438 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 16071438 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 16071438 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 16071438 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028088 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.028088 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026487 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.026487 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059640 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059640 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044659 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044659 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027424 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.027424 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027424 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.027424 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14866.791444 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14866.791444 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44670.147868 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44670.147868 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9955.188917 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9955.188917 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5497.898371 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5497.898371 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26815.399057 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26815.399057 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 26815.399057 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 376552 # number of writebacks
system.cpu0.dcache.writebacks::total 376552 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 264039 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 264039 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176698 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 176698 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7424 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7424 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 440737 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 440737 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 440737 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 440737 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3395057254 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3395057254 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7495344212 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7495344212 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78904750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78904750 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25999113 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25999113 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10890401466 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10890401466 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10890401466 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10890401466 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765517500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765517500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807250835 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807250835 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572768335 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572768335 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028088 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026487 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026487 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059640 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059640 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044629 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044629 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.027424 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027424 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027424 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.165854 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.165854 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42418.953310 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42418.953310 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7950.100756 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7950.100756 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3502.035695 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3502.035695 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24709.523970 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24709.523970 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 5708064 # DTB read hits
system.cpu1.dtb.read_misses 3582 # DTB read misses
system.cpu1.dtb.write_hits 3874465 # DTB write hits
system.cpu1.dtb.write_misses 647 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 5711646 # DTB read accesses
system.cpu1.dtb.write_accesses 3875112 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 9582529 # DTB hits
system.cpu1.dtb.misses 4229 # DTB misses
system.cpu1.dtb.accesses 9586758 # DTB accesses
system.cpu1.itb.inst_hits 19382020 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 19384191 # ITB inst accesses
system.cpu1.itb.hits 19382020 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
system.cpu1.itb.accesses 19384191 # DTB accesses
system.cpu1.numCycles 2390063941 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 18801432 # Number of instructions committed
system.cpu1.committedOps 24909061 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 22272671 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
system.cpu1.num_func_calls 796781 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2514806 # number of instructions that are conditional controls
system.cpu1.num_int_insts 22272671 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
system.cpu1.num_int_register_reads 130802029 # number of times the integer registers were read
system.cpu1.num_int_register_writes 23323968 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
system.cpu1.num_mem_refs 10017952 # number of memory refs
system.cpu1.num_load_insts 5984754 # Number of load instructions
system.cpu1.num_store_insts 4033198 # Number of store instructions
system.cpu1.num_idle_cycles 1969143633.381917 # Number of idle cycles
system.cpu1.num_busy_cycles 420920307.618083 # Number of busy cycles
system.cpu1.not_idle_fraction 0.176113 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.823887 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 39084 # number of quiesce instructions executed
system.cpu1.icache.tags.replacements 376793 # number of replacements
system.cpu1.icache.tags.tagsinuse 474.907040 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 19004711 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 377305 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 50.369624 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 327169943500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.907040 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927553 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.927553 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 19004711 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 19004711 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 19004711 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 19004711 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 19004711 # number of overall hits
system.cpu1.icache.overall_hits::total 19004711 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 377305 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 377305 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 377305 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 377305 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 377305 # number of overall misses
system.cpu1.icache.overall_misses::total 377305 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5159789711 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5159789711 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5159789711 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5159789711 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5159789711 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5159789711 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 19382016 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 19382016 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 19382016 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 19382016 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 19382016 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 19382016 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019467 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.019467 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019467 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.019467 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019467 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.019467 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.381219 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13675.381219 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13675.381219 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13675.381219 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13675.381219 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377305 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 377305 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 377305 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 377305 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 377305 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 377305 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4403600289 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4403600289 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4403600289 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4403600289 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4403600289 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4403600289 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6432750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6432750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6432750 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6432750 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019467 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.019467 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019467 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.019467 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11671.195158 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11671.195158 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11671.195158 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 220883 # number of replacements
system.cpu1.dcache.tags.tagsinuse 471.477381 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 8233318 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 221230 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 37.216101 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 106377423000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.477381 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920854 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.920854 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 4390672 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 4390672 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 3674527 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 3674527 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73485 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 73485 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73732 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 73732 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 8065199 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 8065199 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 8065199 # number of overall hits
system.cpu1.dcache.overall_hits::total 8065199 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 134090 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 134090 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 112827 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 112827 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9762 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 9762 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9429 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 9429 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 246917 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 246917 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 246917 # number of overall misses
system.cpu1.dcache.overall_misses::total 246917 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1656976729 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 1656976729 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4353399476 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 4353399476 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77544499 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 77544499 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49349978 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 49349978 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 6010376205 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 6010376205 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 6010376205 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 6010376205 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524762 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 4524762 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787354 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 3787354 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83247 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 83247 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83161 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 83161 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 8312116 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 8312116 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 8312116 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 8312116 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029635 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.029635 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029790 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.029790 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117265 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117265 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113382 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113382 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029706 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.029706 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029706 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.029706 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12357.198367 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12357.198367 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38584.731279 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 38584.731279 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7943.505327 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7943.505327 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5233.850673 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5233.850673 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 24341.686498 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24341.686498 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24341.686498 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 200272 # number of writebacks
system.cpu1.dcache.writebacks::total 200272 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134090 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 134090 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112827 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 112827 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9762 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9762 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9426 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 9426 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 246917 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 246917 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 246917 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 246917 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1388441271 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1388441271 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4117774524 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4117774524 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58015501 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58015501 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30499022 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30499022 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5506215795 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 5506215795 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5506215795 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 5506215795 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168382941250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168382941250 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531038000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531038000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168913979250 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168913979250 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029635 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029635 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029790 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029790 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117265 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117265 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113346 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113346 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.029706 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029706 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.029706 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10354.547476 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10354.547476 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36496.357468 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36496.357468 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5942.993342 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5942.993342 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3235.627201 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3235.627201 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22299.865117 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22299.865117 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651875253502 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 651875253502 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651875253502 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 651875253502 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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