path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.195945                       # Number of seconds simulated
sim_ticks                                1195945260000                       # Number of ticks simulated
final_tick                               1195945260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 424891                       # Simulator instruction rate (inst/s)
host_op_rate                                   541366                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8267957779                       # Simulator tick rate (ticks/s)
host_mem_usage                                 468940                       # Number of bytes of host memory used
host_seconds                                   144.65                       # Real time elapsed on the host
sim_insts                                    61459750                       # Number of instructions simulated
sim_ops                                      78307634                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           393612                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4714684                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           324676                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4804472                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62142468                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       393612                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       324676                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          718288                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4110592                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7137936                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             12378                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             73741                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5164                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             75098                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6654453                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           64228                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               821064                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43400408                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              329122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3942224                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              271481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4017301                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51960963                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         329122                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         271481                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             600603                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3437107                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              14215                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2517125                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5968447                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3437107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43400408                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             329122                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3956439                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             271481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            6534426                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               57929411                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6654453                       # Number of read requests accepted
system.physmem.writeReqs                       821064                       # Number of write requests accepted
system.physmem.readBursts                     6654453                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     821064                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                425841472                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     43520                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7149184                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  62142468                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7137936                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      680                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709327                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          12098                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              415328                       # Per bank write bursts
system.physmem.perBankRdBursts::1              415212                       # Per bank write bursts
system.physmem.perBankRdBursts::2              415403                       # Per bank write bursts
system.physmem.perBankRdBursts::3              415611                       # Per bank write bursts
system.physmem.perBankRdBursts::4              422397                       # Per bank write bursts
system.physmem.perBankRdBursts::5              415577                       # Per bank write bursts
system.physmem.perBankRdBursts::6              415747                       # Per bank write bursts
system.physmem.perBankRdBursts::7              415496                       # Per bank write bursts
system.physmem.perBankRdBursts::8              416027                       # Per bank write bursts
system.physmem.perBankRdBursts::9              415632                       # Per bank write bursts
system.physmem.perBankRdBursts::10             415426                       # Per bank write bursts
system.physmem.perBankRdBursts::11             414842                       # Per bank write bursts
system.physmem.perBankRdBursts::12             414820                       # Per bank write bursts
system.physmem.perBankRdBursts::13             415557                       # Per bank write bursts
system.physmem.perBankRdBursts::14             415554                       # Per bank write bursts
system.physmem.perBankRdBursts::15             415144                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6840                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6732                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6969                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7025                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7326                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7107                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7317                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7078                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7464                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7155                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7023                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6543                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6616                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6901                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6977                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6633                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1195940759000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    6849                       # Read request sizes (log2)
system.physmem.readPktSize::3                 6488064                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  159540                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  64228                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    572493                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    410656                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    412880                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    461685                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    417933                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    446395                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1149366                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   1113988                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   1438120                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     64577                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    50343                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    45843                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    44044                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     8771                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     8319                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     8183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3947                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6500                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6488                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       473596                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      914.261641                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     784.047795                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     289.306705                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          25239      5.33%      5.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        21585      4.56%      9.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5945      1.26%     11.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2453      0.52%     11.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2290      0.48%     12.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1636      0.35%     12.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4075      0.86%     13.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          899      0.19%     13.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       409474     86.46%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         473596                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6482                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      1026.497532                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    34346.134147                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-131071         6476     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::131072-262143            3      0.05%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-655359            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-917503            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6482                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6482                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.233261                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.205432                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.970583                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2453     37.84%     37.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 80      1.23%     39.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               3936     60.72%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 11      0.17%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6482                       # Writes before turning the bus around for reads
system.physmem.totQLat                   171035006500                       # Total ticks spent queuing
system.physmem.totMemAccLat              295793250250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  33268865000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25704.97                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44454.97                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         356.07                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           5.98                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       51.96                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        5.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.83                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.78                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         4.89                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        27.45                       # Average write queue length when enqueuing
system.physmem.readRowHits                    6199461                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     92422                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  82.71                       # Row buffer hit rate for writes
system.physmem.avgGap                       159981.01                       # Average gap between requests
system.physmem.pageHitRate                      93.00                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     947634468500                       # Time in different power states
system.physmem.memoryStateTime::REF       39935220000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      208375212750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     59946686                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             7703403                       # Transaction distribution
system.membus.trans_dist::ReadResp            7703403                       # Transaction distribution
system.membus.trans_dist::WriteReq             767582                       # Transaction distribution
system.membus.trans_dist::WriteResp            767582                       # Transaction distribution
system.membus.trans_dist::Writeback             64228                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            31700                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          17261                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12098                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137709                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137266                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382666                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10310                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          910                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1972180                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4366104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               17342232                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390035                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20620                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1820                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17375892                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     19788443                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            71692955                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               71692955                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1224801000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             9242500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy              784500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy          9211274000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         5078680829                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.respLayer2.occupancy        16046108250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    69421                       # number of replacements
system.l2c.tags.tagsinuse                53012.823108                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1672128                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   134609                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    12.422111                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   40185.217534                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000410                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001544                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3710.755623                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4242.358437                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.742287                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001689                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2808.724549                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2063.021033                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.613178                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.056622                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.064733                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000042                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.042858                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.031479                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.808911                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65183                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1920                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8039                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55163                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994614                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 17207703                       # Number of tag accesses
system.l2c.tags.data_accesses                17207703                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         3810                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         1739                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             419090                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             205762                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5504                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1909                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             464812                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             143326                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1245952                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          570869                       # number of Writeback hits
system.l2c.Writeback_hits::total               570869                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1175                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             561                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1736                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           218                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           106                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               324                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            56320                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            52713                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109033                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          3810                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          1739                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              419090                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              262082                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5504                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1909                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              464812                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              196039                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1354985                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         3810                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         1739                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             419090                       # number of overall hits
system.l2c.overall_hits::cpu0.data             262082                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5504                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1909                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             464812                       # number of overall hits
system.l2c.overall_hits::cpu1.data             196039                       # number of overall hits
system.l2c.overall_hits::total                1354985                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             5736                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             7851                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             5067                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             3613                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22275                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          4950                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3658                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8608                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          565                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          478                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1043                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          67127                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72586                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139713                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5736                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             74978                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5067                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             76199                       # number of demand (read+write) misses
system.l2c.demand_misses::total                161988                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5736                       # number of overall misses
system.l2c.overall_misses::cpu0.data            74978                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5067                       # number of overall misses
system.l2c.overall_misses::cpu1.data            76199                       # number of overall misses
system.l2c.overall_misses::total               161988                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        32000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    404696000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    578862249                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       334500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    361943250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    276382250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1622474249                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     13480917                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12005984                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     25486901                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1698427                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2508392                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      4206819                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4495992931                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5253472119                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9749465050                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker        32000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    404696000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   5074855180                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       334500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    361943250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   5529854369                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11371939299                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker        32000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    404696000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   5074855180                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       334500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    361943250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   5529854369                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11371939299                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         3811                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         1741                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         424826                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         213613                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5508                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1910                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         469879                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         146939                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1268227                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       570869                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           570869                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6125                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4219                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10344                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          783                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          584                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1367                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       123447                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       125299                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           248746                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         3811                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         1741                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          424826                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          337060                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5508                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1910                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          469879                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          272238                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1516973                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         3811                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         1741                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         424826                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         337060                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5508                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1910                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         469879                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         272238                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1516973                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013502                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036753                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000524                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010784                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.024588                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017564                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.808163                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.867030                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.832173                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.721584                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.818493                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.762985                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.543772                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.579302                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.561669                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013502                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.222447                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000524                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010784                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.279898                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.106784                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.001149                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013502                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.222447                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000524                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010784                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.279898                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.106784                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        32000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70553.695955                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73731.021399                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        83625                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71431.468324                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76496.609466                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 72838.350123                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2723.417576                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3282.117004                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2960.838871                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3006.065487                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5247.682008                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4033.383509                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66977.414915                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72375.831689                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69782.089355                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 70553.695955                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 67684.589880                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71431.468324                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 72571.219688                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70202.356341                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 70553.695955                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 67684.589880                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71431.468324                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 72571.219688                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70202.356341                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               64228                       # number of writebacks
system.l2c.writebacks::total                    64228                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         5735                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         7851                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         5067                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         3613                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22274                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         4950                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3658                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8608                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          565                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          478                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1043                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        67127                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72586                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139713                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         5735                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        74978                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5067                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        76199                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           161987                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         5735                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        74978                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5067                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        76199                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          161987                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    331983250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    480926749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    297779250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    231458250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1342639499                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     49534942                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     36634151                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     86169093                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5652063                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4782976                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10435039                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3631997561                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4330425379                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7962422940                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    331983250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4112924310                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    297779250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4561883629                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9305062439                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    331983250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4112924310                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    297779250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4561883629                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9305062439                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    350574750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12456402492                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5624750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154292832747                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167105434739                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1046881494                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15722205337                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16769086831                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    350574750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13503283986                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5624750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015038084                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183874521570                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001149                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013500                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036753                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000524                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010784                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024588                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017563                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.808163                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.867030                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.832173                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.721584                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.818493                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.762985                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.543772                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.579302                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.561669                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001149                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013500                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.222447                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000524                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010784                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.279898                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.106783                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001149                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013500                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.222447                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000524                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010784                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.279898                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.106783                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61256.750605                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64062.621091                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60278.328949                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.058990                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.803445                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10010.350023                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.651327                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.225941                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10004.831256                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54106.359006                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59659.237029                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56991.281699                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54855.081624                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59868.024895                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57443.266676                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57887.227550                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54855.081624                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58768.354056                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59868.024895                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57443.266676                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                   119513329                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2535217                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2535217                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            767582                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           767582                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           570869                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           30989                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         17585                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          48574                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           260651                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          260651                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       863496                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1226215                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6137                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12691                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       940498                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4601530                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6236                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15421                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7672224                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27215456                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41348685                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6964                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15244                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30072692                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39622266                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7640                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        22032                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          138310979                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             138310979                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4620420                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4758868690                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1923485226                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1752589322                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           4396000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy           8880000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        2117887474                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        2927028338                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           4326000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy           9913999                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      45398856                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq              7671434                       # Transaction distribution
system.iobus.trans_dist::ReadResp             7671434                       # Transaction distribution
system.iobus.trans_dist::WriteReq                7963                       # Transaction distribution
system.iobus.trans_dist::WriteResp               7963                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8060                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          742                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382666                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                15358794                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40319                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1484                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390035                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             54294547                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                54294547                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21418000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4036000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               377000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               298000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374703000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         16368811750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7064335                       # DTB read hits
system.cpu0.dtb.read_misses                      3758                       # DTB read misses
system.cpu0.dtb.write_hits                    5649339                       # DTB write hits
system.cpu0.dtb.write_misses                      802                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1711                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   143                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 7068093                       # DTB read accesses
system.cpu0.dtb.write_accesses                5650141                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         12713674                       # DTB hits
system.cpu0.dtb.misses                           4560                       # DTB misses
system.cpu0.dtb.accesses                     12718234                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    29562995                       # ITB inst hits
system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1181                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                29565200                       # ITB inst accesses
system.cpu0.itb.hits                         29562995                       # DTB hits
system.cpu0.itb.misses                           2205                       # DTB misses
system.cpu0.itb.accesses                     29565200                       # DTB accesses
system.cpu0.numCycles                      2391890520                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   28864889                       # Number of instructions committed
system.cpu0.committedOps                     37190899                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             33115613                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
system.cpu0.num_func_calls                    1241798                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4372441                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    33115613                       # number of integer instructions
system.cpu0.num_fp_insts                         3860                       # number of float instructions
system.cpu0.num_int_register_reads          192173380                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          36248506                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     13380838                       # number of memory refs
system.cpu0.num_load_insts                    7401595                       # Number of load instructions
system.cpu0.num_store_insts                   5979243                       # Number of store instructions
system.cpu0.num_idle_cycles              2246179687.500122                       # Number of idle cycles
system.cpu0.num_busy_cycles              145710832.499878                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.060919                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.939081                       # Percentage of idle cycles
system.cpu0.Branches                          5600259                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                14567      0.04%      0.04% # Class of executed instruction
system.cpu0.op_class::IntAlu                 24478507     64.56%     64.59% # Class of executed instruction
system.cpu0.op_class::IntMult                   43773      0.12%     64.71% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc               694      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     64.71% # Class of executed instruction
system.cpu0.op_class::MemRead                 7401595     19.52%     84.23% # Class of executed instruction
system.cpu0.op_class::MemWrite                5979243     15.77%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  37918379                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   46956                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           424861                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.353809                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           29137604                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           425373                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            68.498950                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      76246574000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.353809                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994832                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.994832                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         29988352                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        29988352                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     29137604                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       29137604                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     29137604                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        29137604                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     29137604                       # number of overall hits
system.cpu0.icache.overall_hits::total       29137604                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       425374                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       425374                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       425374                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        425374                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       425374                       # number of overall misses
system.cpu0.icache.overall_misses::total       425374                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5893447476                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5893447476                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5893447476                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5893447476                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5893447476                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5893447476                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     29562978                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     29562978                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     29562978                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     29562978                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     29562978                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     29562978                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014389                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014389                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014389                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014389                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014389                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014389                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13854.743064                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13854.743064                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13854.743064                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13854.743064                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13854.743064                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13854.743064                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425374                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       425374                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       425374                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       425374                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       425374                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       425374                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5040497524                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5040497524                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5040497524                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5040497524                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5040497524                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5040497524                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442131250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    442131250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442131250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    442131250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014389                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014389                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014389                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014389                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11849.566556                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11849.566556                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11849.566556                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11849.566556                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           329701                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          455.940244                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           12258862                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           330213                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            37.124105                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        671876250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   455.940244                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.890508                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.890508                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           98                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         50852546                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        50852546                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      6594319                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6594319                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5344510                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5344510                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       148000                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       148000                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149609                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       149609                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11938829                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11938829                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11938829                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11938829                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       227548                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       227548                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       141421                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       141421                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9358                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9358                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7517                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7517                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       368969                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        368969                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       368969                       # number of overall misses
system.cpu0.dcache.overall_misses::total       368969                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3297192496                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   3297192496                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5650617511                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   5650617511                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92814250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     92814250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44512065                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     44512065                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8947810007                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   8947810007                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8947810007                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   8947810007                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      6821867                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      6821867                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5485931                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5485931                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157358                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       157358                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157126                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       157126                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     12307798                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     12307798                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     12307798                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     12307798                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033356                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.033356                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025779                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.025779                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059469                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059469                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047841                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047841                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029978                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.029978                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029978                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.029978                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9918.171618                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9918.171618                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5921.519888                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5921.519888                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       305583                       # number of writebacks
system.cpu0.dcache.writebacks::total           305583                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227548                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       227548                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141421                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       141421                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9358                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9358                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7515                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7515                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       368969                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       368969                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       368969                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       368969                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2840145504                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2840145504                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5338354489                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5338354489                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     74046750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     74046750                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29480935                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29480935                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8178499993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   8178499993                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8178499993                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   8178499993                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13564071000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13564071000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1170919500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1170919500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14734990500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14734990500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033356                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033356                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025779                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025779                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059469                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059469                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047828                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047828                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029978                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.029978                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029978                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.029978                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7912.668305                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7912.668305                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3922.945442                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3922.945442                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     8317790                       # DTB read hits
system.cpu1.dtb.read_misses                      3645                       # DTB read misses
system.cpu1.dtb.write_hits                    5833574                       # DTB write hits
system.cpu1.dtb.write_misses                     1433                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1863                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   144                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 8321435                       # DTB read accesses
system.cpu1.dtb.write_accesses                5835007                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         14151364                       # DTB hits
system.cpu1.dtb.misses                           5078                       # DTB misses
system.cpu1.dtb.accesses                     14156442                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    33205963                       # ITB inst hits
system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1276                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                33208134                       # ITB inst accesses
system.cpu1.itb.hits                         33205963                       # DTB hits
system.cpu1.itb.misses                           2171                       # DTB misses
system.cpu1.itb.accesses                     33208134                       # DTB accesses
system.cpu1.numCycles                      2390414629                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   32594861                       # Number of instructions committed
system.cpu1.committedOps                     41116735                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             37639270                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
system.cpu1.num_func_calls                     962738                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3734786                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    37639270                       # number of integer instructions
system.cpu1.num_fp_insts                         6793                       # number of float instructions
system.cpu1.num_int_register_reads          218315433                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          39777331                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
system.cpu1.num_mem_refs                     14690124                       # number of memory refs
system.cpu1.num_load_insts                    8639728                       # Number of load instructions
system.cpu1.num_store_insts                   6050396                       # Number of store instructions
system.cpu1.num_idle_cycles              1874297798.309079                       # Number of idle cycles
system.cpu1.num_busy_cycles              516116830.690921                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.215911                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.784089                       # Percentage of idle cycles
system.cpu1.Branches                          4947313                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                14267      0.03%      0.03% # Class of executed instruction
system.cpu1.op_class::IntAlu                 26968126     64.63%     64.67% # Class of executed instruction
system.cpu1.op_class::IntMult                   50231      0.12%     64.79% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              1470      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.79% # Class of executed instruction
system.cpu1.op_class::MemRead                 8639728     20.71%     85.50% # Class of executed instruction
system.cpu1.op_class::MemWrite                6050396     14.50%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  41724218                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   44363                       # number of quiesce instructions executed
system.cpu1.icache.tags.replacements           469889                       # number of replacements
system.cpu1.icache.tags.tagsinuse          478.549875                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           32735558                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           470401                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            69.590749                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      93998064500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.549875                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934668                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.934668                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          448                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         33676360                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        33676360                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     32735558                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       32735558                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     32735558                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        32735558                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     32735558                       # number of overall hits
system.cpu1.icache.overall_hits::total       32735558                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       470401                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       470401                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       470401                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        470401                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       470401                       # number of overall misses
system.cpu1.icache.overall_misses::total       470401                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6443025224                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   6443025224                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   6443025224                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   6443025224                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   6443025224                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   6443025224                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     33205959                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     33205959                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     33205959                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     33205959                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     33205959                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     33205959                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014166                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014166                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014166                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014166                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014166                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014166                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13696.878246                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13696.878246                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13696.878246                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13696.878246                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13696.878246                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13696.878246                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       470401                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       470401                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       470401                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       470401                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       470401                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       470401                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5500320776                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5500320776                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5500320776                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5500320776                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5500320776                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5500320776                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7094750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      7094750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      7094750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      7094750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014166                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.014166                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014166                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.014166                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11692.833935                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11692.833935                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11692.833935                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11692.833935                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           292396                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          471.340913                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           11973732                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           292744                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            40.901716                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      85301409250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.340913                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920588                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.920588                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          333                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           15                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         49486795                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        49486795                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      6952689                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        6952689                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4832965                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4832965                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        82012                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        82012                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82761                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        82761                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     11785654                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        11785654                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     11785654                       # number of overall hits
system.cpu1.dcache.overall_hits::total       11785654                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       170655                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       170655                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       150219                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       150219                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11301                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        11301                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10073                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10073                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       320874                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        320874                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       320874                       # number of overall misses
system.cpu1.dcache.overall_misses::total       320874                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2212742497                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2212742497                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6365695527                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   6365695527                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     97206750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     97206750                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52182477                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     52182477                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8578438024                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8578438024                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8578438024                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8578438024                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      7123344                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      7123344                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4983184                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4983184                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93313                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        93313                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92834                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        92834                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     12106528                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     12106528                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     12106528                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     12106528                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023957                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.023957                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030145                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030145                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.121109                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.121109                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108506                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108506                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026504                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.026504                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026504                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.026504                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12966.174428                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12966.174428                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42376.101072                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 42376.101072                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8601.606053                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8601.606053                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5180.430557                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5180.430557                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26734.599949                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 26734.599949                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       265286                       # number of writebacks
system.cpu1.dcache.writebacks::total           265286                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170655                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       170655                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150219                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       150219                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11301                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11301                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10070                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10070                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       320874                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       320874                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       320874                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       320874                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1870737503                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1870737503                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6042583473                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6042583473                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74594250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     74594250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32041523                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32041523                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7913320976                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7913320976                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7913320976                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7913320976                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25187494163                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25187494163                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023957                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023957                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030145                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030145                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.121109                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.121109                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108473                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108473                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026504                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026504                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026504                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.026504                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6600.676931                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6600.676931                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3181.879146                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3181.879146                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 745373562750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------