path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.870989                       # Number of seconds simulated
sim_ticks                                2870988926500                       # Number of ticks simulated
final_tick                               2870988926500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 334502                       # Simulator instruction rate (inst/s)
host_op_rate                                   404603                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7301303629                       # Simulator tick rate (ticks/s)
host_mem_usage                                 607968                       # Number of bytes of host memory used
host_seconds                                   393.22                       # Real time elapsed on the host
sim_insts                                   131531628                       # Number of instructions simulated
sim_ops                                     159096162                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1180196                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1293924                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8559616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           153620                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           569684                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       405184                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12163760                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1180196                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       153620                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1333816                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8766400                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8783964                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26894                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20737                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133744                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2555                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8922                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6331                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199207                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          136975                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               141366                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              411076                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              450689                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2981417                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               53508                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              198428                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       141130                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4236784                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         411076                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          53508                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             464584                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3053443                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6104                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3059560                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3053443                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             411076                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             456793                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2981417                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              53508                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             198442                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       141130                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7296344                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199207                       # Number of read requests accepted
system.physmem.writeReqs                       141366                       # Number of write requests accepted
system.physmem.readBursts                      199207                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     141366                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12740608                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8796800                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12163760                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8783964                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11688                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11970                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12095                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12159                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20723                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12090                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12329                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12246                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12200                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12543                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11897                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11487                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11682                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11835                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11042                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11086                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8412                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8881                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9049                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8857                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8522                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8714                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9020                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8690                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8720                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9031                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8698                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8602                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8645                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8180                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7869                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7560                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          78                       # Number of times write queue was full causing retry
system.physmem.totGap                    2870987895000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  189447                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 136975                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    135724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     17225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10602                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8875                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7477                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5952                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5078                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4199                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3667                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       77                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       48                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2512                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6487                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7013                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7539                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9670                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10012                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      232                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        85540                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      251.780968                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.250026                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.334701                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          42821     50.06%     50.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18143     21.21%     71.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6218      7.27%     78.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3674      4.30%     82.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2664      3.11%     85.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1727      2.02%     87.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          953      1.11%     89.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          967      1.13%     90.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8373      9.79%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          85540                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6799                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.279453                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      564.517669                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6797     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6799                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6799                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.216208                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.546976                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.866150                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5813     85.50%     85.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             291      4.28%     89.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              61      0.90%     90.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              49      0.72%     91.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             268      3.94%     95.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              20      0.29%     95.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              11      0.16%     95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              22      0.32%     96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              12      0.18%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               7      0.10%     96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.09%     96.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              11      0.16%     96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             154      2.27%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.09%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.04%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.10%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.06%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.04%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.06%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             5      0.07%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             4      0.06%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             9      0.13%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             4      0.06%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.04%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             4      0.06%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6799                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9415943788                       # Total ticks spent queuing
system.physmem.totMemAccLat               13148543788                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    995360000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       47299.19                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  66049.19                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.06                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.06                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.01                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166164                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     84817                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.47                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  61.70                       # Row buffer hit rate for writes
system.physmem.avgGap                      8429875.22                       # Average gap between requests
system.physmem.pageHitRate                      74.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  312774840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  166239975                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 751842000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                366156900                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6214010400.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5556704280                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              357731520                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       11629133730                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        9364882080                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       675113260110                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             709836228825                       # Total energy per rank (pJ)
system.physmem_0.averagePower              247.244502                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2857863952057                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      659296177                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2641884000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2807973624000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  24387714557                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      9823730266                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  25502677500                       # Time in different power states
system.physmem_1.actEnergy                  297987900                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  158384325                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 669532080                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                351332100                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6199259040.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5628324780                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              351060000                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       11278473150                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        9521383680                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       675168861345                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             709627419000                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.171771                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2857510482171                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      643430972                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2635632000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2808196835750                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  24795240087                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      9984355357                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  24733432334                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                     7799                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7799                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1450                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6349                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         7799                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7799    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7799                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6405                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12453.161593                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11389.819011                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6523.003169                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         5861     91.51%     91.51% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          469      7.32%     98.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           66      1.03%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            4      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-114687            3      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6405                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1181300000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1181300000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1181300000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         4994     77.97%     77.97% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1411     22.03%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6405                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7799                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7799                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6405                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6405                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        14204                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25116933                       # DTB read hits
system.cpu0.dtb.read_misses                      6669                       # DTB read misses
system.cpu0.dtb.write_hits                   18718433                       # DTB write hits
system.cpu0.dtb.write_misses                     1130                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3389                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1753                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25123602                       # DTB read accesses
system.cpu0.dtb.write_accesses               18719563                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43835366                       # DTB hits
system.cpu0.dtb.misses                           7799                       # DTB misses
system.cpu0.dtb.accesses                     43843165                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     3348                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3348                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          299                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3049                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12654.159520                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11787.335553                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5848.484815                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          389     16.68%     16.68% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1671     71.66%     88.34% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          217      9.31%     97.64% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           27      1.16%     98.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           21      0.90%     99.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            3      0.13%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::122880-131071            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1180899500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1180899500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1180899500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2033     87.18%     87.18% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          299     12.82%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2332                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5680                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   118797664                       # ITB inst hits
system.cpu0.itb.inst_misses                      3348                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2086                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               118801012                       # ITB inst accesses
system.cpu0.itb.hits                        118797664                       # DTB hits
system.cpu0.itb.misses                           3348                       # DTB misses
system.cpu0.itb.accesses                    118801012                       # DTB accesses
system.cpu0.numPwrStateTransitions               3664                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1832                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1490824715.864083                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23921725256.931263                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1059     57.81%     57.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          768     41.92%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.78% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.22%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499964287288                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1832                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   139798047037                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731190879463                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                      5741977853                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1832                       # number of quiesce instructions executed
system.cpu0.committedInsts                  115134358                       # Number of instructions committed
system.cpu0.committedOps                    139131175                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            123155389                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
system.cpu0.num_func_calls                   12669084                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     15658471                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   123155389                       # number of integer instructions
system.cpu0.num_fp_insts                         9755                       # number of float instructions
system.cpu0.num_int_register_reads          226724524                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          85578914                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           504070716                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           52161373                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     44970744                       # number of memory refs
system.cpu0.num_load_insts                   25368600                       # Number of load instructions
system.cpu0.num_store_insts                  19602144                       # Number of store instructions
system.cpu0.num_idle_cycles              5462381758.924097                       # Number of idle cycles
system.cpu0.num_busy_cycles              279596094.075903                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.048693                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.951307                       # Percentage of idle cycles
system.cpu0.Branches                         29063879                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 97803517     68.44%     68.45% # Class of executed instruction
system.cpu0.op_class::IntMult                  109759      0.08%     68.52% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatMisc                     0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8141      0.01%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::MemRead                25366344     17.75%     86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               19594649     13.71%     99.99% # Class of executed instruction
system.cpu0.op_class::FloatMemRead               2256      0.00%     99.99% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite              7495      0.01%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 142894434                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           691910                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          491.841324                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           42965158                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           692422                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            62.050539                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1207348000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   491.841324                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.960628                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.960628                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          111                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88306903                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88306903                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     23857214                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23857214                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17987587                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17987587                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       319351                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       319351                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       364951                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       364951                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361858                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361858                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     41844801                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41844801                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     42164152                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42164152                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       395864                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       395864                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       325028                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325028                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       126936                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       126936                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21386                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21386                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19587                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19587                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       720892                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        720892                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       847828                       # number of overall misses
system.cpu0.dcache.overall_misses::total       847828                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5519668500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5519668500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6305983500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6305983500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    336140000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    336140000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    459598500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    459598500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1175500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1175500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  11825652000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  11825652000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  11825652000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  11825652000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24253078                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24253078                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18312615                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18312615                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446287                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       446287                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386337                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386337                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381445                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381445                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     42565693                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42565693                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     43011980                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43011980                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016322                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016322                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017749                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017749                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.284427                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.284427                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055356                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055356                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051349                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051349                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016936                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016936                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019711                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.019711                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13943.345442                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13943.345442                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19401.354653                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19401.354653                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15717.759282                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15717.759282                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23464.466228                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23464.466228                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16404.193693                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16404.193693                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13948.173450                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13948.173450                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       691910                       # number of writebacks
system.cpu0.dcache.writebacks::total           691910                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25218                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25218                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15019                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15019                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25219                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25219                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25219                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25219                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       370646                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       370646                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325027                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       325027                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        99914                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        99914                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6367                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6367                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19587                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19587                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       695673                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       695673                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       795587                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       795587                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31782                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31782                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28454                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28454                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60236                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60236                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4741194000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4741194000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5980473000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5980473000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1654728000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1654728000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     97962000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     97962000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    440045500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    440045500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1141500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1141500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10721667000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10721667000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12376395000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  12376395000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6631909500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6631909500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6631909500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6631909500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015282                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015282                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017749                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017749                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.223878                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223878                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016480                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016480                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051349                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051349                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016344                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016344                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018497                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018497                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12791.704214                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12791.704214                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18399.926775                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18399.926775                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16561.522910                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16561.522910                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15385.896026                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15385.896026                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22466.202073                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22466.202073                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15411.934918                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15411.934918                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15556.306224                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15556.306224                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208668.727582                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208668.727582                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110098.769839                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110098.769839                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1101405                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.436911                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          117695738                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1101917                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           106.809985                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14178985000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.436911                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998900                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998900                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        238697254                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       238697254                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    117695738                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      117695738                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    117695738                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       117695738                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    117695738                       # number of overall hits
system.cpu0.icache.overall_hits::total      117695738                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1101926                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1101926                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1101926                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1101926                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1101926                       # number of overall misses
system.cpu0.icache.overall_misses::total      1101926                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11884591500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11884591500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11884591500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11884591500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11884591500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11884591500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    118797664                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    118797664                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    118797664                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    118797664                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    118797664                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    118797664                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009276                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009276                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009276                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009276                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009276                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009276                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10785.290029                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10785.290029                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10785.290029                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10785.290029                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10785.290029                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10785.290029                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1101405                       # number of writebacks
system.cpu0.icache.writebacks::total          1101405                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1101926                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1101926                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1101926                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1101926                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1101926                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1101926                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11333628500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11333628500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11333628500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11333628500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11333628500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11333628500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    863305500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    863305500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009276                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009276                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009276                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009276                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009276                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009276                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10285.290029                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10285.290029                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10285.290029                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10285.290029                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10285.290029                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10285.290029                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1842335                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1842343                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       236049                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          259510                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15639.759609                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1683263                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          275158                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.117442                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14465.018905                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.607944                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.119153                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1173.013607                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.882875                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000098                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.071595                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.954575                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          297                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15346                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           36                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          136                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          119                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          812                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6067                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6453                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1818                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.018127                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.936646                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        61207036                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       61207036                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         9838                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4464                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         14302                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       475527                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       475527                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1289984                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1289984                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       227136                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       227136                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1039867                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1039867                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376033                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       376033                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         9838                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4464                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1039867                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       603169                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1657338                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         9838                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4464                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1039867                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       603169                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1657338                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          303                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          138                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          441                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        54610                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        54610                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19582                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19582                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43281                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43281                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        62059                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        62059                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       100894                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       100894                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          303                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          138                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        62059                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144175                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       206675                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          303                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          138                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        62059                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144175                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       206675                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      8179000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3277000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     11456000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     32137500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total     32137500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      8911500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      8911500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1089999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1089999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2751603000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2751603000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3417541500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3417541500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3327393000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3327393000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      8179000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3277000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3417541500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6078996000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   9507993500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      8179000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3277000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3417541500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6078996000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   9507993500                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        10141                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4602                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        14743                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       475527                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       475527                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1289984                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1289984                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54610                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        54610                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19582                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19582                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       270417                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       270417                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1101926                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1101926                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       476927                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       476927                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        10141                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4602                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1101926                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       747344                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1864013                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        10141                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4602                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1101926                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       747344                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1864013                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.029879                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.029987                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.029913                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.160053                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.160053                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056319                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056319                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.211550                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.211550                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.029879                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.029987                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056319                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.192917                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.110876                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.029879                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.029987                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056319                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.192917                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.110876                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26993.399340                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23746.376812                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25977.324263                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   588.491119                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   588.491119                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   455.086304                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   455.086304                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 217999.800000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 217999.800000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63575.310182                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63575.310182                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55069.232505                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55069.232505                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32979.096874                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32979.096874                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26993.399340                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23746.376812                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55069.232505                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42164.009017                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 46004.565139                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26993.399340                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23746.376812                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55069.232505                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42164.009017                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 46004.565139                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10584                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       226675                       # number of writebacks
system.cpu0.l2cache.writebacks::total          226675                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1590                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1590                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           30                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           30                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1620                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1620                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1620                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1620                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          303                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          138                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          441                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       262593                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       262593                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        54610                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        54610                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19582                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19582                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41691                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41691                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        62059                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        62059                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100864                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100864                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          303                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          138                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        62059                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       142555                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       205055                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          303                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          138                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        62059                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       142555                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       262593                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       467648                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31782                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40804                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28454                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28454                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60236                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69258                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      6361000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2449000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      8810000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16813897141                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  16813897141                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    934853500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    934853500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    293341500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    293341500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       885999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       885999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2209696500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2209696500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3045187500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3045187500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2716829000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2716829000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      6361000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2449000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3045187500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4926525500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   7980523000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      6361000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2449000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3045187500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4926525500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16813897141                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  24794420141                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6377241500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7172882000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6377241500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7172882000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.029879                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.029987                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.029913                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.154173                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.154173                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056319                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056319                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.211487                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.211487                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.029879                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.029987                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056319                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.190749                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.110007                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.029879                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.029987                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056319                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.190749                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.250882                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19977.324263                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64030.256484                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17118.723677                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17118.723677                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14980.160351                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14980.160351                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 177199.800000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 177199.800000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53001.762970                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53001.762970                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49069.232505                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49069.232505                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26935.566704                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26935.566704                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49069.232505                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34558.770299                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38918.938821                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20993.399340                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17746.376812                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49069.232505                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34558.770299                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64030.256484                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53019.408061                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200655.764269                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175788.697187                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105870.932665                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103567.558982                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      3728751                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1879521                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27804                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       211480                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       209803                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1677                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq         61377                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1688185                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28454                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28454                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       702444                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1317788                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict        79827                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       309039                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        86996                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41768                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       111544                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           48                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       289661                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       286091                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1101926                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       562800                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3273                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3323301                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2556545                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10999                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        24289                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5915134                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    141049272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     96382808                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        18408                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        40564                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         237491052                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     885699                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             18622452                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      2792086                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.090598                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.289121                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2540806     91.00%     91.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            249603      8.94%     99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              1677      0.06%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2792086                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3710834999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114296030                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1661911000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1204165985                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6397000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     14154986                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                     3359                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3359                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          669                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2690                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         3359                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3359    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3359                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2589                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12693.897258                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11812.728196                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5453.033399                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-4095            2      0.08%      0.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::4096-8191          579     22.36%     22.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-12287         1101     42.53%     64.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::12288-16383          577     22.29%     87.25% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-20479           84      3.24%     90.50% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::20480-24575          148      5.72%     96.21% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-28671           49      1.89%     98.11% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::28672-32767           18      0.70%     98.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-36863           23      0.89%     99.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::36864-40959            2      0.08%     99.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-45055            4      0.15%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-53247            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-61439            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2589                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1937787828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1937787828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1937787828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1928     74.47%     74.47% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          661     25.53%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2589                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3359                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3359                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2589                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2589                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5948                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3975776                       # DTB read hits
system.cpu1.dtb.read_misses                      2856                       # DTB read misses
system.cpu1.dtb.write_hits                    3446428                       # DTB write hits
system.cpu1.dtb.write_misses                      503                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1973                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   329                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3978632                       # DTB read accesses
system.cpu1.dtb.write_accesses                3446931                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7422204                       # DTB hits
system.cpu1.dtb.misses                           3359                       # DTB misses
system.cpu1.dtb.accesses                      7425563                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1578                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13066.847335                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12198.452511                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5775.216215                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          143     12.92%     12.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          638     57.63%     70.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          167     15.09%     85.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           51      4.61%     90.24% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575           51      4.61%     94.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           28      2.53%     97.38% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           17      1.54%     98.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.09%     99.01% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.45%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.27%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            3      0.27%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1938367828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1938367828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1938367828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    16753470                       # ITB inst hits
system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1084                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                16755216                       # ITB inst accesses
system.cpu1.itb.hits                         16753470                       # DTB hits
system.cpu1.itb.misses                           1746                       # DTB misses
system.cpu1.itb.accesses                     16755216                       # DTB accesses
system.cpu1.numPwrStateTransitions               5461                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2731                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1041523757.275357                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25854556705.104488                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1955     71.59%     71.59% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          770     28.19%     99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 929980418584                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2731                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    26587545381                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844401381119                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                      5741033861                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2731                       # number of quiesce instructions executed
system.cpu1.committedInsts                   16397270                       # Number of instructions committed
system.cpu1.committedOps                     19964987                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             17986629                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
system.cpu1.num_func_calls                    1033857                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1854028                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    17986629                       # number of integer instructions
system.cpu1.num_fp_insts                         1792                       # number of float instructions
system.cpu1.num_int_register_reads           32622652                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          12608250                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            72946565                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            6544066                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      7656991                       # number of memory refs
system.cpu1.num_load_insts                    4087327                       # Number of load instructions
system.cpu1.num_store_insts                   3569664                       # Number of store instructions
system.cpu1.num_idle_cycles              5687867512.323336                       # Number of idle cycles
system.cpu1.num_busy_cycles              53166348.676665                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.009261                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.990739                       # Percentage of idle cycles
system.cpu1.Branches                          2968001                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 12630695     62.17%     62.17% # Class of executed instruction
system.cpu1.op_class::IntMult                   26529      0.13%     62.30% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatMisc                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3311      0.02%     62.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.31% # Class of executed instruction
system.cpu1.op_class::MemRead                 4086811     20.11%     82.43% # Class of executed instruction
system.cpu1.op_class::MemWrite                3568388     17.56%     99.99% # Class of executed instruction
system.cpu1.op_class::FloatMemRead                516      0.00%     99.99% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite              1276      0.01%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  20317592                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           188214                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          469.650282                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7155880                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           188578                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.946526                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     105561245500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.650282                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.917286                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.917286                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          343                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           21                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.710938                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         15064679                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        15064679                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      3662279                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3662279                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3257080                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3257080                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49206                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        49206                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79332                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        79332                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71298                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71298                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6919359                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6919359                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6968565                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6968565                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       134376                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       134376                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        92202                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        92202                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30516                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30516                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17009                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17009                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23197                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23197                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       226578                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        226578                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       257094                       # number of overall misses
system.cpu1.dcache.overall_misses::total       257094                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2053970000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2053970000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2521876000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2521876000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    321694000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    321694000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    544347500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    544347500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1836500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1836500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4575846000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4575846000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4575846000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4575846000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3796655                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3796655                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3349282                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3349282                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79722                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79722                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96341                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96341                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94495                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94495                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      7145937                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7145937                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      7225659                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7225659                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035393                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035393                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027529                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.027529                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382780                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382780                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.176550                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.176550                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.245484                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.245484                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031707                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031707                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035581                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035581                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15285.244389                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15285.244389                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27351.640962                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 27351.640962                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18913.163619                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18913.163619                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23466.288744                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23466.288744                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20195.455870                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20195.455870                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17798.338351                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17798.338351                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       188214                       # number of writebacks
system.cpu1.dcache.writebacks::total           188214                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          253                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          253                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12043                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12043                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          253                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          253                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          253                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          253                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       134123                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       134123                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        92202                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        92202                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29799                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29799                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4966                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4966                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23197                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23197                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       226325                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       226325                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       256124                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       256124                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3085                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3085                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2441                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2441                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5526                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5526                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1909849500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1909849500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2429674000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2429674000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    508192000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    508192000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89547000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89547000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521193500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521193500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1793500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1793500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4339523500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4339523500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4847715500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4847715500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    443097000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    443097000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    443097000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    443097000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035327                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035327                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027529                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027529                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.373786                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.373786                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.051546                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.051546                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.245484                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.245484                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031672                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031672                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035446                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035446                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14239.537589                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14239.537589                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26351.640962                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26351.640962                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17053.995101                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17053.995101                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18032.017720                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18032.017720                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22468.142432                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22468.142432                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19173.858389                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19173.858389                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18927.220799                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18927.220799                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143629.497569                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143629.497569                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80184.039088                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80184.039088                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           506865                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.456606                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           16246088                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           507377                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            32.019757                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      85409397000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.456606                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973548                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973548                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          389                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          119                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            4                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         34014307                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        34014307                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     16246088                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       16246088                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     16246088                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        16246088                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     16246088                       # number of overall hits
system.cpu1.icache.overall_hits::total       16246088                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       507377                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       507377                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       507377                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        507377                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       507377                       # number of overall misses
system.cpu1.icache.overall_misses::total       507377                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4790701000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4790701000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4790701000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4790701000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4790701000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4790701000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     16753465                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     16753465                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     16753465                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     16753465                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     16753465                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     16753465                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030285                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030285                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030285                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030285                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030285                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030285                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9442.093355                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9442.093355                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9442.093355                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9442.093355                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9442.093355                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9442.093355                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       506865                       # number of writebacks
system.cpu1.icache.writebacks::total           506865                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       507377                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       507377                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       507377                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       507377                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       507377                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       507377                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4537012500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4537012500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4537012500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4537012500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4537012500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4537012500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     17068500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     17068500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     17068500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     17068500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030285                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030285                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030285                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.030285                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030285                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.030285                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8942.093355                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8942.093355                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8942.093355                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8942.093355                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8942.093355                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8942.093355                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       202159                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       202159                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        59833                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           43683                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14553.446834                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            604546                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           57834                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           10.453124                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14136.855711                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.245443                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.035798                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   412.309882                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.862845                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000137                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000124                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.025165                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.888272                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          316                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           10                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13825                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          293                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1016                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2429                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10380                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.019287                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000610                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.843811                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        24413579                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       24413579                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3816                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2015                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          5831                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       114934                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       114934                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       568988                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       568988                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27893                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27893                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       485948                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       485948                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99069                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        99069                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3816                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2015                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       485948                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       126962                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         618741                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3816                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2015                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       485948                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       126962                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        618741                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          441                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          325                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          766                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29445                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29445                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23189                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23189                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34864                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34864                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        21429                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        21429                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69819                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        69819                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          441                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          325                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        21429                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       104683                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       126878                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          441                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          325                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        21429                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       104683                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       126878                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      9097000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6572000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     15669000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     14547500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     14547500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     17306000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     17306000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1729000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1729000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1479795000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1479795000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    845906500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    845906500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1606277000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1606277000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      9097000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6572000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    845906500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3086072000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3947647500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      9097000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6572000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    845906500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3086072000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3947647500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         4257                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2340                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         6597                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       114934                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       114934                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       568988                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       568988                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29445                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29445                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23189                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23189                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62757                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62757                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       507377                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       507377                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       168888                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       168888                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         4257                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2340                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       507377                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       231645                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       745619                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         4257                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2340                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       507377                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       231645                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       745619                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.103594                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.138889                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.116113                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.555540                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.555540                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.042235                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.042235                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.413404                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.413404                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.103594                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.138889                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.042235                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.451911                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.170165                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.103594                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.138889                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.042235                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.451911                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.170165                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20628.117914                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20221.538462                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20455.613577                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   494.056716                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   494.056716                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   746.302126                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   746.302126                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       216125                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       216125                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42444.785452                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42444.785452                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39474.847170                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39474.847170                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23006.302009                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23006.302009                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20628.117914                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20221.538462                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39474.847170                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29480.163923                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31113.727360                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20628.117914                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20221.538462                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39474.847170                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29480.163923                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31113.727360                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             815                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        32960                       # number of writebacks
system.cpu1.l2cache.writebacks::total           32960                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           84                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           84                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           84                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           84                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           84                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           84                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          441                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          325                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          766                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25865                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        25865                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29445                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29445                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23189                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23189                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34780                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34780                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        21429                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        21429                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69819                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69819                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          441                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          325                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        21429                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104599                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       126794                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          441                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          325                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        21429                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104599                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25865                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       152659                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3085                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3262                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2441                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2441                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5526                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5703                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6451000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4622000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11073000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    943203517                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    943203517                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    450885000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    450885000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    347198000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    347198000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1471000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1471000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1260374500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1260374500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    717332500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    717332500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1187363000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1187363000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6451000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4622000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    717332500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2447737500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3176143000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6451000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4622000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    717332500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2447737500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    943203517                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4119346517                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15741000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    418070500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    433811500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     15741000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    418070500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    433811500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.103594                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.138889                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.116113                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.554201                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.554201                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.042235                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042235                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.413404                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.413404                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.103594                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.138889                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.042235                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.451549                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.170052                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.103594                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.138889                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.042235                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.451549                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.204741                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14455.613577                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36466.403132                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15312.786551                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15312.786551                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14972.530079                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.530079                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       183875                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       183875                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36238.484761                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36238.484761                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33474.847170                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33474.847170                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17006.302009                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17006.302009                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33474.847170                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23401.155843                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25049.631686                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14628.117914                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14221.538462                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33474.847170                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23401.155843                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36466.403132                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26983.974197                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135517.179903                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132989.423666                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75655.175534                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76067.245309                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1493074                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       754096                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11157                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       112771                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       104472                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8299                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         12635                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       726264                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2441                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2441                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       148991                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       580145                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        27848                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        30881                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        70910                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40918                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85257                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        69946                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        67407                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       507377                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       264100                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          245                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1521973                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       842546                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5664                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        10306                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2380489                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     64912196                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29583168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         9360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        17028                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          94521752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     332142                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              4881760                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1061400                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.130546                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.359362                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            931138     87.73%     87.73% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            121963     11.49%     99.22% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              8299      0.78%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1061400                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1447209000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79433455                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    761242500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    378138998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      6050996                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180874                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48592000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               318500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                31500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                15000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                92000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               615500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               46500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6203500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            32039500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187757841                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.377097                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         290025611000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.377097                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898569                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898569                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36479                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
system.iocache.overall_misses::total            36479                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     40988875                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     40988875                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4375977966                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4375977966                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4416966841                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4416966841                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4416966841                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4416966841                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36479                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36479                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36479                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36479                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 160740.686275                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 160740.686275                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120803.278655                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120803.278655                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 121082.454042                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121082.454042                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 121082.454042                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121082.454042                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            56                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    6                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.333333                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36479                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     28238875                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     28238875                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2562446714                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2562446714                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2590685589                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2590685589                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2590685589                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2590685589                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110740.686275                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 110740.686275                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70738.922096                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70738.922096                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 71018.547356                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 71018.547356                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 71018.547356                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 71018.547356                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   137086                       # number of replacements
system.l2c.tags.tagsinuse                65074.643000                       # Cycle average of tags in use
system.l2c.tags.total_refs                     524868                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   202455                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.592517                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             103102985000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    6607.466111                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.944223                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.038978                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7194.422354                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6927.905114                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37164.228779                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1475.884148                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3147.084233                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2554.669060                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.100822                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.109778                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.105711                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.567081                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.022520                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.048021                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.038981                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.992960                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        34101                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        31263                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          163                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4783                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        29155                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1095                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30056                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.520340                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.477036                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6098343                       # Number of tag accesses
system.l2c.tags.data_accesses                 6098343                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       259635                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          259635                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           39907                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4995                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               44902                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2353                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          2177                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              4530                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3978                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1485                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5463                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          146                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           71                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        44179                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        52512                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45683                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           56                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           30                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        19035                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        10985                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5208                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           177905                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           146                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            71                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               44179                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               56490                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        45683                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            56                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            30                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               19035                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12470                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5208                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  183368                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          146                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           71                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              44179                       # number of overall hits
system.l2c.overall_hits::cpu0.data              56490                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        45683                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           56                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           30                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              19035                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12470                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5208                       # number of overall hits
system.l2c.overall_hits::total                 183368                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data           508                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           339                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total               847                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          113                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          106                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             219                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11276                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7954                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19230                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17880                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9100                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133915                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2394                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          952                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6331                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         170581                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17880                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20376                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133915                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2394                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8906                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6331                       # number of demand (read+write) misses
system.l2c.demand_misses::total                189811                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17880                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20376                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133915                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2394                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8906                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6331                       # number of overall misses
system.l2c.overall_misses::total               189811                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      9776500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1123500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     10900000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       603500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       259000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       862500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1642507500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    809344500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2451852000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      1270000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       179500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1949692500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1106153000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  16003328825                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    265577500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    121124000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    827024607                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  20274349932                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1270000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       179500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1949692500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2748660500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  16003328825                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    265577500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    930468500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    827024607                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     22726201932                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1270000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       179500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1949692500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2748660500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  16003328825                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    265577500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    930468500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    827024607                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    22726201932                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       259635                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       259635                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        40415                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5334                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45749                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2466                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2283                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4749                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15254                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9439                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24693                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          153                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           73                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        62059                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        61612                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179598                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           56                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           30                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        21429                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        11937                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11539                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       348486                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          153                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           73                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           62059                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           76866                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179598                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           56                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           30                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           21429                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21376                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11539                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              373179                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          153                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           73                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          62059                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          76866                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179598                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           56                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           30                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          21429                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21376                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11539                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             373179                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.012570                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.063555                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.018514                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.045823                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.046430                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.046115                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.739216                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.842674                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.778763                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.045752                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.288113                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.147699                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.745637                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.111718                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.079752                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.548661                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.489492                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.045752                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.288113                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.265085                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.745637                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.111718                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.416635                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.548661                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.508633                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.045752                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.288113                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.265085                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.745637                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.111718                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.416635                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.548661                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.508633                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19245.078740                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3314.159292                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 12868.949233                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5340.707965                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2443.396226                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3938.356164                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145664.020929                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101753.143073                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127501.404056                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 181428.571429                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        89750                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109043.204698                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121555.274725                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110934.628237                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 127231.092437                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 118854.678610                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 181428.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        89750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 109043.204698                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 134896.962112                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 110934.628237                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 104476.588817                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 119730.689644                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 181428.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        89750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 109043.204698                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 134896.962112                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119503.631595                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 110934.628237                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 104476.588817                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130630.959880                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 119730.689644                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              100785                       # number of writebacks
system.l2c.writebacks::total                   100785                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  5                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 5                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3664                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3664                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data          508                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          339                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          847                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          113                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          106                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          219                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11276                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7954                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19230                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17879                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9100                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133915                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2390                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          952                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6331                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       170576                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17879                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20376                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133915                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2390                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8906                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6331                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           189806                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17879                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20376                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133915                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2390                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8906                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6331                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          189806                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31782                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3082                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44063                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28454                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2441                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30895                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60236                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5523                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        74958                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     11966500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7400000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     19366500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      2957500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2539000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      5496500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1529747500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    729804500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2259552000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      1200000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       159500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1770876500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1015153000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14664172837                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    241454001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    111604000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    763713609                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  18568333447                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1200000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       159500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1770876500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2544900500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  14664172837                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    241454001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    841408500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    763713609                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  20827885447                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1200000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       159500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1770876500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2544900500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14664172837                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    241454001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    841408500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    763713609                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  20827885447                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5805153000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12555000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    362546500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6813498500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5805153000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12555000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    362546500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6813498500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.012570                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.063555                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.018514                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.045823                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.046430                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.046115                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.739216                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.842674                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.778763                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.045752                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.288097                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.147699                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.745637                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.111531                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.079752                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.548661                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.489477                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.045752                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.288097                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.265085                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.745637                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.111531                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.416635                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.548661                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.508619                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.045752                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.288097                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.265085                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.745637                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.111531                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.416635                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.548661                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.508619                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23556.102362                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21828.908555                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22864.817001                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26172.566372                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23952.830189                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25098.173516                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135664.020929                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 91753.143073                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117501.404056                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        79750                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99047.849432                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111555.274725                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101026.778661                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 117231.092437                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108856.658891                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        79750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99047.849432                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124896.962112                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101026.778661                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94476.588817                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 109732.492371                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 171428.571429                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        79750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99047.849432                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124896.962112                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109503.586880                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101026.778661                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94476.588817                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120630.802243                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 109732.492371                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182655.370965                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117633.517197                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154630.835395                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96373.480975                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65643.038204                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 90897.549294                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        503139                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       282937                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          589                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               44063                       # Transaction distribution
system.membus.trans_dist::ReadResp             214894                       # Transaction distribution
system.membus.trans_dist::WriteReq              30895                       # Transaction distribution
system.membus.trans_dist::WriteResp             30895                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       136975                       # Transaction distribution
system.membus.trans_dist::CleanEvict            16276                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            64763                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          38177                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              17                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39789                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19204                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        170831                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13664                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       647846                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       769460                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 842399                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18630604                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18820796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21137916                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123039                       # Total snoops (count)
system.membus.snoopTraffic                      37632                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            424743                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.012198                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.109769                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  419562     98.78%     98.78% # Request fanout histogram
system.membus.snoop_fanout::1                    5181      1.22%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              424743                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88158500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11394500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           971210962                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1112716909                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1441377                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1012483                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       538775                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       174846                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          29019                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        27944                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1075                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870988926500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              44066                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            511105                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30895                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30895                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       360420                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          118997                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          109639                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         42707                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         152346                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           77                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50919                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50919                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       467041                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4574                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1269868                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       316423                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1586291                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35149508                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5612856                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               40762364                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          388626                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  15721036                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           887021                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.395992                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.491535                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 536843     60.52%     60.52% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 349103     39.36%     99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1075      0.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             887021                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          892902016                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360623                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         675868420                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         239041660                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------