path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.194884                       # Number of seconds simulated
sim_ticks                                1194883580500                       # Number of ticks simulated
final_tick                               1194883580500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 298011                       # Simulator instruction rate (inst/s)
host_op_rate                                   379758                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             5802481089                       # Simulator tick rate (ticks/s)
host_mem_usage                                 399660                       # Number of bytes of host memory used
host_seconds                                   205.93                       # Real time elapsed on the host
sim_insts                                    61368273                       # Number of instructions simulated
sim_ops                                      78202205                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           463716                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          6626292                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           256092                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          2904240                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62155300                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       463716                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       256092                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          719808                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4136384                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data       3027304                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7163728                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             13464                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            103608                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              4083                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             45405                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6654631                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           64631                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           756826                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               821467                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43438970                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              388085                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             5545554                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              214324                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             2430563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52017871                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         388085                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         214324                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             602408                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3461746                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data            2533556                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 33                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5995336                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3461746                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43438970                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             388085                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            8079110                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             214324                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            2430597                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               58013207                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6654631                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       821467                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                     6654631                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     821467                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                    425896384                       # Total number of bytes read from memory
system.physmem.bytesWritten                  52573888                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               62155300                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                7163728                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      531                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite              10643                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                415730                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                415559                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                414958                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                415336                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                422327                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                415339                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                415446                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                415286                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                415350                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                415631                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               415270                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               414743                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               415547                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               416088                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               415759                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               415731                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7326                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7216                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  6699                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  6873                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7393                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  6968                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7176                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6994                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  6995                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7264                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 6985                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 6704                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7238                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7541                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7391                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 7368                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    1194879167500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                    6825                       # Categorize read packet sizes
system.physmem.readPktSize::3                 6488064                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  159742                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 756836                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  64631                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    586175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    426728                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    441027                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1598520                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1190036                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1186243                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1162812                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      9752                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      7190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     12576                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    17869                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    12223                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      819                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      704                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      675                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      658                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       89                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        34155                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    12682.337813                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     707.328285                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   25224.390929                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-127          7803     22.85%     22.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-191         4015     11.76%     34.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-255         2702      7.91%     42.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-319         1928      5.64%     48.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-383         1397      4.09%     52.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-447         1203      3.52%     55.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-511          946      2.77%     58.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-575          826      2.42%     60.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-639          667      1.95%     62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-703          557      1.63%     64.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-767          438      1.28%     65.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-831          432      1.26%     67.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-895          317      0.93%     68.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-959          252      0.74%     68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-1023          181      0.53%     69.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1087          297      0.87%     70.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1151          146      0.43%     70.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1215          131      0.38%     70.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1279          122      0.36%     71.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1343           99      0.29%     71.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1407           97      0.28%     71.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1471          161      0.47%     72.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1535          728      2.13%     74.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1599          239      0.70%     75.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1663          168      0.49%     75.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1727          146      0.43%     76.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1791          103      0.30%     76.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1855           87      0.25%     76.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1919           68      0.20%     76.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1983           55      0.16%     77.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2047           40      0.12%     77.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2111           46      0.13%     77.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2175           38      0.11%     77.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2239           21      0.06%     77.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2303           23      0.07%     77.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2367           20      0.06%     77.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2431           20      0.06%     77.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2495           20      0.06%     77.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2559           23      0.07%     77.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2623           11      0.03%     77.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2687           12      0.04%     77.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2751           19      0.06%     77.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2815            8      0.02%     77.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2879           17      0.05%     77.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2943           10      0.03%     77.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-3007            5      0.01%     78.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3071            7      0.02%     78.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3135           13      0.04%     78.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3199            2      0.01%     78.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3263           15      0.04%     78.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3327            7      0.02%     78.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3391           12      0.04%     78.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3455           12      0.04%     78.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3519            8      0.02%     78.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3583            8      0.02%     78.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3647           11      0.03%     78.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3711           11      0.03%     78.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3775            6      0.02%     78.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3839            9      0.03%     78.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3903            4      0.01%     78.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3967            5      0.01%     78.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-4031           11      0.03%     78.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4095            7      0.02%     78.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4159           32      0.09%     78.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4223            4      0.01%     78.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4287            3      0.01%     78.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4351            5      0.01%     78.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4415            6      0.02%     78.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4479            3      0.01%     78.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4543            3      0.01%     78.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4607            8      0.02%     78.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4671            7      0.02%     78.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4735            5      0.01%     78.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4799            2      0.01%     78.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4863            4      0.01%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4927            4      0.01%     78.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4991            6      0.02%     78.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5055            4      0.01%     78.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5119            2      0.01%     78.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5183            5      0.01%     78.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5247            1      0.00%     78.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5311            2      0.01%     78.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5439            1      0.00%     78.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5631            4      0.01%     78.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5695            2      0.01%     78.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5759            2      0.01%     78.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5823            3      0.01%     78.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5887            4      0.01%     78.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5951            1      0.00%     78.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-6015            2      0.01%     78.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6143            4      0.01%     78.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6207            5      0.01%     78.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6271            1      0.00%     78.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6335            2      0.01%     78.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6399            2      0.01%     78.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6463            1      0.00%     78.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6527            2      0.01%     78.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6591            1      0.00%     78.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6719            4      0.01%     78.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6783            1      0.00%     78.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6847           22      0.06%     78.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6911            3      0.01%     78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6975            1      0.00%     78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7039            1      0.00%     78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7103            5      0.01%     78.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7231            7      0.02%     78.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7359            3      0.01%     79.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7487            2      0.01%     79.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7551            2      0.01%     79.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7615            3      0.01%     79.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7679            3      0.01%     79.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7743            3      0.01%     79.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7807            2      0.01%     79.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7871            6      0.02%     79.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7935            7      0.02%     79.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7999            1      0.00%     79.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8063            3      0.01%     79.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8127            9      0.03%     79.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8191            6      0.02%     79.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8255          323      0.95%     80.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8319            1      0.00%     80.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8511           25      0.07%     80.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8575          138      0.40%     80.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8639          174      0.51%     81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8767            2      0.01%     81.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8895            1      0.00%     81.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8959            1      0.00%     81.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9471            1      0.00%     81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-10047            3      0.01%     81.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10303            1      0.00%     81.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10815            2      0.01%     81.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11071            1      0.00%     81.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11327            4      0.01%     81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11839            2      0.01%     81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12095            1      0.00%     81.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12351            2      0.01%     81.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12607            1      0.00%     81.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12863            3      0.01%     81.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13119            1      0.00%     81.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13375            3      0.01%     81.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13631            1      0.00%     81.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13887            1      0.00%     81.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14143            1      0.00%     81.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14271            1      0.00%     81.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14399            1      0.00%     81.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14911            3      0.01%     81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15167            2      0.01%     81.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15423            5      0.01%     81.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15679            1      0.00%     81.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16191            1      0.00%     81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16447            1      0.00%     81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16703            1      0.00%     81.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16959            1      0.00%     81.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17215            1      0.00%     81.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17471            4      0.01%     81.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18239            1      0.00%     81.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18495            3      0.01%     81.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18751            1      0.00%     81.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-19007            1      0.00%     81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19136-19199            1      0.00%     81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19263            1      0.00%     81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19391            1      0.00%     81.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19519            3      0.01%     81.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19775            2      0.01%     81.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-20031            2      0.01%     81.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20543            4      0.01%     81.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-21055            1      0.00%     81.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21311            3      0.01%     81.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21567            5      0.01%     81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22335            1      0.00%     81.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23615            2      0.01%     81.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24127            3      0.01%     81.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24383            1      0.00%     81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24639            2      0.01%     81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25151            1      0.00%     81.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25663            3      0.01%     81.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26175            2      0.01%     81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26431            1      0.00%     81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26687            1      0.00%     81.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27199            3      0.01%     81.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27455            4      0.01%     81.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27711            2      0.01%     81.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28479            1      0.00%     81.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28735            3      0.01%     81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28991            1      0.00%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29247            1      0.00%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29503            1      0.00%     81.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29759            4      0.01%     81.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-30015            1      0.00%     81.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30271            1      0.00%     81.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-31039            3      0.01%     81.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31295            3      0.01%     81.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31551            2      0.01%     81.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31807            3      0.01%     81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32831            4      0.01%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33087           11      0.03%     81.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33343           42      0.12%     81.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33855            1      0.00%     81.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34111            1      0.00%     81.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34112-34175            1      0.00%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35135            1      0.00%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35903            1      0.00%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36927            1      0.00%     81.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37183            1      0.00%     81.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37951            2      0.01%     81.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38207            1      0.00%     81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38975            1      0.00%     81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41535            1      0.00%     81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42047            1      0.00%     81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42303            1      0.00%     81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44095            1      0.00%     81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44863            1      0.00%     81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45119            2      0.01%     81.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45631            1      0.00%     81.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45887            1      0.00%     81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46208-46271            1      0.00%     81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47423            1      0.00%     81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48191            1      0.00%     81.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48959            1      0.00%     81.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49215            1      0.00%     81.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49408-49471            1      0.00%     81.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50239            2      0.01%     81.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50751            1      0.00%     81.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51328-51391            1      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52287            1      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52480-52543            1      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52992-53055            1      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53311            2      0.01%     81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::55552-55615            1      0.00%     81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56128-56191            1      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57088-57151            1      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58112-58175            1      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58368-58431            1      0.00%     81.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59392-59455            1      0.00%     81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60928-60991            1      0.00%     81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61440-61503            2      0.01%     81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61952-62015            1      0.00%     81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62464-62527            1      0.00%     81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62720-62783            1      0.00%     81.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63680-63743            1      0.00%     81.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65024-65087           39      0.11%     81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65343            1      0.00%     81.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65472-65535            1      0.00%     81.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65599         6180     18.09%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::66880-66943            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::66944-67007            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::67904-67967            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::74048-74111            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::74112-74175            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          34155                       # Bytes accessed per row activation
system.physmem.totQLat                   126519681500                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              168380906500                       # Sum of mem lat for all requests
system.physmem.totBusLat                  33270500000                       # Total cycles spent in databus access
system.physmem.totBankLat                  8590725000                       # Total cycles spent in bank access
system.physmem.avgQLat                       19013.79                       # Average queueing delay per request
system.physmem.avgBankLat                     1291.04                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  25304.84                       # Average memory access latency
system.physmem.avgRdBW                         356.43                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          44.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  52.02                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.13                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.14                       # Average read queue length over time
system.physmem.avgWrQLen                        14.04                       # Average write queue length over time
system.physmem.readRowHits                    6636405                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97666                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.73                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  11.89                       # Row buffer hit rate for writes
system.physmem.avgGap                       159826.58                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     60029719                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             7703148                       # Transaction distribution
system.membus.trans_dist::ReadResp            7703148                       # Transaction distribution
system.membus.trans_dist::WriteReq             767203                       # Transaction distribution
system.membus.trans_dist::WriteResp            767203                       # Transaction distribution
system.membus.trans_dist::Writeback             64631                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            27692                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          16414                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           10643                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137763                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137302                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382562                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         8866                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          906                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1966647                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4359019                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               17335147                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389878                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        17732                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17414516                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     19824014                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            71728526                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               71728526                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1208318500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             7968000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy              776500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy          9149406000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         5034563338                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.respLayer2.occupancy        14646378749                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
system.l2c.tags.replacements                    69624                       # number of replacements
system.l2c.tags.tagsinuse                53154.717455                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1650852                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   134785                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    12.248039                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   40039.692381                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.667893                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001521                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4638.680952                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     5789.816440                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001659                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1927.067698                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      756.788910                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.610957                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000041                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.070781                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.088346                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.029405                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.011548                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.811077                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         4524                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         1438                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             483013                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             241892                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         3782                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1869                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             372280                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             110462                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1219260                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          576006                       # number of Writeback hits
system.l2c.Writeback_hits::total               576006                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1292                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             416                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1708                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           255                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           100                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               355                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            65542                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            45349                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               110891                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4524                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          1438                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              483013                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              307434                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          3782                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1869                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              372280                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              155811                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1330151                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4524                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         1438                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             483013                       # number of overall hits
system.l2c.overall_hits::cpu0.data             307434                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         3782                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1869                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             372280                       # number of overall hits
system.l2c.overall_hits::cpu1.data             155811                       # number of overall hits
system.l2c.overall_hits::total                1330151                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             6832                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             9716                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             3996                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1890                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22441                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          3974                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3371                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              7345                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          385                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          476                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             861                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          95136                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          44603                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139739                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              6832                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            104852                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              3996                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             46493                       # number of demand (read+write) misses
system.l2c.demand_misses::total                162180                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             6832                       # number of overall misses
system.l2c.overall_misses::cpu0.data           104852                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             3996                       # number of overall misses
system.l2c.overall_misses::cpu1.data            46493                       # number of overall misses
system.l2c.overall_misses::total               162180                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       687750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       122500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    482771250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    688091749                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        89250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    282183750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    151111000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1605057249                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     11611000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12427970                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     24038970                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1906918                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1117452                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3024370                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   6193599427                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2824169884                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9017769311                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       687750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       122500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    482771250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   6881691176                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        89250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    282183750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   2975280884                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     10622826560                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       687750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       122500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    482771250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   6881691176                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        89250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    282183750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   2975280884                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    10622826560                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         4528                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         1440                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         489845                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         251608                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         3782                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1870                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         376276                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         112352                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1241701                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       576006                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           576006                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         5266                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3787                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            9053                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          640                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          576                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1216                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       160678                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        89952                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           250630                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         4528                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         1440                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          489845                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          412286                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         3782                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1870                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          376276                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          202304                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1492331                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         4528                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         1440                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         489845                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         412286                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         3782                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1870                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         376276                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         202304                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1492331                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000883                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001389                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013947                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.038616                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000535                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010620                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.016822                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.018073                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.754652                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.890151                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.811333                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.601562                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.826389                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.708059                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.592091                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.495853                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.557551                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000883                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.001389                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013947                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.254319                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000535                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010620                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.229818                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.108676                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000883                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.001389                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013947                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.254319                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000535                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010620                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.229818                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.108676                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        61250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        89250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 71523.428056                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2921.741319                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3686.730940                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3272.834581                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4953.033766                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2347.588235                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3512.624855                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 64532.945785                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        61250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        89250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 65500.225429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        61250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        89250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 65500.225429                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               64631                       # number of writebacks
system.l2c.writebacks::total                    64631                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         6831                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         9716                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         3996                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1890                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22440                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         3974                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3371                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         7345                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          385                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          476                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          861                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        95136                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        44603                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139739                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         6831                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       104852                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         3996                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        46493                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           162179                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         6831                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       104852                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         3996                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        46493                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          162179                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       635750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        97500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    396501000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    564859249                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        76250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    231739250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    127085000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1320993999                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     39771967                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     33821856                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     73593823                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3851884                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4768975                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      8620859                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   5000986069                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2264195114                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7265181183                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       635750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        97500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    396501000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   5565845318                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        76250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    231739250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   2391280114                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   8586175182                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       635750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        97500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    396501000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   5565845318                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        76250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    231739250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   2391280114                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   8586175182                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    323836500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12647640494                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      4849500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  16272049535                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    486218500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16758268035                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    323836500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  28919690029                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      4849500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183805138029                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000883                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001389                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013945                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.038616                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000535                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010620                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.016822                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.018072                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.754652                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.890151                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.811333                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.601562                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.826389                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.708059                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.592091                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.495853                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.557551                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000883                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001389                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013945                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.254319                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000535                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010620                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.229818                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.108675                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000883                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001389                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013945                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.254319                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000535                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010620                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.229818                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.108675                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        48750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        76250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        48750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        76250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 52942.583084                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        48750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        76250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 52942.583084                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                   118384606                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2504676                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2504676                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            767203                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           767203                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           576006                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           26963                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         16769                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          43732                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           262452                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          262452                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       993712                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2951029                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         5836                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        14921                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       753525                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2879302                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6196                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        11995                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7616516                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     31376632                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     53718524                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         5760                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        18112                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     24082060                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     27916814                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7480                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15128                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          137140510                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             137140510                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4315312                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4764811697                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2217607730                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        2471552710                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           4396500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          10394000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy        1697838714                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy        2214012427                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy           4326250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy           8213499                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      45439063                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq              7671399                       # Transaction distribution
system.iobus.trans_dist::ReadResp             7671399                       # Transaction distribution
system.iobus.trans_dist::WriteReq                7946                       # Transaction distribution
system.iobus.trans_dist::WriteResp               7946                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30448                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8060                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          740                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382562                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                15358690                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40166                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1480                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2389878                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             54294390                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                54294390                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21350000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4036000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               376000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               298000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374616000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         17783069251                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     9653247                       # DTB read hits
system.cpu0.dtb.read_misses                      3738                       # DTB read misses
system.cpu0.dtb.write_hits                    7597488                       # DTB write hits
system.cpu0.dtb.write_misses                     1585                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1811                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   134                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 9656985                       # DTB read accesses
system.cpu0.dtb.write_accesses                7599073                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         17250735                       # DTB hits
system.cpu0.dtb.misses                           5323                       # DTB misses
system.cpu0.dtb.accesses                     17256058                       # DTB accesses
system.cpu0.itb.inst_hits                    43297764                       # ITB inst hits
system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1332                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                43299969                       # ITB inst accesses
system.cpu0.itb.hits                         43297764                       # DTB hits
system.cpu0.itb.misses                           2205                       # DTB misses
system.cpu0.itb.accesses                     43299969                       # DTB accesses
system.cpu0.numCycles                      2389767161                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   42570861                       # Number of instructions committed
system.cpu0.committedOps                     53303375                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             48060351                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
system.cpu0.num_func_calls                    1403492                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      5582702                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    48060351                       # number of integer instructions
system.cpu0.num_fp_insts                         3860                       # number of float instructions
system.cpu0.num_int_register_reads          272449792                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          52270848                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
system.cpu0.num_mem_refs                     18020156                       # number of memory refs
system.cpu0.num_load_insts                   10037111                       # Number of load instructions
system.cpu0.num_store_insts                   7983045                       # Number of store instructions
system.cpu0.num_idle_cycles              2150298949.878201                       # Number of idle cycles
system.cpu0.num_busy_cycles              239468211.121800                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.100206                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.899794                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   51312                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           490078                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.399401                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           42807156                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           490590                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            87.256479                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      76013480250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.399401                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994921                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.994921                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     42807156                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       42807156                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     42807156                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        42807156                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     42807156                       # number of overall hits
system.cpu0.icache.overall_hits::total       42807156                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       490591                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       490591                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       490591                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        490591                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       490591                       # number of overall misses
system.cpu0.icache.overall_misses::total       490591                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6809993230                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   6809993230                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   6809993230                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   6809993230                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   6809993230                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   6809993230                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     43297747                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     43297747                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     43297747                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     43297747                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     43297747                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     43297747                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011331                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011331                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011331                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011331                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011331                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011331                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13881.202937                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13881.202937                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       490591                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       490591                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       490591                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       490591                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       490591                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       490591                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5825469770                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5825469770                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5825469770                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5825469770                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5825469770                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5825469770                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    415499500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    415499500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    415499500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    415499500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011331                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011331                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011331                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.011331                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011331                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.011331                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           406634                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          471.214045                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           15967998                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           407146                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            39.219341                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        643231250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.214045                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.920340                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.920340                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      9137347                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        9137347                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      6494912                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       6494912                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       156532                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       156532                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       159004                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       159004                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     15632259                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        15632259                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     15632259                       # number of overall hits
system.cpu0.dcache.overall_hits::total       15632259                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       263669                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       263669                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       176685                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       176685                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9910                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9910                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7384                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7384                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       440354                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        440354                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       440354                       # number of overall misses
system.cpu0.dcache.overall_misses::total       440354                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3876875497                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   3876875497                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7541622539                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   7541622539                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     98733750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     98733750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     40506385                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     40506385                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  11418498036                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  11418498036                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  11418498036                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  11418498036                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      9401016                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      9401016                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      6671597                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      6671597                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       166442                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       166442                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       166388                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       166388                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     16072613                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     16072613                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     16072613                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     16072613                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028047                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.028047                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026483                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.026483                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059540                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059540                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.044378                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.044378                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027398                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027398                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027398                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.027398                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9963.042381                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9963.042381                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5485.696777                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5485.696777                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       376568                       # number of writebacks
system.cpu0.dcache.writebacks::total           376568                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       263669                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       263669                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       176685                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       176685                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9910                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9910                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7379                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7379                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       440354                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       440354                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       440354                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       440354                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3344880503                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3344880503                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7142186461                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7142186461                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     78848250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     78848250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     25751615                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     25751615                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10487066964                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10487066964                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10487066964                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10487066964                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13764220500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13764220500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  25807115461                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  25807115461                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  39571335961                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  39571335961                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028047                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.028047                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026483                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026483                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059540                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059540                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.044348                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.044348                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027398                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027398                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027398                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.027398                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7956.432896                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7956.432896                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3489.851606                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3489.851606                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     5705173                       # DTB read hits
system.cpu1.dtb.read_misses                      3576                       # DTB read misses
system.cpu1.dtb.write_hits                    3872049                       # DTB write hits
system.cpu1.dtb.write_misses                      645                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1989                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   144                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 5708749                       # DTB read accesses
system.cpu1.dtb.write_accesses                3872694                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          9577222                       # DTB hits
system.cpu1.dtb.misses                           4221                       # DTB misses
system.cpu1.dtb.accesses                      9581443                       # DTB accesses
system.cpu1.itb.inst_hits                    19377969                       # ITB inst hits
system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1495                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                19380140                       # ITB inst accesses
system.cpu1.itb.hits                         19377969                       # DTB hits
system.cpu1.itb.misses                           2171                       # DTB misses
system.cpu1.itb.accesses                     19380140                       # DTB accesses
system.cpu1.numCycles                      2388332817                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   18797412                       # Number of instructions committed
system.cpu1.committedOps                     24898830                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             22263010                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
system.cpu1.num_func_calls                     796668                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2514459                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    22263010                       # number of integer instructions
system.cpu1.num_fp_insts                         6793                       # number of float instructions
system.cpu1.num_int_register_reads          130745617                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          23316317                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
system.cpu1.num_mem_refs                     10012651                       # number of memory refs
system.cpu1.num_load_insts                    5981805                       # Number of load instructions
system.cpu1.num_store_insts                   4030846                       # Number of store instructions
system.cpu1.num_idle_cycles              1968708722.646828                       # Number of idle cycles
system.cpu1.num_busy_cycles              419624094.353172                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.175697                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.824303                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   39053                       # number of quiesce instructions executed
system.cpu1.icache.tags.replacements           376539                       # number of replacements
system.cpu1.icache.tags.tagsinuse          474.945138                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           19000914                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           377051                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            50.393485                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     327002273500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   474.945138                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.927627                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.927627                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst     19000914                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       19000914                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     19000914                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        19000914                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     19000914                       # number of overall hits
system.cpu1.icache.overall_hits::total       19000914                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       377051                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       377051                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       377051                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        377051                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       377051                       # number of overall misses
system.cpu1.icache.overall_misses::total       377051                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5154764964                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5154764964                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5154764964                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5154764964                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5154764964                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5154764964                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     19377965                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     19377965                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     19377965                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     19377965                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     19377965                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     19377965                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.019458                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.019458                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.019458                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.019458                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.019458                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.019458                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13671.267187                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13671.267187                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       377051                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       377051                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       377051                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       377051                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       377051                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       377051                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4398685536                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4398685536                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4398685536                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4398685536                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4398685536                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4398685536                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6184500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6184500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6184500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      6184500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019458                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019458                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019458                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.019458                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019458                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.019458                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           220336                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          471.526784                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            8228665                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           220703                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.283884                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     106211109000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.526784                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920951                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.920951                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      4388185                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        4388185                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3672248                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3672248                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        73451                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        73451                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        73727                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        73727                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      8060433                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         8060433                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      8060433                       # number of overall hits
system.cpu1.dcache.overall_hits::total        8060433                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       133748                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       133748                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       112730                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       112730                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9735                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         9735                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9394                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         9394                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       246478                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        246478                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       246478                       # number of overall misses
system.cpu1.dcache.overall_misses::total       246478                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1649486235                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1649486235                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3739097468                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3739097468                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     77937249                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     77937249                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     49168975                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     49168975                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   5388583703                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   5388583703                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   5388583703                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   5388583703                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      4521933                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4521933                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3784978                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3784978                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        83186                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        83186                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        83121                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        83121                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      8306911                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      8306911                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      8306911                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      8306911                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.029578                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.029578                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029784                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.029784                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.117027                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.117027                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113016                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113016                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029671                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.029671                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.029671                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.029671                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8005.880740                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8005.880740                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5234.082925                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5234.082925                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       199438                       # number of writebacks
system.cpu1.dcache.writebacks::total           199438                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133748                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       133748                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       112730                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       112730                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9735                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9735                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9393                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total         9393                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       246478                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       246478                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       246478                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       246478                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1381071765                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1381071765                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3492633532                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3492633532                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     58449751                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     58449751                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     30384025                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30384025                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4873705297                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4873705297                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4873705297                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4873705297                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    531034000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    531034000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029578                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029578                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.029784                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.029784                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.117027                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.117027                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.113004                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.113004                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029671                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029671                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.029671                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.029671                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6004.083308                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6004.083308                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3234.751943                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3234.751943                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 618710198251                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------