path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.870823                       # Number of seconds simulated
sim_ticks                                2870822663000                       # Number of ticks simulated
final_tick                               2870822663000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 442891                       # Simulator instruction rate (inst/s)
host_op_rate                                   535691                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9664154143                       # Simulator tick rate (ticks/s)
host_mem_usage                                 616988                       # Number of bytes of host memory used
host_seconds                                   297.06                       # Real time elapsed on the host
sim_insts                                   131564747                       # Number of instructions simulated
sim_ops                                     159131669                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker          576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1180196                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1289828                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8538816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           149012                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           568660                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       388160                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12116336                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1180196                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       149012                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1329208                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8714368                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8731932                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            9                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26894                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20673                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       133419                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2483                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8906                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6065                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198466                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          136162                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               140553                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           201                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              411100                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              449289                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2974345                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               51906                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              198083                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       135209                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4220510                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         411100                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          51906                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             463006                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3035495                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6104                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3041613                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3035495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          201                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             411100                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             455393                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2974345                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              51906                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             198097                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       135209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7262123                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198466                       # Number of read requests accepted
system.physmem.writeReqs                       140553                       # Number of write requests accepted
system.physmem.readBursts                      198466                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     140553                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12692032                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9792                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8744000                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12116336                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8731932                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      153                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3897                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11821                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11810                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12062                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12027                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20473                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12098                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12277                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12432                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12179                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12459                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11810                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11367                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11535                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11583                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11073                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11307                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8516                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8730                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8955                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8735                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8248                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8655                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8964                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8852                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8742                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8980                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8644                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8478                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8438                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8004                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7925                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7759                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          91                       # Number of times write queue was full causing retry
system.physmem.totGap                    2870821632000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  188706                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 136162                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    135157                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     17197                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10634                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8782                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5915                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5070                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       63                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7533                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     9511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7906                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      416                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      236                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        84864                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      252.592006                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.738576                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     307.804055                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          42330     49.88%     49.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18020     21.23%     71.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6191      7.30%     78.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3740      4.41%     82.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2680      3.16%     85.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1634      1.93%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          923      1.09%     88.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          980      1.15%     90.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8366      9.86%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          84864                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6753                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.364283                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      566.459907                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6751     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6753                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6753                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.231749                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.531627                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.015829                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5781     85.61%     85.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             288      4.26%     89.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              56      0.83%     90.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              54      0.80%     91.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             265      3.92%     95.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              16      0.24%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              17      0.25%     95.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              13      0.19%     96.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              10      0.15%     96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               4      0.06%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.06%     96.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              11      0.16%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             146      2.16%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.07%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.10%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               6      0.09%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              12      0.18%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.06%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.06%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.04%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             6      0.09%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.16%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             4      0.06%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.01%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             4      0.06%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.04%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             4      0.06%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6753                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9353740299                       # Total ticks spent queuing
system.physmem.totMemAccLat               13072109049                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    991565000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       47166.55                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  65916.55                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.42                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.22                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.04                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.09                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165583                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     84490                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.50                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  61.83                       # Row buffer hit rate for writes
system.physmem.avgGap                      8468025.78                       # Average gap between requests
system.physmem.pageHitRate                      74.66                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  311268300                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  165439230                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 749700000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                363599100                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6175288080.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5556148530                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              353114880                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       11660360040                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        9231007680                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       675128481165                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             709697287665                       # Total energy per rank (pJ)
system.physmem_0.averagePower              247.210424                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2857712170474                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      646078467                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2625372000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2808102138000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  24039125004                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      9838978559                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  25570970970                       # Time in different power states
system.physmem_1.actEnergy                  294667800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  156619650                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 666254820                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                349583400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6182663760.000001                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5620280370                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              353139840                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       11082999060                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        9548118720                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       675230388855                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             709488226485                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.137601                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2857213980946                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      650996744                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2628804000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2808400306500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  24864927177                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      9973048810                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  24304579769                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                     7793                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7793                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1456                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6337                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         7793                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7793    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7793                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6399                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535         6392     99.89%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071            4      0.06%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607            1      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6399                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1181299500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1181299500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1181299500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         4982     77.86%     77.86% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1417     22.14%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6399                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7793                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7793                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6399                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6399                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        14192                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25156364                       # DTB read hits
system.cpu0.dtb.read_misses                      6669                       # DTB read misses
system.cpu0.dtb.write_hits                   18748845                       # DTB write hits
system.cpu0.dtb.write_misses                     1124                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3378                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1745                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25163033                       # DTB read accesses
system.cpu0.dtb.write_accesses               18749969                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         43905209                       # DTB hits
system.cpu0.dtb.misses                           7793                       # DTB misses
system.cpu0.dtb.accesses                     43913002                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     3349                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3349                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          299                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3050                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3349                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3349    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3349                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2333                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5955.666994                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          437     18.73%     18.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1604     68.75%     87.48% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          228      9.77%     97.26% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           34      1.46%     98.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959           24      1.03%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            2      0.09%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-57343            1      0.04%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::57344-65535            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-106495            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::122880-131071            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2333                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1180899500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1180899500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1180899500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2034     87.18%     87.18% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          299     12.82%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2333                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3349                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3349                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2333                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2333                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5682                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   119019454                       # ITB inst hits
system.cpu0.itb.inst_misses                      3349                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2087                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               119022803                       # ITB inst accesses
system.cpu0.itb.hits                        119019454                       # DTB hits
system.cpu0.itb.misses                           3349                       # DTB misses
system.cpu0.itb.accesses                    119022803                       # DTB accesses
system.cpu0.numPwrStateTransitions               3740                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1870                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1460468935.028877                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23678191319.145061                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1076     57.54%     57.54% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10          789     42.19%     99.73% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            1      0.05%     99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            4      0.21%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499962822056                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1870                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   139745754496                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                      5741645326                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1870                       # number of quiesce instructions executed
system.cpu0.committedInsts                  115354991                       # Number of instructions committed
system.cpu0.committedOps                    139381682                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            123361088                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9690                       # Number of float alu accesses
system.cpu0.num_func_calls                   12675511                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     15701045                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   123361088                       # number of integer instructions
system.cpu0.num_fp_insts                         9690                       # number of float instructions
system.cpu0.num_int_register_reads          227079516                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          85717450                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7430                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           504946337                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           52296035                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     45041487                       # number of memory refs
system.cpu0.num_load_insts                   25408167                       # Number of load instructions
system.cpu0.num_store_insts                  19633320                       # Number of store instructions
system.cpu0.num_idle_cycles              5462153817.006098                       # Number of idle cycles
system.cpu0.num_busy_cycles              279491508.993903                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.048678                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.951322                       # Percentage of idle cycles
system.cpu0.Branches                         29114863                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 97984598     68.45%     68.45% # Class of executed instruction
system.cpu0.op_class::IntMult                  109968      0.08%     68.53% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8149      0.01%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.53% # Class of executed instruction
system.cpu0.op_class::MemRead                25408167     17.75%     86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               19633320     13.72%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 143146475                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           692883                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          489.706194                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           43033783                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           693395                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            62.062436                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1207347000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   489.706194                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.956457                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.956457                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         88447658                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        88447658                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     23895020                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23895020                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     18016527                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18016527                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       319201                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       319201                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365698                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       365698                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362461                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       362461                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     41911547                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41911547                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     42230748                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42230748                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       396353                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       396353                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       325830                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       325830                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127542                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       127542                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21311                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21311                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19654                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19654                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       722183                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        722183                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       849725                       # number of overall misses
system.cpu0.dcache.overall_misses::total       849725                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5544958500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5544958500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6307912000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6307912000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    337776000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    337776000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    461133500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    461133500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1598000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1598000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  11852870500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  11852870500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  11852870500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  11852870500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24291373                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24291373                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18342357                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18342357                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446743                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       446743                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387009                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       387009                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382115                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       382115                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     42633730                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42633730                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     43080473                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43080473                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016317                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016317                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017764                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017764                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.285493                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.285493                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055066                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055066                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051435                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051435                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016939                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016939                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019724                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.019724                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       692883                       # number of writebacks
system.cpu0.dcache.writebacks::total           692883                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25228                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25228                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15026                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15026                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25229                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25229                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25229                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25229                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       371125                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       371125                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       325829                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       325829                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100399                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       100399                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19654                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19654                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       696954                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       696954                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       797353                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       797353                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31790                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31790                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28464                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28464                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60254                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60254                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4765649500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4765649500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5981552000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5981552000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1664266000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1664266000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     99162500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     99162500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    441526500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    441526500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1551000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1551000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10747201500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10747201500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  12411467500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  12411467500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6632422500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6632422500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6632422500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6632422500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015278                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015278                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017764                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017764                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224735                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224735                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016240                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016240                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051435                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051435                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016347                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016347                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018508                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018508                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1103683                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.436898                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          117915250                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1104195                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           106.788430                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14180312000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.436898                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998900                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998900                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        239143112                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       239143112                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    117915250                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      117915250                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    117915250                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       117915250                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    117915250                       # number of overall hits
system.cpu0.icache.overall_hits::total      117915250                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1104204                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1104204                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1104204                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1104204                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1104204                       # number of overall misses
system.cpu0.icache.overall_misses::total      1104204                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11911095000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  11911095000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11911095000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  11911095000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11911095000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  11911095000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    119019454                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    119019454                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    119019454                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    119019454                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    119019454                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    119019454                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009278                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009278                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009278                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009278                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009278                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009278                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10787.042068                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10787.042068                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10787.042068                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10787.042068                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10787.042068                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10787.042068                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1103683                       # number of writebacks
system.cpu0.icache.writebacks::total          1103683                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1104204                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1104204                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1104204                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1104204                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1104204                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1104204                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11358993000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11358993000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11358993000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11358993000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11358993000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11358993000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    863305500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    863305500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    863305500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009278                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009278                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009278                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009278                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009278                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009278                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10287.042068                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10287.042068                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10287.042068                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10287.042068                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10287.042068                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10287.042068                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1852661                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1852734                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           64                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       236762                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements          259898                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15638.452129                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1682248                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          275540                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.105277                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.347817                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.124083                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1181.932022                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.882266                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000082                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.072139                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.954495                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          340                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15293                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           30                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          149                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          154                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          821                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         6084                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6238                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1977                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.020752                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.933411                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        61320295                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       61320295                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         9508                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4316                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         13824                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       476285                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       476285                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1292383                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1292383                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       227392                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       227392                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1042059                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1042059                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       376265                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       376265                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         9508                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4316                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1042059                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       603657                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1659540                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         9508                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4316                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1042059                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       603657                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1659540                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          306                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          159                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          465                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55222                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55222                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19651                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19651                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43215                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43215                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        62145                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        62145                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101544                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       101544                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          306                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          159                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        62145                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       144759                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       207369                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          306                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          159                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        62145                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       144759                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       207369                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      8941000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3729500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     12670500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data     32046500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total     32046500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data      9591500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total      9591500                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1480500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1480500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2734835500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2734835500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3426232500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3426232500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3359763500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3359763500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      8941000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3729500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3426232500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6094599000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   9533502000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      8941000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3729500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3426232500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6094599000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   9533502000                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         9814                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4475                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        14289                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       476285                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       476285                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1292383                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1292383                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55222                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55222                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19651                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19651                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       270607                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       270607                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1104204                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1104204                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       477809                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       477809                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         9814                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4475                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1104204                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       748416                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1866909                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         9814                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4475                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1104204                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       748416                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1866909                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.031180                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.035531                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.032543                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.159697                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.159697                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.056280                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.056280                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.212520                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.212520                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.031180                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.035531                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.056280                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.193421                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.111076                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.031180                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.035531                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.056280                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.193421                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.111076                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29218.954248                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23455.974843                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27248.387097                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data   580.321249                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total   580.321249                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data   488.092209                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total   488.092209                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       493500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       493500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63284.403564                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63284.403564                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 55132.874728                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 55132.874728                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33086.775191                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33086.775191                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29218.954248                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23455.974843                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 55132.874728                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42101.693159                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 45973.612256                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29218.954248                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23455.974843                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 55132.874728                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42101.693159                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 45973.612256                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           10606                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks       227429                       # number of writebacks
system.cpu0.l2cache.writebacks::total          227429                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1561                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1561                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           33                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1594                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1594                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1594                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1594                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          306                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          159                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          465                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264666                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       264666                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55222                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55222                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19651                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19651                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41654                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41654                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        62145                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        62145                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       101511                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       101511                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          306                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          159                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        62145                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143165                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       205775                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          306                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          159                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        62145                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143165                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264666                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       470441                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31790                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40812                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28464                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28464                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60254                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69276                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      7105000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2775500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      9880500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  16752910842                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  16752910842                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    946229000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    946229000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    294413000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    294413000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1198500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1198500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2205065500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2205065500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3053362500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3053362500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2745598500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2745598500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      7105000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2775500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3053362500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4950664000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8013907000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      7105000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2775500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3053362500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4950664000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  16752910842                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  24766817842                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6377687500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7173328000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    795640500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6377687500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7173328000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.031180                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.035531                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.032543                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.153928                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.153928                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.056280                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.056280                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.212451                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.212451                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.031180                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.035531                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.056280                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.191291                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.110222                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.031180                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.035531                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.056280                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.191291                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.251989                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       399500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       399500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests      3736636                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1884055                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27898                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       214108                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       212409                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         1699                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq         61364                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1691356                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28464                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28464                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       703950                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1320281                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict        79590                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       311154                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        87625                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41858                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112323                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           88                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       289865                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       286282                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1104204                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       563680                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3258                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3330135                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2561187                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10874                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        23944                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5926140                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    141340856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     96515744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        17900                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        39256                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         237913756                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     888922                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic             18673228                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples      2798771                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.091578                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.290526                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2544165     90.90%     90.90% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            252907      9.04%     99.94% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              1699      0.06%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2798771                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3717731500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114379544                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1665328000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1206139485                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6399000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     14135489                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                     3333                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3333                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          662                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2671                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         3333                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3333    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3333                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2563                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5354.487249                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-4095            3      0.12%      0.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::4096-8191          723     28.21%     28.33% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-12287         1059     41.32%     69.64% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::12288-16383          482     18.81%     88.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-20479           76      2.97%     91.42% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::20480-24575          147      5.74%     97.15% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-28671           46      1.79%     98.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::28672-32767           15      0.59%     99.53% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-36863            4      0.16%     99.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::36864-40959            3      0.12%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-45055            2      0.08%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-53247            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::53248-57343            2      0.08%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2563                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1936423828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1936423828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1936423828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1909     74.48%     74.48% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          654     25.52%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2563                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3333                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3333                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2563                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2563                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5896                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3943012                       # DTB read hits
system.cpu1.dtb.read_misses                      2827                       # DTB read misses
system.cpu1.dtb.write_hits                    3420749                       # DTB write hits
system.cpu1.dtb.write_misses                      506                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1972                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   323                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3945839                       # DTB read accesses
system.cpu1.dtb.write_accesses                3421255                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7363761                       # DTB hits
system.cpu1.dtb.misses                           3333                       # DTB misses
system.cpu1.dtb.accesses                      7367094                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1578                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6041.889650                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          210     18.97%     18.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          573     51.76%     70.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          161     14.54%     85.28% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           52      4.70%     89.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575           52      4.70%     94.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           26      2.35%     97.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           21      1.90%     98.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            3      0.27%     99.19% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.27%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            4      0.36%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            2      0.18%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1937292828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1937292828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1937292828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    16565425                       # ITB inst hits
system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1084                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                16567171                       # ITB inst accesses
system.cpu1.itb.hits                         16565425                       # DTB hits
system.cpu1.itb.misses                           1746                       # DTB misses
system.cpu1.itb.accesses                     16567171                       # DTB accesses
system.cpu1.numPwrStateTransitions               5507                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         2754                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1032876592.840595                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   25746480816.391750                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1963     71.28%     71.28% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10          785     28.50%     99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.07%     99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.04%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11            1      0.04%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11            1      0.04%     99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.04%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 929980503556                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           2754                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON    26280526317                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                      5740713090                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2754                       # number of quiesce instructions executed
system.cpu1.committedInsts                   16209756                       # Number of instructions committed
system.cpu1.committedOps                     19749987                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             17811459                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
system.cpu1.num_func_calls                    1029227                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1814790                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    17811459                       # number of integer instructions
system.cpu1.num_fp_insts                         1792                       # number of float instructions
system.cpu1.num_int_register_reads           32322640                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          12491718                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            72198073                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            6423445                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      7597281                       # number of memory refs
system.cpu1.num_load_insts                    4054552                       # Number of load instructions
system.cpu1.num_store_insts                   3542729                       # Number of store instructions
system.cpu1.num_idle_cycles              5688160571.384175                       # Number of idle cycles
system.cpu1.num_busy_cycles              52552518.615825                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.009154                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.990846                       # Percentage of idle cycles
system.cpu1.Branches                          2922489                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 12473914     62.06%     62.06% # Class of executed instruction
system.cpu1.op_class::IntMult                   26414      0.13%     62.19% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.19% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3315      0.02%     62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.20% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.20% # Class of executed instruction
system.cpu1.op_class::MemRead                 4054552     20.17%     82.38% # Class of executed instruction
system.cpu1.op_class::MemWrite                3542729     17.62%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  20100990                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements           186832                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          467.596388                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            7094042                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           187196                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.896333                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     105561729000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   467.596388                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.913274                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.913274                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          364                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           88                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.710938                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         14946466                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        14946466                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data      3631076                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3631076                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3232073                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3232073                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48864                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        48864                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78973                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78973                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70916                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        70916                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      6863149                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         6863149                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      6912013                       # number of overall hits
system.cpu1.dcache.overall_hits::total        6912013                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       133685                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       133685                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        91868                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        91868                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30333                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30333                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17012                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17012                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23235                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23235                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       225553                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        225553                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       255886                       # number of overall misses
system.cpu1.dcache.overall_misses::total       255886                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2037941500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2037941500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2527681500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2527681500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319638500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    319638500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    545121500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    545121500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1812500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1812500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4565623000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4565623000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4565623000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4565623000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3764761                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3764761                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      3323941                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      3323941                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79197                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79197                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        95985                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        95985                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94151                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94151                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      7088702                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      7088702                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      7167899                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      7167899                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035510                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035510                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027638                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.027638                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.383007                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.383007                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.177236                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.177236                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.246784                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.246784                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031819                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031819                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035699                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035699                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       186832                       # number of writebacks
system.cpu1.dcache.writebacks::total           186832                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          254                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          254                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12014                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12014                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          254                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          254                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          254                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          254                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133431                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       133431                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91868                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        91868                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29599                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29599                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4998                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4998                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23235                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23235                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       225299                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       225299                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       254898                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       254898                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3096                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3096                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2451                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2451                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5547                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5547                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1895035500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1895035500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2435813500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2435813500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    504348000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    504348000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87440500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87440500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    521927500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    521927500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1771500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1771500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4330849000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4330849000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4835197000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4835197000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    443722000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    443722000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    443722000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    443722000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035442                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035442                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027638                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027638                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.373739                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.373739                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.052071                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.052071                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.246784                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.246784                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031783                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031783                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035561                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035561                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements           505764                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.454577                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           16059144                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           506276                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            31.720137                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      85411536000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.454577                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973544                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973544                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          388                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          121                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         33637116                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        33637116                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst     16059144                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       16059144                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     16059144                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        16059144                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     16059144                       # number of overall hits
system.cpu1.icache.overall_hits::total       16059144                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       506276                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       506276                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       506276                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        506276                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       506276                       # number of overall misses
system.cpu1.icache.overall_misses::total       506276                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4773110000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4773110000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4773110000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4773110000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4773110000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4773110000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     16565420                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     16565420                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     16565420                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     16565420                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     16565420                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     16565420                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.030562                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.030562                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.030562                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.030562                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.030562                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.030562                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9427.881235                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9427.881235                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9427.881235                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9427.881235                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9427.881235                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9427.881235                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       505764                       # number of writebacks
system.cpu1.icache.writebacks::total           505764                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       506276                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       506276                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       506276                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       506276                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       506276                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       506276                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4519972000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4519972000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4519972000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4519972000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4519972000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4519972000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     17010500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     17010500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     17010500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     17010500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.030562                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.030562                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.030562                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.030562                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.030562                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.030562                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8927.881235                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8927.881235                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8927.881235                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8927.881235                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8927.881235                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8927.881235                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued       197759                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       197759                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        59073                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements           42341                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14550.545082                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            605184                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           56718                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           10.670052                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.459040                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.079959                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   410.926752                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.862676                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000211                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.025081                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.888095                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          333                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           17                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14027                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           35                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          296                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          895                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2799                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        10333                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.020325                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001038                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.856140                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        24327160                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       24327160                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3447                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1877                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          5324                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       114448                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       114448                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       567034                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       567034                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27676                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27676                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       485156                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       485156                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        98414                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        98414                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3447                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1877                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       485156                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       126090                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         616570                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3447                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1877                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       485156                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       126090                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        616570                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          422                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          327                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          749                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29541                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29541                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23233                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23233                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34651                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34651                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        21120                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        21120                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        69614                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        69614                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          422                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          327                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        21120                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       104265                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       126134                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          422                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          327                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        21120                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       104265                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       126134                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      8582000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6568500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     15150500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     13749500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     13749500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     16999500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     16999500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1709500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1709500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1487134000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1487134000                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    835278500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    835278500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1591067500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1591067500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      8582000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6568500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    835278500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3078201500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3928630500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      8582000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6568500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    835278500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3078201500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3928630500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3869                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2204                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         6073                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       114448                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       114448                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       567034                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       567034                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29541                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29541                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23233                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23233                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62327                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62327                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       506276                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       506276                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       168028                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       168028                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3869                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2204                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       506276                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       230355                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       742704                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3869                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2204                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       506276                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       230355                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       742704                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.109072                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.148367                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.123333                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.555955                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.555955                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.041716                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.041716                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.414300                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.414300                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.109072                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.148367                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.041716                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.452627                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.169831                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.109072                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.148367                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.041716                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.452627                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.169831                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20336.492891                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20087.155963                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20227.636849                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data   465.437866                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total   465.437866                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data   731.696294                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total   731.696294                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       854750                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       854750                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42917.491559                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42917.491559                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39549.171402                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39549.171402                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22855.567846                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22855.567846                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20336.492891                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20087.155963                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39549.171402                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29522.864816                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 31146.483105                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20336.492891                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20087.155963                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39549.171402                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29522.864816                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 31146.483105                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches             833                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks        32020                       # number of writebacks
system.cpu1.l2cache.writebacks::total           32020                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           87                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           87                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           87                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           87                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           87                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           87                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          422                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          327                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          749                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        25249                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        25249                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29541                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29541                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23233                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23233                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34564                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34564                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        21120                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        21120                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        69614                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        69614                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          422                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          327                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        21120                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104178                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       126047                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          422                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          327                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        21120                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104178                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        25249                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       151296                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3096                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3273                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2451                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2451                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5547                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5724                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      6050000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4606500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     10656500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    879904235                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    879904235                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    451017000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    451017000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    347632000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    347632000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1463500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1463500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1270463000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1270463000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    708558500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    708558500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1173383500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1173383500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      6050000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4606500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    708558500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2443846500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3163061500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      6050000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4606500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    708558500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2443846500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    879904235                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   4042965735                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15683000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    418607000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    434290000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     15683000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    418607000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    434290000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.109072                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.148367                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.123333                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.554559                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.554559                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.041716                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041716                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.414300                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.414300                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.109072                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.148367                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.041716                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.452250                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.169714                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.109072                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.148367                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.041716                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.452250                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.203710                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       731750                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       731750                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests      1488382                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       751796                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       112776                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       104479                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         8297                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq         12601                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       724485                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2451                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2451                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       147576                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       578148                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        27257                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        30156                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        71390                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40982                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85466                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           88                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        69531                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66980                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       506276                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       263615                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq          248                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1518670                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       839199                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5528                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9873                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2373270                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     64771268                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     29426964                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        15476                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          94222524                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     331491                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic              4839132                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples      1057684                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.131012                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.359912                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            927412     87.68%     87.68% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            121975     11.53%     99.22% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              8297      0.78%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1057684                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1442349000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79817806                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    759591000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    376283000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      6005497                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180874                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48719500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                32000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               610000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               23000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6166000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            32044000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187769062                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.383154                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         289903742000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.383154                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898947                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898947                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36479                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36479                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36479                       # number of overall misses
system.iocache.overall_misses::total            36479                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     40888377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     40888377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4391190685                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4391190685                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4432079062                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4432079062                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4432079062                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4432079062                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36479                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36479                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36479                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36479                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 160346.576471                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 121496.725842                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121496.725842                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 121496.725842                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121496.725842                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            70                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   10                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36479                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36479                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36479                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36479                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     28138377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     28138377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2577641992                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2577641992                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2605780369                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2605780369                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2605780369                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2605780369                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110346.576471                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 110346.576471                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71158.403048                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71158.403048                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 71432.341046                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 71432.341046                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 71432.341046                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 71432.341046                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                   136024                       # number of replacements
system.l2c.tags.tagsinuse                65074.400284                       # Cycle average of tags in use
system.l2c.tags.total_refs                     524979                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   201414                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.606467                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             103030494000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    6378.541377                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.901261                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.045973                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7223.294710                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     6923.893951                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1427.225105                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3211.431328                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2259.694892                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.097329                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000060                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.110219                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.105650                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.574438                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.021778                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.049003                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.034480                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.992957                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        34321                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        31064                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          178                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4958                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        29180                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1178                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29816                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.523697                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.473999                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6089608                       # Number of tag accesses
system.l2c.tags.data_accesses                 6089608                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks       259449                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          259449                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           40103                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4906                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               45009                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2386                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          2218                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              4604                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4006                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1413                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5419                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          142                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           81                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        44259                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        52827                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        45774                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           38                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           20                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        18793                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        10825                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5311                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           178070                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker           142                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            81                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               44259                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               56833                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        45774                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            38                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            20                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               18793                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12238                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5311                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  183489                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          142                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           81                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              44259                       # number of overall hits
system.l2c.overall_hits::cpu0.data              56833                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        45774                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           38                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           20                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              18793                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12238                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5311                       # number of overall hits
system.l2c.overall_hits::total                 183489                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data           592                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           252                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total               844                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          118                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data           92                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total             210                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11217                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8015                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19232                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            9                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17886                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         9091                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       133589                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2327                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          875                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6065                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         169844                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            9                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17886                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20308                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       133589                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2327                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8890                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6065                       # number of demand (read+write) misses
system.l2c.demand_misses::total                189076                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            9                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17886                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20308                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       133589                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2327                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8890                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6065                       # number of overall misses
system.l2c.overall_misses::total               189076                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      9921500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       813500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     10735000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       614000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       361000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       975000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1635531500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    824298500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2459830000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker      1956500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       180000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1955907500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1124374000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  15941458655                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    261946000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    108772000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    762939367                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  20157534022                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker      1956500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       180000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1955907500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2759905500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  15941458655                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    261946000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    933070500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    762939367                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     22617364022                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker      1956500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       180000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1955907500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2759905500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  15941458655                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    261946000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    933070500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    762939367                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    22617364022                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       259449                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       259449                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        40695                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5158                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45853                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2504                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2310                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4814                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15223                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9428                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24651                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          151                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           83                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        62145                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        61918                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179363                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           38                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           20                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        21120                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        11700                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11376                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       347914                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          151                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           83                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           62145                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           77141                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179363                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           38                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           20                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           21120                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           21128                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11376                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              372565                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          151                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           83                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          62145                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          77141                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179363                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           38                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           20                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          21120                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          21128                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11376                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             372565                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.014547                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.048856                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.018407                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.047125                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.039827                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.043623                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.736846                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.850127                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.780171                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.059603                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.024096                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.287811                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.146823                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.110180                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.074786                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.488178                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.059603                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.024096                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.287811                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.263258                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.110180                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.420769                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.507498                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.059603                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.024096                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.287811                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.263258                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.110180                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.420769                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.507498                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16759.290541                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3228.174603                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 12719.194313                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5203.389831                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  3923.913043                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4642.857143                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145808.282072                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102844.479102                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127902.974210                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 217388.888889                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        90000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109354.103768                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123679.903201                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112568.113451                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 124310.857143                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 118682.638315                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 217388.888889                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 109354.103768                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 135902.378373                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 112568.113451                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 104957.311586                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 119620.491347                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 217388.888889                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        90000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 109354.103768                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 135902.378373                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119332.120571                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 112568.113451                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 104957.311586                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125793.795054                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 119620.491347                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               873                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    109.125000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               99972                       # number of writebacks
system.l2c.writebacks::total                    99972                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            9                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           16                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 16                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                16                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3644                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3644                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data          592                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          252                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total          844                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          118                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           92                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total          210                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11217                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8015                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19232                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            9                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17879                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         9091                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       133589                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2318                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          875                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6065                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       169828                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            9                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17879                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20308                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       133589                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2318                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8890                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6065                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           189060                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            9                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17879                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20308                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       133589                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2318                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8890                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6065                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          189060                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31790                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3093                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44082                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28464                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2451                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30915                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60254                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5544                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        74997                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13698000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5474500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     19172500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3092000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2171500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total      5263500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1523361500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    744148500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2267510000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker      1866500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       160000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1775966000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1033464000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  14605564664                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    238288500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    100021501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    702288868                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  18457620033                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1866500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       160000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1775966000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2556825500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  14605564664                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    238288500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    844170001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    702288868                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  20725130033                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1866500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       160000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1775966000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2556825500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  14605564664                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    238288500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    844170001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    702288868                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  20725130033                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5805450500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12497000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    362875500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6814067000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    633244000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5805450500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12497000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    362875500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6814067000                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.014547                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.048856                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.018407                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.047125                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.039827                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.043623                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.736846                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.850127                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.780171                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.059603                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.024096                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.287698                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.146823                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.109754                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.074786                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.488132                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.059603                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.024096                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.287698                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.263258                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.109754                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.420769                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.507455                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.059603                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.024096                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.287698                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.263258                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.744797                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.109754                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.420769                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.533140                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.507455                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 109621.972035                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        80000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 109621.972035                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        501880                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       282396                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          588                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               44082                       # Transaction distribution
system.membus.trans_dist::ReadResp             214165                       # Transaction distribution
system.membus.trans_dist::WriteReq              30915                       # Transaction distribution
system.membus.trans_dist::WriteResp             30915                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       136162                       # Transaction distribution
system.membus.trans_dist::CleanEvict            16178                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            65137                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          38197                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39788                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19211                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        170083                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13742                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       645838                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       767530                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72939                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 840469                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27484                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18531148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18721496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21038616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123440                       # Total snoops (count)
system.membus.snoopTraffic                      37632                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            424426                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.012207                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.109809                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  419245     98.78%     98.78% # Request fanout histogram
system.membus.snoop_fanout::1                    5181      1.22%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              424426                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88263500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11456000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           968117274                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1108847564                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1391627                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      1012066                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       538478                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       175231                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          28833                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        27811                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         1022                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              44085                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            510917                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30915                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30915                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       359421                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          118152                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          110125                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         42801                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         152926                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           88                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           88                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50897                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50897                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       466834                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4575                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1272193                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       313311                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1585504                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35206412                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      5504908                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               40711320                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          388372                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  15694348                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           886366                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.396986                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.491624                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 535513     60.42%     60.42% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 349831     39.47%     99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                   1022      0.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             886366                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          892357874                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360373                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         676996738                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         237913566                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------