path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.866913                       # Number of seconds simulated
sim_ticks                                2866913114000                       # Number of ticks simulated
final_tick                               2866913114000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 786450                       # Simulator instruction rate (inst/s)
host_op_rate                                   951292                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            17090693254                       # Simulator tick rate (ticks/s)
host_mem_usage                                 609256                       # Number of bytes of host memory used
host_seconds                                   167.75                       # Real time elapsed on the host
sim_insts                                   131924636                       # Number of instructions simulated
sim_ops                                     159576421                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           236004                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data           838784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      9619456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            50964                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           440736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      1362944                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12550680                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       236004                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        50964                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          286968                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6395008                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      2318336                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8731088                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            8                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             12141                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             13632                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       150304                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               951                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              6910                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        21296                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                205262                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           99922                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide         36224                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               140582                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           179                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               82320                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              292574                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3355336                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            67                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               17777                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              153732                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       475405                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4377768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          82320                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          17777                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             100097                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2230625                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6175                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          808652                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3045467                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2230625                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          179                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              82320                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             298749                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3355336                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           67                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              17777                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             153746                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       475405                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          808987                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7423234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        205263                       # Number of read requests accepted
system.physmem.writeReqs                       140582                       # Number of write requests accepted
system.physmem.readBursts                      205263                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     140582                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 13120768                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     16064                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8744768                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12550744                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8731088                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      251                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3914                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          15112                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12846                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12299                       # Per bank write bursts
system.physmem.perBankRdBursts::2               13037                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12736                       # Per bank write bursts
system.physmem.perBankRdBursts::4               21227                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12513                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12853                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12957                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12050                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12106                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12270                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11010                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11804                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12158                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11709                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11437                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8735                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8638                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9213                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8824                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8594                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8713                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8840                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8875                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8399                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8546                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8611                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8118                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8409                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8327                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8185                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7610                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
system.physmem.totGap                    2866912757000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9742                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  195493                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 136146                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    121382                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     21626                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13280                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     11136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      9518                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      8180                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      7045                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      6231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      5373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       545                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      124                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       75                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       45                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7897                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7694                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7605                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       16                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        80938                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      270.150881                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     152.124225                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     319.049708                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          39103     48.31%     48.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        16130     19.93%     68.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6485      8.01%     76.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3355      4.15%     80.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3128      3.86%     84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1920      2.37%     86.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1075      1.33%     87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1014      1.25%     89.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8728     10.78%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          80938                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6722                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.497025                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      543.729847                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6720     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6722                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6722                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.326837                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.830242                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.742760                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5511     81.98%     81.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             381      5.67%     87.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              92      1.37%     89.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             211      3.14%     92.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             209      3.11%     95.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              21      0.31%     95.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              13      0.19%     95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              14      0.21%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              24      0.36%     96.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.12%     96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.07%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               4      0.06%     96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             163      2.42%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.12%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               3      0.04%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              17      0.25%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               7      0.10%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.04%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             7      0.10%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.12%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6722                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5976562250                       # Total ticks spent queuing
system.physmem.totMemAccLat                9820537250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1025060000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29152.26                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47902.26                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.58                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.05                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.05                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         2.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.80                       # Average write queue length when enqueuing
system.physmem.readRowHits                     175010                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     85700                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   85.37                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  62.71                       # Row buffer hit rate for writes
system.physmem.avgGap                      8289588.56                       # Average gap between requests
system.physmem.pageHitRate                      76.30                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2731202883250                       # Time in different power states
system.physmem.memoryStateTime::REF       95732520000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       39977707750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 322237440                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 289653840                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 175824000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 158045250                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                861650400                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                737435400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               456399360                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               429008400                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          187252809120                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          187252809120                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           82565899920                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           81397166220                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1647721613250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1648746818250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1919356433490                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1919010936480                       # Total energy per rank (pJ)
system.physmem.averagePower::0             669.485397                       # Core power per rank (mW)
system.physmem.averagePower::1             669.364885                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    24351477                       # DTB read hits
system.cpu0.dtb.read_misses                      6408                       # DTB read misses
system.cpu0.dtb.write_hits                   18124986                       # DTB write hits
system.cpu0.dtb.write_misses                     1114                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3406                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1440                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                24357885                       # DTB read accesses
system.cpu0.dtb.write_accesses               18126100                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         42476463                       # DTB hits
system.cpu0.dtb.misses                           7522                       # DTB misses
system.cpu0.dtb.accesses                     42483985                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   115065570                       # ITB inst hits
system.cpu0.itb.inst_misses                      3350                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2152                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               115068920                       # ITB inst accesses
system.cpu0.itb.hits                        115065570                       # DTB hits
system.cpu0.itb.misses                           3350                       # DTB misses
system.cpu0.itb.accesses                    115068920                       # DTB accesses
system.cpu0.numCycles                      5733826228                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  111421445                       # Number of instructions committed
system.cpu0.committedOps                    134708041                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            119418221                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
system.cpu0.num_func_calls                   12527454                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14979151                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   119418221                       # number of integer instructions
system.cpu0.num_fp_insts                         9755                       # number of float instructions
system.cpu0.num_int_register_reads          220362058                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          83043778                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           488373650                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           49988627                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     43585923                       # number of memory refs
system.cpu0.num_load_insts                   24597873                       # Number of load instructions
system.cpu0.num_store_insts                  18988050                       # Number of store instructions
system.cpu0.num_idle_cycles              5477680330.504089                       # Number of idle cycles
system.cpu0.num_busy_cycles              256145897.495911                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.044673                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.955327                       # Percentage of idle cycles
system.cpu0.Branches                         28215151                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2272      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 94727035     68.43%     68.43% # Class of executed instruction
system.cpu0.op_class::IntMult                  104174      0.08%     68.51% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              7381      0.01%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.51% # Class of executed instruction
system.cpu0.op_class::MemRead                24597873     17.77%     86.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               18988050     13.72%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 138426785                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    2075                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           658574                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          484.573597                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           41679745                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           659086                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            63.238705                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1015660000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   484.573597                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.946433                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.946433                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         85564578                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        85564578                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     23153254                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23153254                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     17430094                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      17430094                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       323112                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       323112                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       358254                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       358254                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       353760                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       353760                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     40583348                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        40583348                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     40906460                       # number of overall hits
system.cpu0.dcache.overall_hits::total       40906460                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       360294                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       360294                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       297575                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       297575                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       106237                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       106237                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21398                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21398                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        21370                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        21370                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       657869                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        657869                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       764106                       # number of overall misses
system.cpu0.dcache.overall_misses::total       764106                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4477052020                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4477052020                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4450265428                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4450265428                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    335153501                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    335153501                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    473430117                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    473430117                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1336000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1336000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8927317448                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   8927317448                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8927317448                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   8927317448                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     23513548                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23513548                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17727669                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17727669                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       429349                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       429349                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       379652                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       379652                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       375130                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       375130                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     41241217                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     41241217                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     41670566                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     41670566                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.015323                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.015323                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016786                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.016786                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.247437                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.247437                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056362                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056362                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056967                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056967                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.015952                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.015952                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018337                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018337                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       483361                       # number of writebacks
system.cpu0.dcache.writebacks::total           483361                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7378                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total         7378                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15071                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15071                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data         7378                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total         7378                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data         7378                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total         7378                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       352916                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       352916                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       297575                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       297575                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        96924                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        96924                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6327                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6327                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        21370                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        21370                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       650491                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       650491                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       747415                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       747415                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3678269480                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3678269480                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3844865572                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3844865572                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1196073992                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1196073992                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     89532500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89532500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    429878883                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    429878883                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1262000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1262000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7523135052                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7523135052                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8719209044                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   8719209044                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5564453750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5564453750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4183862994                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4183862994                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   9748316744                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   9748316744                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015009                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015009                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016786                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.016786                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225746                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225746                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016665                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016665                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056967                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056967                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015773                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015773                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.017936                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.017936                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1061124                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.483230                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          114003925                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1061636                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           107.385135                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      12806917500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.483230                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998991                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998991                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        231192785                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       231192785                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    114003925                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      114003925                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    114003925                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       114003925                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    114003925                       # number of overall hits
system.cpu0.icache.overall_hits::total      114003925                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1061645                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1061645                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1061645                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1061645                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1061645                       # number of overall misses
system.cpu0.icache.overall_misses::total      1061645                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9000982497                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   9000982497                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   9000982497                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   9000982497                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   9000982497                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   9000982497                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    115065570                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115065570                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    115065570                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115065570                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    115065570                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115065570                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009226                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009226                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009226                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009226                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009226                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009226                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8478.335505                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8478.335505                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8478.335505                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8478.335505                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8478.335505                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8478.335505                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1061645                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1061645                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1061645                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1061645                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1061645                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1061645                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   7407816003                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   7407816003                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   7407816003                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   7407816003                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   7407816003                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   7407816003                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    719096500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    719096500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    719096500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    719096500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009226                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009226                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009226                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009226                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  6977.677098                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  6977.677098                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  6977.677098                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  6977.677098                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  6977.677098                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  6977.677098                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      9923384                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       228338                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      9249316                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          376                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           35                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       445319                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       778112                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          357554                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16100.801595                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1935390                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          373791                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            5.177733                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  6719.608952                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.125628                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.135893                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   793.879272                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1140.668616                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7443.383233                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.410132                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000191                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.048455                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.069621                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.454308                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.982715                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         7987                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         8246                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           35                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          107                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1881                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         4986                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          978                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2886                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4666                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          532                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.487488                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.503296                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        38013369                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       38013369                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7065                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3186                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1046032                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       372434                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       1428717                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       483361                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       483361                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        10097                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        10097                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         2054                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         2054                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       212764                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       212764                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7065                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3186                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1046032                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       585198                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1641481                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7065                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3186                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1046032                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       585198                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1641481                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          284                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          213                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        15613                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        83733                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        99843                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        29803                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        29803                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19308                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19308                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        44911                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        44911                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          284                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          213                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        15613                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       128644                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       144754                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          284                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          213                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        15613                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       128644                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       144754                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      6608000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4758500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    598124482                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2271341908                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   2880832890                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    522877259                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    522877259                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    377985887                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    377985887                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1224995                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1224995                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1513514605                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1513514605                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      6608000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4758500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst    598124482                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   3784856513                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   4394347495                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      6608000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4758500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst    598124482                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   3784856513                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   4394347495                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7349                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3399                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1061645                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       456167                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      1528560                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       483361                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       483361                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        39900                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        39900                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        21362                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        21362                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       257675                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       257675                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7349                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3399                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1061645                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       713842                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1786235                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7349                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3399                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1061645                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       713842                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1786235                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.038645                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.062665                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.014706                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.183558                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.065318                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.746942                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.746942                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.903848                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.903848                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.174293                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.174293                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.038645                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.062665                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.014706                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.180214                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.081039                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.038645                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.062665                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.014706                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.180214                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.081039                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23267.605634                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22340.375587                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 38309.388458                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 27126.006568                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28853.629098                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17544.450525                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17544.450525                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19576.646312                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19576.646312                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 153124.375000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 153124.375000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 33700.309612                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 33700.309612                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23267.605634                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22340.375587                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38309.388458                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29421.166265                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 30357.347604                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23267.605634                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22340.375587                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38309.388458                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29421.166265                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 30357.347604                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         6544                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              99                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    66.101010                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       205226                       # number of writebacks
system.cpu0.l2cache.writebacks::total          205226                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         2290                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         2728                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         5018                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1210                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1210                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         2290                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         3938                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         6228                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         2290                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         3938                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         6228                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          284                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          213                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        13323                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        81005                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        94825                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       445317                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       445317                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        29803                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        29803                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19308                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19308                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        43701                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        43701                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          284                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          213                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        13323                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       124706                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       138526                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          284                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          213                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        13323                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       124706                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       445317                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       583843                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4618500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3267500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    457593766                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   1665461966                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   2130941732                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17831693567                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  17831693567                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    489548028                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    489548028                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    261537598                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    261537598                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       965995                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       965995                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1080387358                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1080387358                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4618500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3267500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    457593766                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   2745849324                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   3211329090                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4618500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3267500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    457593766                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   2745849324                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17831693567                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  21043022657                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    647208500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5328411497                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5975619997                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3986952006                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3986952006                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    647208500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   9315363503                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   9962572003                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.038645                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.062665                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.012549                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.177578                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.062036                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.746942                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.746942                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.903848                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.903848                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.169597                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.169597                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.038645                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.062665                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.012549                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.174697                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.077552                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.038645                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.062665                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.012549                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.174697                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.326857                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       1734345                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1628634                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        26254                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        26254                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       483361                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       595652                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36231                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        80946                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43669                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       101586                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           74                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       279437                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       269063                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2141334                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2249028                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         9800                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        21070                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          4421232                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     67981368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80878536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13596                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        29396                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         148902896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     988296                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      3215199                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.272128                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.445055                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           2340254     72.79%     72.79% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            874945     27.21%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       3215199                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1699304627                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115610498                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1603950497                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1150471329                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6401000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     13721750                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4826061                       # DTB read hits
system.cpu1.dtb.read_misses                      2744                       # DTB read misses
system.cpu1.dtb.write_hits                    4130169                       # DTB write hits
system.cpu1.dtb.write_misses                      524                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2012                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   437                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4828805                       # DTB read accesses
system.cpu1.dtb.write_accesses                4130693                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          8956230                       # DTB hits
system.cpu1.dtb.misses                           3268                       # DTB misses
system.cpu1.dtb.accesses                      8959498                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    20883965                       # ITB inst hits
system.cpu1.itb.inst_misses                      1747                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1149                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                20885712                       # ITB inst accesses
system.cpu1.itb.hits                         20883965                       # DTB hits
system.cpu1.itb.misses                           1747                       # DTB misses
system.cpu1.itb.accesses                     20885712                       # DTB accesses
system.cpu1.numCycles                      5732918807                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   20503191                       # Number of instructions committed
system.cpu1.committedOps                     24868380                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             22184707                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
system.cpu1.num_func_calls                    1209330                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2571856                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    22184707                       # number of integer instructions
system.cpu1.num_fp_insts                         1792                       # number of float instructions
system.cpu1.num_int_register_reads           39845208                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          15444901                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            90439564                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            8859928                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      9245671                       # number of memory refs
system.cpu1.num_load_insts                    4945342                       # Number of load instructions
system.cpu1.num_store_insts                   4300329                       # Number of store instructions
system.cpu1.num_idle_cycles              5671530100.732908                       # Number of idle cycles
system.cpu1.num_busy_cycles              61388706.267092                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010708                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989292                       # Percentage of idle cycles
system.cpu1.Branches                          3891928                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   67      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 16013514     63.30%     63.30% # Class of executed instruction
system.cpu1.op_class::IntMult                   33536      0.13%     63.44% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4037      0.02%     63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     63.45% # Class of executed instruction
system.cpu1.op_class::MemRead                 4945342     19.55%     83.00% # Class of executed instruction
system.cpu1.op_class::MemWrite                4300329     17.00%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  25296825                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2733                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements           218952                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          479.963069                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            8650768                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           219309                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            39.445568                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     104113347000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   479.963069                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.937428                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.937428                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          357                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           48                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.697266                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         18157371                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        18157371                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      4461777                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        4461777                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      3918409                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       3918409                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        64134                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        64134                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        87180                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        87180                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79638                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        79638                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      8380186                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         8380186                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      8444320                       # number of overall hits
system.cpu1.dcache.overall_hits::total        8444320                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       155208                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       155208                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       103786                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       103786                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        34227                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        34227                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17933                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17933                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23205                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23205                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       258994                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        258994                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       293221                       # number of overall misses
system.cpu1.dcache.overall_misses::total       293221                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2219053526                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2219053526                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2269605832                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2269605832                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    325236501                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    325236501                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    538183221                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    538183221                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1673500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1673500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4488659358                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4488659358                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4488659358                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4488659358                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      4616985                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      4616985                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4022195                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4022195                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        98361                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        98361                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       105113                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       105113                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102843                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       102843                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      8639180                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      8639180                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      8737541                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      8737541                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.033617                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.033617                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.025803                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.025803                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.347973                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.347973                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.170607                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.170607                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.225635                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.225635                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029979                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.029979                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.033559                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.033559                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       135060                       # number of writebacks
system.cpu1.dcache.writebacks::total           135060                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          314                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          314                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data            1                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12325                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12325                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          315                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          315                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          315                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          315                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       154894                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       154894                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       103785                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       103785                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        33053                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        33053                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5608                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5608                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23205                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23205                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       258679                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       258679                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       291732                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       291732                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1899677974                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1899677974                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2055753168                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2055753168                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    496489496                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    496489496                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     84032750                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     84032750                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    490566779                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    490566779                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1599500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1599500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3955431142                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3955431142                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4451920638                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4451920638                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    961065499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    961065499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    833382997                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    833382997                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1794448496                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1794448496                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033549                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033549                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025803                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.025803                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.336038                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.336038                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.053352                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053352                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.225635                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.225635                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029943                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029943                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033388                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033388                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           565004                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.690467                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           20318443                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           565516                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            35.929033                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     115083689500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.690467                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974005                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.974005                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          110                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            5                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         42333437                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        42333437                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     20318443                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       20318443                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     20318443                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        20318443                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     20318443                       # number of overall hits
system.cpu1.icache.overall_hits::total       20318443                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       565517                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       565517                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       565517                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        565517                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       565517                       # number of overall misses
system.cpu1.icache.overall_misses::total       565517                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4683990281                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4683990281                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4683990281                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4683990281                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4683990281                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4683990281                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     20883960                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     20883960                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     20883960                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     20883960                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     20883960                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     20883960                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.027079                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.027079                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.027079                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.027079                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.027079                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.027079                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8282.669276                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8282.669276                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8282.669276                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8282.669276                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8282.669276                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8282.669276                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       565517                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       565517                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       565517                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       565517                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       565517                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       565517                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3835548219                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3835548219                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3835548219                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3835548219                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3835548219                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3835548219                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13880000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13880000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13880000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     13880000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027079                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027079                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027079                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.027079                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027079                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.027079                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6782.374746                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6782.374746                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6782.374746                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6782.374746                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6782.374746                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6782.374746                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      4611088                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr        22954                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      4468812                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          204                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           20                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       119098                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       522488                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements           85089                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15598.515375                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            830428                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs          100250                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            8.283571                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    2855976531500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  4729.771122                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.150877                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.487977                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   867.406317                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  1520.802657                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  8476.896425                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.288682                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000192                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000030                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.052942                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.092822                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.517389                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.952058                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9282                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           14                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         5865                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           69                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         1139                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         8074                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          273                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1132                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4460                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.566528                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000854                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.357971                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        16688806                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       16688806                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2996                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1704                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       559876                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       123244                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        687820                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       135060                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       135060                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1609                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1609                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          861                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          861                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        39179                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        39179                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2996                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1704                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       559876                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       162423                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         726999                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2996                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1704                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       559876                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       162423                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        726999                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          338                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          277                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst         5641                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        70311                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        76567                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29399                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        29399                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22337                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22337                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            7                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            7                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        33598                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        33598                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          338                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          277                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         5641                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       103909                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       110165                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          338                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          277                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         5641                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       103909                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       110165                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6952000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5546000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    192723218                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1546712890                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1751934108                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    537154147                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    537154147                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    436854563                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    436854563                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1562500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1562500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1072389357                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1072389357                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6952000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5546000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    192723218                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2619102247                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   2824323465                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6952000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5546000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    192723218                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2619102247                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   2824323465                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3334                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1981                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       565517                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       193555                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       764387                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       135060                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       135060                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        31008                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        31008                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23198                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23198                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            7                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        72777                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        72777                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3334                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1981                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       565517                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       266332                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       837164                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3334                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1981                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       565517                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       266332                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       837164                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.101380                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.139828                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.009975                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.363261                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.100168                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.948110                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.948110                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.962885                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.962885                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.461657                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.461657                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.101380                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.139828                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.009975                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.390148                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.131593                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.101380                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.139828                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.009975                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.390148                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.131593                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         1642                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              35                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    46.914286                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        35198                       # number of writebacks
system.cpu1.l2cache.writebacks::total           35198                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          739                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          100                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          839                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          193                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          193                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          739                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          293                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         1032                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          739                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          293                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         1032                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          338                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          277                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         4902                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        70211                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        75728                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       119097                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       119097                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29399                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29399                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22337                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22337                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            7                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        33405                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        33405                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          338                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          277                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         4902                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       103616                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       109133                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          338                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          277                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         4902                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       103616                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       119097                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       228230                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4586000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3607000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    143902025                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1053014200                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1205109225                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   3247389638                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   3247389638                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    430450689                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    430450689                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    306453691                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306453691                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1303500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1303500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    820460623                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    820460623                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4586000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3607000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    143902025                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   1873474823                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2025569848                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4586000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3607000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    143902025                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   1873474823                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   3247389638                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   5272959486                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12475500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    916023500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    928499000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    796472502                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    796472502                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12475500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1712496002                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1724971502                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.101380                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.139828                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.008668                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.362744                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.099070                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.948110                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.948110                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.962885                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.962885                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.459005                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.459005                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.101380                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.139828                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.008668                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.389048                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.130360                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.101380                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.139828                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.008668                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.389048                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.272623                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1205511                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       816520                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         4921                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         4921                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       135060                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       171236                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36231                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        86319                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        42477                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        89729                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           74                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        90979                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        78176                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1131388                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       880635                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5306                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9255                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2026584                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     36193796                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     28781627                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7924                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          64996683                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     818999                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1762052                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.415245                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.492764                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5           1030369     58.48%     58.48% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            731683     41.52%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1762052                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     658210715                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     89516500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    848574281                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    438678337                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3325000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      5921000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31019                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31019                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59407                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59440                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           33                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          844                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107964                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180918                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          446                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162847                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484103                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               503000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           326671825                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84748000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36845580                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36443                       # number of replacements
system.iocache.tags.tagsinuse               14.446794                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36459                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         277163106000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.446794                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.902925                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.902925                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328557                       # Number of tag accesses
system.iocache.tags.data_accesses              328557                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide        36224                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total        36224                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide          253                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              253                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           33                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           33                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          253                       # number of demand (read+write) misses
system.iocache.demand_misses::total               253                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          253                       # number of overall misses
system.iocache.overall_misses::total              253                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31609377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31609377                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31609377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31609377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31609377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31609377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          253                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            253                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36257                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36257                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          253                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             253                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          253                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            253                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000910                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000910                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124938.249012                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124938.249012                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124938.249012                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124938.249012                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                      36224                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ide          253                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          253                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          253                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          253                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          253                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          253                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18452377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18452377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2250014028                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2250014028                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18452377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18452377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18452377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18452377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72934.296443                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   132935                       # number of replacements
system.l2c.tags.tagsinuse                64217.518730                       # Cycle average of tags in use
system.l2c.tags.total_refs                     488817                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   197475                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.475336                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12771.193603                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     4.858844                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.037003                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     1138.507599                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     1415.888274                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.641656                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.007796                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      536.042723                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      904.271560                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  8794.277876                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.194873                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000074                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.017372                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.021605                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.589749                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000040                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.008179                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.013798                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.134190                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.979882                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        44757                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        19776                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          193                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5076                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        39488                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1542                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        18030                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.682938                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.301758                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  6143442                       # Number of tag accesses
system.l2c.tags.data_accesses                 6143442                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          146                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker          155                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              10201                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              29439                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher       168037                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           53                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           44                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst               4112                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              10373                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        47653                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 270213                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          240423                       # number of Writeback hits
system.l2c.Writeback_hits::total               240423                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            9633                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1000                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               10633                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           247                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           137                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               384                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4104                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             2566                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 6670                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           146                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker           155                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               10201                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               33543                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       168037                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            53                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            44                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                4112                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               12939                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        47653                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  276883                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          146                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker          155                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              10201                       # number of overall hits
system.l2c.overall_hits::cpu0.data              33543                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       168037                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           53                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           44                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               4112                       # number of overall hits
system.l2c.overall_hits::cpu1.data              12939                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        47653                       # number of overall hits
system.l2c.overall_hits::total                 276883                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            8                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             3124                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6991                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       150306                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              786                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             1400                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        21296                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               183916                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8554                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4191                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12745                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          893                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1293                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2186                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data           6191                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           5553                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              11744                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              3124                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             13182                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       150306                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               786                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              6953                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        21296                       # number of demand (read+write) misses
system.l2c.demand_misses::total                195660                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            8                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             3124                       # number of overall misses
system.l2c.overall_misses::cpu0.data            13182                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       150306                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              786                       # number of overall misses
system.l2c.overall_misses::cpu1.data             6953                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        21296                       # number of overall misses
system.l2c.overall_misses::total               195660                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       598250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    271876998                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    570375499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  15077807020                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       223500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     71055248                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    119227499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   2276558323                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    18387871837                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      9302615                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      9559091                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     18861706                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1287445                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2175907                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      3463352                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    491575637                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    403495431                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total    895071068                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       598250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    271876998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1061951136                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  15077807020                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       223500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     71055248                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    522722930                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   2276558323                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     19282942905                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       598250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    271876998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1061951136                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  15077807020                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       223500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     71055248                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    522722930                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   2276558323                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    19282942905                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          154                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker          156                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          13325                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          36430                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       318343                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           56                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           45                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst           4898                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          11773                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        68949                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             454129                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       240423                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           240423                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        18187                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5191                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           23378                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1140                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1430                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2570                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        10295                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         8119                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            18414                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          154                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker          156                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           13325                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           46725                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       318343                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           56                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           45                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            4898                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           19892                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        68949                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              472543                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          154                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker          156                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          13325                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          46725                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       318343                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           56                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           45                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           4898                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          19892                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        68949                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             472543                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.051948                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.006410                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.234447                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.191902                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.472151                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.053571                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.022222                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.160474                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.118916                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.308866                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.404986                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.470336                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.807359                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.545171                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.783333                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.904196                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.850584                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.601360                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.683951                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.637776                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.051948                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.006410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.234447                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.282119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.472151                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.053571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.022222                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.160474                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.349538                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.308866                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.414058                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.051948                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.006410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.234447                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.282119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.472151                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.053571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.022222                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.160474                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.349538                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.308866                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.414058                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 99979.728990                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1087.516367                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2280.861608                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1479.929855                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1441.707727                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1682.836040                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1584.333028                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76215.179496                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 98553.321604                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 98553.321604                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               370                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     46.250000                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               99922                       # number of writebacks
system.l2c.writebacks::total                    99922                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            8                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         3124                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6991                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       150305                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          786                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         1400                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        21296                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          183915                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8554                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4191                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12745                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          893                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1293                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2186                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data         6191                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         5553                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         11744                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            8                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         3124                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        13182                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       150305                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          786                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         6953                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        21296                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           195659                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            8                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         3124                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        13182                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       150305                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          786                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         6953                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        21296                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          195659                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       498750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    233055498                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    483422499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13209375020                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       187500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     61295748                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    101745999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2016216323                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  16105922337                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     86281499                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     42154679                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    128436178                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8967891                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     12981791                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     21949682                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    414199861                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    333199069                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total    747398930                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       498750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    233055498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data    897622360                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  13209375020                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       187500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     61295748                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    434945068                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   2016216323                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16853321267                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       498750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    233055498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data    897622360                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13209375020                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       187500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     61295748                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    434945068                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2016216323                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16853321267                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    476661000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   4796922003                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      9143000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    814310000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6097036003                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3540062000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    712612000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4252674000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    476661000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   8336984003                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      9143000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1526922000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10349710003                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.051948                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.006410                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.234447                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.191902                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.472148                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.053571                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.022222                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.160474                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.118916                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308866                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.404984                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.470336                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.807359                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.545171                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.783333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.904196                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.850584                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.601360                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.683951                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.637776                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.051948                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.006410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.234447                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.282119                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.472148                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.053571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.022222                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.160474                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.349538                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308866                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.414055                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.051948                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.006410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.234447                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.282119                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.472148                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.053571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.022222                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.160474                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.349538                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.308866                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.414055                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 86136.192391                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 86136.192391                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              228475                       # Transaction distribution
system.membus.trans_dist::ReadResp             228474                       # Transaction distribution
system.membus.trans_dist::WriteReq              31175                       # Transaction distribution
system.membus.trans_dist::WriteResp             31175                       # Transaction distribution
system.membus.trans_dist::Writeback             99922                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            85905                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          41202                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15112                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
system.membus.trans_dist::ReadExReq             28459                       # Transaction distribution
system.membus.trans_dist::ReadExResp            11563                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107964                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14554                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678409                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       800961                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72716                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72716                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 873677                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162847                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        29108                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18962472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     19154495                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2319296                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21473791                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           129134                       # Total snoops (count)
system.membus.snoop_fanout::samples            475892                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  475892    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              475892                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88166996                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            12082997                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1515063497                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1971064197                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38584420                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             633379                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            633359                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             31175                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            31175                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           240423                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36231                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           96357                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41586                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         137943                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           74                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           74                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            39964                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           39964                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1256968                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       399943                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1656911                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     37604672                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8289023                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               45893695                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          305031                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1043713                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.034956                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.183668                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                1007229     96.50%     96.50% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36484      3.50%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1043713                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1520313197                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1071000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2134327544                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         850356790                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------