path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.203695                       # Number of seconds simulated
sim_ticks                                1203694548000                       # Number of ticks simulated
final_tick                               1203694548000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 610810                       # Simulator instruction rate (inst/s)
host_op_rate                                   778429                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            11963163223                       # Simulator tick rate (ticks/s)
host_mem_usage                                 383784                       # Number of bytes of host memory used
host_seconds                                   100.62                       # Real time elapsed on the host
sim_insts                                    61457649                       # Number of instructions simulated
sim_ops                                      78322983                       # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               56                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           56                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              56                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           354404                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4259252                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           364636                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5307760                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62191012                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       354404                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       364636                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          719040                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4163840                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7191184                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             11756                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             66623                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5779                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             82960                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6655189                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           65060                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               821896                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43120999                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            53                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           160                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              294430                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3538482                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           160                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              302931                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4409557                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51666772                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         294430                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         302931                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             597361                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3459216                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              14123                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2500920                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5974260                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3459216                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43120999                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          160                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             294430                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3552606                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          160                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             302931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            6910477                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               57641032                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         70187                       # number of replacements
system.l2c.tagsinuse                     53228.642974                       # Cycle average of tags in use
system.l2c.total_refs                         1643789                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        135350                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         12.144728                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        40454.040636                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker       0.000402                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker       0.003088                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst          3394.914064                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data          2735.381228                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker       2.669984                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst          3118.851455                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data          3522.782116                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.617280                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst            0.051802                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data            0.041739                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker      0.000041                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst            0.047590                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data            0.053753                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.812205                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker         2523                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         1490                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             278283                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             124654                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5208                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1502                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             576279                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             223386                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1213325                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          571443                       # number of Writeback hits
system.l2c.Writeback_hits::total               571443                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data             992                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             888                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1880                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           191                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            95                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               286                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            39230                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            70245                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109475                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          2523                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          1490                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              278283                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              163884                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5208                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1502                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              576279                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              293631                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1322800                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         2523                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         1490                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             278283                       # number of overall hits
system.l2c.overall_hits::cpu0.data             163884                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5208                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1502                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             576279                       # number of overall hits
system.l2c.overall_hits::cpu1.data             293631                       # number of overall hits
system.l2c.overall_hits::total                1322800                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             5124                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             6001                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             5692                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             5607                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22431                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          4012                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4909                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8921                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          655                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          388                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1043                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          61449                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          78839                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             140288                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5124                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             67450                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5692                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             84446                       # number of demand (read+write) misses
system.l2c.demand_misses::total                162719                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5124                       # number of overall misses
system.l2c.overall_misses::cpu0.data            67450                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5692                       # number of overall misses
system.l2c.overall_misses::cpu1.data            84446                       # number of overall misses
system.l2c.overall_misses::total               162719                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        52000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       156500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    268094000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    313174000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       160000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    298650000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    293295000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1173581500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     15964999                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     31408500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     47373499                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1462500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6173000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      7635500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   3221682991                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4131389996                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7353072987                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker        52000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       156500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    268094000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   3534856991                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       160000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    298650000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   4424684996                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8526654487                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker        52000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       156500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    268094000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   3534856991                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       160000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    298650000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   4424684996                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8526654487                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         2524                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         1493                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         283407                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         130655                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5211                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1502                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         581971                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         228993                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1235756                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       571443                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           571443                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         5004                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5797                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10801                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          846                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          483                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1329                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       100679                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       149084                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           249763                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         2524                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         1493                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          283407                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          231334                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5211                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1502                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          581971                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          378077                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1485519                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         2524                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         1493                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         283407                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         231334                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5211                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1502                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         581971                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         378077                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1485519                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000396                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.002009                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.018080                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.045930                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000576                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.009781                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.024485                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.018152                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.801759                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.846817                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.825942                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.774232                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.803313                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.784801                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.610346                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.528823                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.561684                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000396                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.002009                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.018080                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.291570                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000576                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.009781                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.223357                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.109537                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000396                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.002009                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.018080                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.291570                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000576                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.009781                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.223357                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.109537                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52166.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52321.233411                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52186.968839                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 53333.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52468.376669                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52308.721241                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52319.624627                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3979.311815                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6398.146262                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  5310.335052                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2232.824427                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15909.793814                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  7320.709492                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52428.566632                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52402.871624                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52414.126561                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52166.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 52321.233411                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 52407.071772                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 53333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 52468.376669                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52396.620278                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52401.099361                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52166.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 52321.233411                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 52407.071772                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 53333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 52468.376669                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52396.620278                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52401.099361                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               65060                       # number of writebacks
system.l2c.writebacks::total                    65060                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         5123                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         6001                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         5692                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         5607                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22430                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         4012                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4909                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8921                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          655                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          388                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1043                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        61449                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        78839                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        140288                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         5123                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        67450                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5692                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        84446                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           162718                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         5123                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        67450                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5692                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        84446                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          162718                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       120000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    204994000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    240097000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       124000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    228616000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    224783500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    898774500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    160670998                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    196506499                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    357177497                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     26201999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     15527999                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     41729998                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2458624491                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3165174496                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5623798987                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       120000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    204994000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2698721491                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       124000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    228616000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   3389957996                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6522573487                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       120000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    204994000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2698721491                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       124000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    228616000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   3389957996                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6522573487                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  11136775500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3961500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155704815500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167111072500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1070730500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30910255000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  31980985500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  12207506000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3961500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 186615070500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 199092058000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000396                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.002009                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018076                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.045930                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000576                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009781                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024485                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.018151                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.801759                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.846817                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.825942                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.774232                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.803313                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.784801                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.610346                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.528823                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.561684                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000396                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.002009                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018076                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.291570                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000576                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009781                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.223357                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.109536                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000396                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.002009                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018076                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.291570                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000576                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009781                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.223357                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.109536                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40014.444661                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40009.498417                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40164.441321                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40089.798466                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40070.196166                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40047.606680                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40029.842942                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.831745                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40003.051908                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40020.615979                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40009.585810                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40010.813699                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40147.319169                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40087.526994                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40014.444661                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40010.696679                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40164.441321                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40143.499941                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40085.138012                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40014.444661                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40010.696679                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40164.441321                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40143.499941                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40085.138012                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     4800541                       # DTB read hits
system.cpu0.dtb.read_misses                      2116                       # DTB read misses
system.cpu0.dtb.write_hits                    4101169                       # DTB write hits
system.cpu0.dtb.write_misses                      405                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1539                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                    91                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      203                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 4802657                       # DTB read accesses
system.cpu0.dtb.write_accesses                4101574                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                          8901710                       # DTB hits
system.cpu0.dtb.misses                           2521                       # DTB misses
system.cpu0.dtb.accesses                      8904231                       # DTB accesses
system.cpu0.itb.inst_hits                    19425295                       # ITB inst hits
system.cpu0.itb.inst_misses                      1350                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1347                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                19426645                       # ITB inst accesses
system.cpu0.itb.hits                         19425295                       # DTB hits
system.cpu0.itb.misses                           1350                       # DTB misses
system.cpu0.itb.accesses                     19426645                       # DTB accesses
system.cpu0.numCycles                      2405961611                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   19048182                       # Number of instructions committed
system.cpu0.committedOps                     25051772                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             22684080                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4364                       # Number of float alu accesses
system.cpu0.num_func_calls                     868675                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      2620305                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    22684080                       # number of integer instructions
system.cpu0.num_fp_insts                         4364                       # number of float instructions
system.cpu0.num_int_register_reads          128950966                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          23731370                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3980                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                384                       # number of times the floating registers were written
system.cpu0.num_mem_refs                      9388163                       # number of memory refs
system.cpu0.num_load_insts                    5047859                       # Number of load instructions
system.cpu0.num_store_insts                   4340304                       # Number of store instructions
system.cpu0.num_idle_cycles              2301502404.823749                       # Number of idle cycles
system.cpu0.num_busy_cycles              104459206.176251                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.043417                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.956583                       # Percentage of idle cycles
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   34020                       # number of quiesce instructions executed
system.cpu0.icache.replacements                283184                       # number of replacements
system.cpu0.icache.tagsinuse               509.502628                       # Cycle average of tags in use
system.cpu0.icache.total_refs                19141582                       # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs                283696                       # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs                 67.472160                       # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle           75588601000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst   509.502628                       # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst     0.995122                       # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total        0.995122                       # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst     19141582                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       19141582                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     19141582                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        19141582                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     19141582                       # number of overall hits
system.cpu0.icache.overall_hits::total       19141582                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       283696                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       283696                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       283696                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        283696                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       283696                       # number of overall misses
system.cpu0.icache.overall_misses::total       283696                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   3929923500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   3929923500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   3929923500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   3929923500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   3929923500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   3929923500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     19425278                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     19425278                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     19425278                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     19425278                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     19425278                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     19425278                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014604                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014604                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014604                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014604                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014604                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014604                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.586924                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13852.586924                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.586924                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13852.586924                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.586924                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13852.586924                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       283696                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       283696                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       283696                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       283696                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       283696                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       283696                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   3362531500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   3362531500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   3362531500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   3362531500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   3362531500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   3362531500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    353907000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    353907000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    353907000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    353907000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014604                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014604                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014604                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014604                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014604                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014604                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11852.586924                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11852.586924                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11852.586924                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11852.586924                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11852.586924                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11852.586924                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.replacements                220187                       # number of replacements
system.cpu0.dcache.tagsinuse               456.524851                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                 8560144                       # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs                220557                       # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs                 38.811482                       # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle             656029000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data   456.524851                       # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data     0.891650                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total        0.891650                       # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data      4452407                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        4452407                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      3852535                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3852535                       # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117731                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       117731                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       117849                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       117849                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data      8304942                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total         8304942                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data      8304942                       # number of overall hits
system.cpu0.dcache.overall_hits::total        8304942                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       146461                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       146461                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       116958                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       116958                       # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7880                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         7880                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7697                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7697                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       263419                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        263419                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       263419                       # number of overall misses
system.cpu0.dcache.overall_misses::total       263419                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   1991314500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   1991314500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4199641500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4199641500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     70263500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     70263500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     66334500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     66334500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   6190956000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   6190956000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   6190956000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   6190956000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      4598868                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      4598868                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      3969493                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      3969493                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       125611                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       125611                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       125546                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       125546                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data      8568361                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total      8568361                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data      8568361                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total      8568361                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031847                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031847                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.029464                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.029464                       # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.062733                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.062733                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.061308                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.061308                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.030743                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.030743                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.030743                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.030743                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13596.209913                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13596.209913                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35907.261581                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 35907.261581                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  8916.687817                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  8916.687817                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8618.227881                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  8618.227881                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23502.313804                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 23502.313804                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23502.313804                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23502.313804                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       204960                       # number of writebacks
system.cpu0.dcache.writebacks::total           204960                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       146461                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       146461                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       116958                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       116958                       # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         7880                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7880                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7695                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7695                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       263419                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       263419                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       263419                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       263419                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1698392500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1698392500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   3965725500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   3965725500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     54503500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     54503500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     50946500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     50946500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   5664118000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   5664118000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   5664118000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   5664118000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  12130688000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  12130688000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1193496500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1193496500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  13324184500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  13324184500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031847                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031847                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.029464                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.029464                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062733                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.062733                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.061292                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.061292                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030743                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.030743                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030743                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.030743                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581                       # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  6916.687817                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6916.687817                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6620.727745                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6620.727745                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10590618                       # DTB read hits
system.cpu1.dtb.read_misses                      5230                       # DTB read misses
system.cpu1.dtb.write_hits                    7384755                       # DTB write hits
system.cpu1.dtb.write_misses                     1835                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2257                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   194                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      249                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10595848                       # DTB read accesses
system.cpu1.dtb.write_accesses                7386590                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         17975373                       # DTB hits
system.cpu1.dtb.misses                           7065                       # DTB misses
system.cpu1.dtb.accesses                     17982438                       # DTB accesses
system.cpu1.itb.inst_hits                    43340388                       # ITB inst hits
system.cpu1.itb.inst_misses                      3017                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1458                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                43343405                       # ITB inst accesses
system.cpu1.itb.hits                         43340388                       # DTB hits
system.cpu1.itb.misses                           3017                       # DTB misses
system.cpu1.itb.accesses                     43343405                       # DTB accesses
system.cpu1.numCycles                      2407389096                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   42409467                       # Number of instructions committed
system.cpu1.committedOps                     53271211                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             47739499                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5457                       # Number of float alu accesses
system.cpu1.num_func_calls                    1335008                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      5483103                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    47739499                       # number of integer instructions
system.cpu1.num_fp_insts                         5457                       # number of float instructions
system.cpu1.num_int_register_reads          274842107                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          51975033                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                3577                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1884                       # number of times the floating registers were written
system.cpu1.num_mem_refs                     18684058                       # number of memory refs
system.cpu1.num_load_insts                   11000639                       # Number of load instructions
system.cpu1.num_store_insts                   7683419                       # Number of store instructions
system.cpu1.num_idle_cycles              1827105047.254482                       # Number of idle cycles
system.cpu1.num_busy_cycles              580284048.745518                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.241043                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.758957                       # Percentage of idle cycles
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   56706                       # number of quiesce instructions executed
system.cpu1.icache.replacements                582628                       # number of replacements
system.cpu1.icache.tagsinuse               479.068937                       # Cycle average of tags in use
system.cpu1.icache.total_refs                42757244                       # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs                583140                       # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs                 73.322434                       # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle           92849627500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst   479.068937                       # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst     0.935682                       # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total        0.935682                       # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst     42757244                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       42757244                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     42757244                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        42757244                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     42757244                       # number of overall hits
system.cpu1.icache.overall_hits::total       42757244                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       583140                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       583140                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       583140                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        583140                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       583140                       # number of overall misses
system.cpu1.icache.overall_misses::total       583140                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7853505000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   7853505000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   7853505000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   7853505000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   7853505000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   7853505000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     43340384                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     43340384                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     43340384                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     43340384                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     43340384                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     43340384                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013455                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.013455                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013455                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.013455                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013455                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.013455                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.614981                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.614981                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.614981                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13467.614981                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.614981                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13467.614981                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       583140                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       583140                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       583140                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       583140                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       583140                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       583140                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6687225000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   6687225000                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6687225000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   6687225000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6687225000                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   6687225000                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5251000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5251000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5251000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      5251000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013455                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013455                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013455                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.013455                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013455                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.013455                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11467.614981                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11467.614981                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11467.614981                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11467.614981                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11467.614981                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11467.614981                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.replacements                401361                       # number of replacements
system.cpu1.dcache.tagsinuse               473.304740                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                15681919                       # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs                401873                       # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs                 39.022077                       # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle           84382221000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data   473.304740                       # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data     0.924423                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total        0.924423                       # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data      9101949                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        9101949                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      6323711                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       6323711                       # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       111853                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total       111853                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data       114473                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total       114473                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     15425660                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        15425660                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     15425660                       # number of overall hits
system.cpu1.dcache.overall_hits::total       15425660                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       253200                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       253200                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       178129                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       178129                       # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13100                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        13100                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10404                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10404                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       431329                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        431329                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       431329                       # number of overall misses
system.cpu1.dcache.overall_misses::total       431329                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3278248500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   3278248500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5660664500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   5660664500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    115759000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    115759000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     63020500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     63020500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8938913000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8938913000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8938913000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8938913000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9355149                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9355149                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6501840                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6501840                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       124953                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       124953                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       124877                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       124877                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     15856989                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     15856989                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     15856989                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     15856989                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.027065                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.027065                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.027397                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.027397                       # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.104839                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.104839                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.083314                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.083314                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027201                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.027201                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027201                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.027201                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8836.564885                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8836.564885                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  6057.333718                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  6057.333718                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       366483                       # number of writebacks
system.cpu1.dcache.writebacks::total           366483                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       253200                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       253200                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       178129                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       178129                       # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        13100                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        13100                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10399                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10399                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       431329                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       431329                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       431329                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       431329                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2771848500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2771848500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5304406500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5304406500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89559000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89559000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     42226500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     42226500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8076255000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   8076255000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8076255000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   8076255000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40377042500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40377042500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027065                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.027065                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027397                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027397                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.104839                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.104839                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.083274                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.083274                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027201                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.027201                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027201                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.027201                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501                       # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6836.564885                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6836.564885                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4060.630830                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4060.630830                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 567076826640                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------