path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.871120                       # Number of seconds simulated
sim_ticks                                2871119862000                       # Number of ticks simulated
final_tick                               2871119862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 654504                       # Simulator instruction rate (inst/s)
host_op_rate                                   791691                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            14285860596                       # Simulator tick rate (ticks/s)
host_mem_usage                                 653456                       # Number of bytes of host memory used
host_seconds                                   200.98                       # Real time elapsed on the host
sim_insts                                   131539806                       # Number of instructions simulated
sim_ops                                     159111212                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1136484                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1250788                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8185344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           157844                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           581136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       673536                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11986604                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1136484                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       157844                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1294328                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8637696                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8655260                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26211                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20063                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       127896                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2621                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9100                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        10524                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                196438                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          134964                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               139355                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           134                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              395833                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              435645                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2850924                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               54976                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              202407                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       234590                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4174888                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         395833                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          54976                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             450809                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3008476                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6104                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3014594                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3008476                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          134                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             395833                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             441748                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2850924                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              54976                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             202421                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       234590                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7189482                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        196438                       # Number of read requests accepted
system.physmem.writeReqs                       139355                       # Number of write requests accepted
system.physmem.readBursts                      196438                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     139355                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12561984                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10048                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8668288                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11986604                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8655260                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      157                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          49183                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11406                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11655                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11752                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11575                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20585                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12467                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12095                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12222                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12044                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12120                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11627                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11103                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11588                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11719                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10853                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11470                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8250                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8603                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8782                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8359                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8401                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9093                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8866                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8828                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8708                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8716                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8411                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8212                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8400                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8108                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7766                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7939                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          25                       # Number of times write queue was full causing retry
system.physmem.totGap                    2871119474000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9731                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  186679                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 134964                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    137894                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15510                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10092                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8580                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6925                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5397                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4544                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3804                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3324                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2816                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5041                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9048                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7440                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       68                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        87652                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      242.210195                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     137.335340                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     303.154059                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46068     52.56%     52.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17715     20.21%     72.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6262      7.14%     79.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3427      3.91%     83.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2480      2.83%     86.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1647      1.88%     88.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          825      0.94%     89.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          930      1.06%     90.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8298      9.47%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          87652                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6626                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.622698                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      552.814463                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6624     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6626                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6626                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.440990                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.878741                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.359150                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5426     81.89%     81.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             462      6.97%     88.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              72      1.09%     89.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             157      2.37%     92.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              32      0.48%     92.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             137      2.07%     94.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              41      0.62%     95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              17      0.26%     95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              26      0.39%     96.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              21      0.32%     96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.12%     96.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               4      0.06%     96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             152      2.29%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.08%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.05%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              25      0.38%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.06%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.02%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.06%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.05%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.20%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6626                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4505900396                       # Total ticks spent queuing
system.physmem.totMemAccLat                8186169146                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    981405000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       22956.38                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  41706.38                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.02                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.17                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.01                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.23                       # Average write queue length when enqueuing
system.physmem.readRowHits                     163849                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80221                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.22                       # Row buffer hit rate for writes
system.physmem.avgGap                      8550266.01                       # Average gap between requests
system.physmem.pageHitRate                      73.57                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  338884560                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  184907250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 809296800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                448299360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187527431520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            85706052435                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1647489846750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1922504718675                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.601510                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2740606830696                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95872920000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     34639965804                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  323764560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  176657250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 721687200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                429364800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187527431520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            84711391605                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1648362356250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1922252653185                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.513716                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2742063716846                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95872920000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     33181034404                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     5019                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                5019                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1041                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         3978                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         5019                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           5019    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         5019                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         4056                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9826.177645                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7625.006320                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767         4042     99.65%     99.65% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           10      0.25%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            3      0.07%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         4056                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1809726500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3032     74.75%     74.75% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1024     25.25%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         4056                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5019                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5019                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4056                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4056                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total         9075                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    23515104                       # DTB read hits
system.cpu0.dtb.read_misses                      4346                       # DTB read misses
system.cpu0.dtb.write_hits                   17278792                       # DTB write hits
system.cpu0.dtb.write_misses                      673                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    2434                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1554                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      187                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                23519450                       # DTB read accesses
system.cpu0.dtb.write_accesses               17279465                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         40793896                       # DTB hits
system.cpu0.dtb.misses                           5019                       # DTB misses
system.cpu0.dtb.accesses                     40798915                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     2305                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                2305                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          237                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2068                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         2305                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           2305    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         2305                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         1509                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9696.406116                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7256.111559                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         1436     95.16%     95.16% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767           61      4.04%     99.20% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           10      0.66%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.07%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-180223            1      0.07%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         1509                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1809154500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1272     84.29%     84.29% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          237     15.71%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         1509                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2305                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2305                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1509                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1509                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         3814                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   111711640                       # ITB inst hits
system.cpu0.itb.inst_misses                      2305                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1402                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               111713945                       # ITB inst accesses
system.cpu0.itb.hits                        111711640                       # DTB hits
system.cpu0.itb.misses                           2305                       # DTB misses
system.cpu0.itb.accesses                    111713945                       # DTB accesses
system.cpu0.numCycles                      5741309822                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  108455216                       # Number of instructions committed
system.cpu0.committedOps                    130919966                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            115934267                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  4495                       # Number of float alu accesses
system.cpu0.num_func_calls                   12371356                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14793634                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   115934267                       # number of integer instructions
system.cpu0.num_fp_insts                         4495                       # number of float instructions
system.cpu0.num_int_register_reads          213655151                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          80737315                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3581                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           474775860                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           48809609                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     41877995                       # number of memory refs
system.cpu0.num_load_insts                   23749275                       # Number of load instructions
system.cpu0.num_store_insts                  18128720                       # Number of store instructions
system.cpu0.num_idle_cycles              5480212444.901863                       # Number of idle cycles
system.cpu0.num_busy_cycles              261097377.098137                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.045477                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.954523                       # Percentage of idle cycles
system.cpu0.Branches                         27818534                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2172      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 92606456     68.80%     68.80% # Class of executed instruction
system.cpu0.op_class::IntMult                  105045      0.08%     68.88% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.88% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              7793      0.01%     68.89% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.89% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.89% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.89% # Class of executed instruction
system.cpu0.op_class::MemRead                23749275     17.64%     86.53% # Class of executed instruction
system.cpu0.op_class::MemWrite               18128720     13.47%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 134599461                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1796                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           588364                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          493.639030                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           40011095                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           588715                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            67.963437                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1836356000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.639030                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.964139                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.964139                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.685547                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         82121594                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        82121594                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     22367728                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       22367728                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     16608644                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16608644                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       300494                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       300494                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       340955                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       340955                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       337105                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       337105                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     38976372                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        38976372                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     39276866                       # number of overall hits
system.cpu0.dcache.overall_hits::total       39276866                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       340778                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       340778                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       289444                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       289444                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       113643                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       113643                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20322                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        20322                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19364                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19364                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       630222                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        630222                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       743865                       # number of overall misses
system.cpu0.dcache.overall_misses::total       743865                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4892226500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4892226500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5708519500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   5708519500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    329935000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    329935000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    454112500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    454112500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1575000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1575000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  10600746000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  10600746000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  10600746000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  10600746000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     22708506                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     22708506                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     16898088                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     16898088                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       414137                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       414137                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       361277                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       361277                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       356469                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       356469                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     39606594                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     39606594                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     40020731                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     40020731                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.015007                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.015007                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017129                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017129                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.274409                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.274409                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056250                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056250                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.054322                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.054322                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.015912                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.015912                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018587                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018587                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14356.051447                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14356.051447                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19722.362530                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19722.362530                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16235.360693                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16235.360693                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23451.378847                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23451.378847                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16820.653674                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16820.653674                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14250.900365                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14250.900365                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       443107                       # number of writebacks
system.cpu0.dcache.writebacks::total           443107                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25234                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25234                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14124                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14124                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25235                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25235                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25235                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25235                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       315544                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       315544                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       289443                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       289443                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        86831                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        86831                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6198                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6198                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19364                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19364                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       604987                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       604987                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       691818                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       691818                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31738                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31738                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28393                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28393                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60131                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60131                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4148741500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4148741500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5419061500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5419061500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1553984000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1553984000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101488000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101488000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    434796500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    434796500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1527000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1527000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9567803000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9567803000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  11121787000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  11121787000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6274722500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6274722500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5086196500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5086196500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11360919000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11360919000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.013895                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.013895                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017129                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017129                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.209667                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.209667                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017156                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017156                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.054322                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.054322                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015275                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.015275                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.017286                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.017286                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15814.890237                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15814.890237                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16076.174659                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16076.174659                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197703.777806                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 197703.777806                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements           987035                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.323984                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          110724084                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           987547                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           112.120318                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14346160000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.323984                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998680                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998680                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          400                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3          103                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::4            9                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        224410836                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       224410836                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    110724084                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      110724084                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    110724084                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       110724084                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    110724084                       # number of overall hits
system.cpu0.icache.overall_hits::total      110724084                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       987556                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       987556                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       987556                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        987556                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       987556                       # number of overall misses
system.cpu0.icache.overall_misses::total       987556                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10780435500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10780435500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10780435500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10780435500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10780435500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10780435500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    111711640                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    111711640                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    111711640                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    111711640                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    111711640                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    111711640                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.008840                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.008840                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.008840                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.008840                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.008840                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.008840                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10916.277659                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10916.277659                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10916.277659                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10916.277659                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10916.277659                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       987556                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       987556                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       987556                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       987556                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       987556                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       987556                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10286657500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10286657500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10286657500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10286657500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10286657500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10286657500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.008840                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.008840                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.008840                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.008840                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.008840                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.008840                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10416.277659                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10416.277659                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10416.277659                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10416.277659                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1606259                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1606313                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           46                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       209215                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          245604                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16082.851224                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2813687                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          260278                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           10.810314                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7782.048512                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     0.435939                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.142248                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4563.552019                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1967.112212                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1769.560295                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.474979                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000027                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000009                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.278537                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.120063                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.108005                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981619                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1320                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13335                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3           46                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         1270                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2          259                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         1410                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4        11666                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.080566                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.001160                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.813904                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        52809362                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       52809362                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         5209                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         2366                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total          7575                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       443106                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       443106                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28064                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28064                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1524                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1524                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       197142                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       197142                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst       946461                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total       946461                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       317431                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       317431                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         5209                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         2366                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst       946461                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       514573                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1468609                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         5209                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         2366                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst       946461                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       514573                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1468609                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          313                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          217                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          530                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        25366                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        25366                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        17838                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        17838                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        38871                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        38871                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        41095                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        41095                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        91142                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        91142                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          313                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          217                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        41095                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       130013                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       171638                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          313                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          217                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        41095                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       130013                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       171638                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      7197500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      4644500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total     11842000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    564638000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    564638000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    375101000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    375101000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1455000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1455000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2573340000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2573340000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3117324500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3117324500                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3123622500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3123622500                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      7197500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      4644500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3117324500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   5696962500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   8826129000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      7197500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      4644500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3117324500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   5696962500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   8826129000                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         5522                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         2583                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total         8105                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       443106                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       443106                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        53430                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        53430                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19362                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19362                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       236013                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       236013                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst       987556                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total       987556                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       408573                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       408573                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         5522                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         2583                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst       987556                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       644586                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1640247                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         5522                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         2583                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst       987556                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       644586                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1640247                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.056682                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.084011                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.065392                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.474752                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.474752                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.921289                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.921289                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.164699                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.164699                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.041613                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.041613                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.223074                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.223074                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.056682                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.084011                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.041613                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.201700                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.104642                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.056682                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.084011                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.041613                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.201700                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.104642                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22995.207668                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21403.225806                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 22343.396226                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22259.638887                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22259.638887                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21028.198229                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21028.198229                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       727500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       727500                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66202.052944                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66202.052944                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 75856.539725                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 75856.539725                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34272.042527                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34272.042527                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22995.207668                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21403.225806                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 75856.539725                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43818.406621                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 51422.930820                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22995.207668                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21403.225806                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 75856.539725                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43818.406621                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 51422.930820                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       185810                       # number of writebacks
system.cpu0.l2cache.writebacks::total          185810                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1552                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1552                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           49                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           49                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1601                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1601                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1601                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1601                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          313                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          217                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          530                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         7353                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total         7353                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       230762                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       230762                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        25366                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        25366                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        17838                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        17838                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        37319                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        37319                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        41095                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        41095                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        91093                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        91093                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          313                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          217                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        41095                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       128412                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       170037                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          313                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          217                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        41095                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       128412                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       230762                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       400799                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31738                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40760                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28393                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28393                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60131                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69153                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      5319500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3342500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      8662000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  19159534735                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  19159534735                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    795300000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    795300000                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    289164000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    289164000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1167000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1167000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2199161500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2199161500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2870754500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2870754500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2571948500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2571948500                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      5319500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3342500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2870754500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   4771110000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   7650526500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      5319500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3342500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2870754500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   4771110000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  19159534735                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  26810061235                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6020817500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7207029000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4873249000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4873249000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10894066500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12080278000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.056682                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.084011                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.065392                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.474752                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.474752                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.921289                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.921289                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.158123                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.158123                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.041613                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041613                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.222954                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.222954                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.056682                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.084011                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.041613                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.199216                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.103665                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.056682                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.084011                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.041613                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.199216                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.244353                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       583500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       583500                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      3288140                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1656034                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        25235                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       165607                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       165490                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          117                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq         54153                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1498300                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28393                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28393                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       629767                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1193646                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       275537                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        87023                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42073                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       110674                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       255600                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       251928                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq       987556                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       494836                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3354                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2960662                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2239612                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         6956                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        14519                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5221749                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     63239672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     73903156                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10332                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        22088                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         137175248                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     821565                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4077224                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.054943                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.227994                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           3853328     94.51%     94.51% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            223779      5.49%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2               117      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4077224                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2138731998                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115020156                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1490356000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1049276975                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      4373000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy      8998497                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     6206                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                6206                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         1170                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         5036                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         6206                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           6206    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         6206                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5005                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9159.943965                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  4842.286315                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-4095           42      0.84%      0.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::4096-8191         2213     44.22%     45.05% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-12287         1504     30.05%     75.10% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::12288-16383         1077     21.52%     96.62% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-20479           52      1.04%     97.66% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::20480-24575           27      0.54%     98.20% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-28671           32      0.64%     98.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::28672-32767           42      0.84%     99.68% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-36863            5      0.10%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::36864-40959            7      0.14%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-45055            3      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::57344-61439            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5005                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1704519828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1704519828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1704519828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3865     77.22%     77.22% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1140     22.78%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5005                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6206                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6206                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5005                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5005                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        11211                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     5575996                       # DTB read hits
system.cpu1.dtb.read_misses                      5233                       # DTB read misses
system.cpu1.dtb.write_hits                    4889133                       # DTB write hits
system.cpu1.dtb.write_misses                      973                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    3067                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   530                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      258                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 5581229                       # DTB read accesses
system.cpu1.dtb.write_accesses                4890106                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         10465129                       # DTB hits
system.cpu1.dtb.misses                           6206                       # DTB misses
system.cpu1.dtb.accesses                     10471335                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     2787                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                2787                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          249                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2538                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         2787                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           2787    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         2787                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1928                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9816.231267                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6428.442620                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          752     39.00%     39.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          479     24.84%     63.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          554     28.73%     92.58% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           71      3.68%     96.27% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.10%     96.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           15      0.78%     97.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           17      0.88%     98.03% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            5      0.26%     98.29% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959           26      1.35%     99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.16%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.05%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::53248-57343            2      0.10%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1928                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1705600828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1705600828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1705600828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1679     87.09%     87.09% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          249     12.91%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1928                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         2787                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         2787                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1928                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1928                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         4715                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    23850368                       # ITB inst hits
system.cpu1.itb.inst_misses                      2787                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1894                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                23853155                       # ITB inst accesses
system.cpu1.itb.hits                         23850368                       # DTB hits
system.cpu1.itb.misses                           2787                       # DTB misses
system.cpu1.itb.accesses                     23853155                       # DTB accesses
system.cpu1.numCycles                      5742239724                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   23084590                       # Number of instructions committed
system.cpu1.committedOps                     28191246                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             25227117                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  6988                       # Number of float alu accesses
system.cpu1.num_func_calls                    1341368                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2715447                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    25227117                       # number of integer instructions
system.cpu1.num_fp_insts                         6988                       # number of float instructions
system.cpu1.num_int_register_reads           45751310                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          17465196                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                5190                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1800                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           102291851                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            9890204                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     10752307                       # number of memory refs
system.cpu1.num_load_insts                    5706058                       # Number of load instructions
system.cpu1.num_store_insts                   5046249                       # Number of store instructions
system.cpu1.num_idle_cycles              5671495056.418025                       # Number of idle cycles
system.cpu1.num_busy_cycles              70744667.581975                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.012320                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.987680                       # Percentage of idle cycles
system.cpu1.Branches                          4219564                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                  167      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 17843088     62.32%     62.32% # Class of executed instruction
system.cpu1.op_class::IntMult                   31349      0.11%     62.43% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3702      0.01%     62.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.44% # Class of executed instruction
system.cpu1.op_class::MemRead                 5706058     19.93%     82.37% # Class of executed instruction
system.cpu1.op_class::MemWrite                5046249     17.63%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  28630613                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2852                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements           292035                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          469.567308                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           10109505                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           292547                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            34.556858                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     105794397000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.567308                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.917124                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.917124                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         21253597                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        21253597                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      5149175                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        5149175                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4639914                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4639914                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        67630                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        67630                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       103001                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total       103001                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        95778                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        95778                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      9789089                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         9789089                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      9856719                       # number of overall hits
system.cpu1.dcache.overall_hits::total        9856719                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       190277                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       190277                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       126690                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       126690                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        44121                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        44121                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        18673                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        18673                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23929                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23929                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       316967                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        316967                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       361088                       # number of overall misses
system.cpu1.dcache.overall_misses::total       361088                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2557291000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2557291000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3433917500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   3433917500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    339355000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    339355000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    630190000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    630190000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5470500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5470500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   5991208500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   5991208500                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   5991208500                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   5991208500                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      5339452                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      5339452                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4766604                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4766604                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       111751                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       111751                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       121674                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total       121674                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       119707                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total       119707                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     10106056                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     10106056                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     10217807                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     10217807                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035636                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035636                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.026579                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.026579                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.394815                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.394815                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.153467                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.153467                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.199896                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.199896                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031364                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031364                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035339                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035339                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       180790                       # number of writebacks
system.cpu1.dcache.writebacks::total           180790                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          404                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          404                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        13063                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        13063                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          404                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          404                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          404                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          404                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       189873                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       189873                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       126690                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       126690                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        43074                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        43074                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5610                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5610                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23929                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23929                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       316563                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       316563                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       359637                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       359637                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3143                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3143                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2520                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2520                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5663                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5663                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2352437000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2352437000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3307227500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3307227500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    648806500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    648806500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     97651500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     97651500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    606310000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    606310000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5421500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5421500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5659664500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   5659664500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6308471000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   6308471000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    420340500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    420340500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    296300500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    296300500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    716641000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    716641000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035560                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035560                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026579                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.026579                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.385446                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.385446                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.046107                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.046107                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.199896                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.199896                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031324                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031324                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035197                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035197                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           622414                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.397194                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           23227437                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           622926                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            37.287634                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     105696892000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.397194                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973432                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973432                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          220                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         48323652                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        48323652                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     23227437                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       23227437                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     23227437                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        23227437                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     23227437                       # number of overall hits
system.cpu1.icache.overall_hits::total       23227437                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       622926                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       622926                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       622926                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        622926                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       622926                       # number of overall misses
system.cpu1.icache.overall_misses::total       622926                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5716886500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   5716886500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   5716886500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   5716886500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   5716886500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   5716886500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     23850363                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     23850363                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     23850363                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     23850363                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     23850363                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     23850363                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.026118                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.026118                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.026118                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.026118                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.026118                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.026118                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9177.472926                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9177.472926                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9177.472926                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9177.472926                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9177.472926                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9177.472926                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       622926                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       622926                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       622926                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       622926                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       622926                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       622926                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5405423500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5405423500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5405423500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5405423500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5405423500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5405423500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     23975000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     23975000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     23975000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     23975000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.026118                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.026118                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.026118                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.026118                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.026118                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.026118                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8677.472926                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8677.472926                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8677.472926                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8677.472926                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8677.472926                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8677.472926                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       437692                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       437708                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           14                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        85932                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           65711                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15078.335139                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1680940                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           81927                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           20.517534                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  8770.071442                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.089565                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.088469                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3192.092107                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2103.725355                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1007.268201                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.535283                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000189                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.194830                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.128401                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.061479                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.920309                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1082                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15126                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          297                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          350                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          424                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3207                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         7762                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3991                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.066040                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.923218                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        31008240                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       31008240                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         5928                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2864                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          8792                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       180790                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       180790                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1732                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1732                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data         1100                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total         1100                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        58942                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        58942                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       603650                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       603650                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data       167802                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total       167802                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         5928                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2864                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       603650                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       226744                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         839186                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         5928                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2864                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       603650                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       226744                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        839186                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          209                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          176                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          385                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28345                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28345                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22827                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22827                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        37671                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        37671                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        19276                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        19276                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        70755                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        70755                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          209                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          176                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        19276                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       108426                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       128087                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          209                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          176                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        19276                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       108426                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       128087                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      4414000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      3881000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total      8295000                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    586663000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    586663000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    490009500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    490009500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5348000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5348000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1921205500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1921205500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    842911500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    842911500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1648156000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1648156000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      4414000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      3881000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    842911500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3569361500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   4420568000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      4414000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      3881000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    842911500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3569361500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   4420568000                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         6137                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         3040                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         9177                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       180790                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       180790                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        30077                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        30077                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23927                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23927                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        96613                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        96613                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       622926                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       622926                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       238557                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       238557                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         6137                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         3040                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       622926                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       335170                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       967273                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         6137                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         3040                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       622926                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       335170                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       967273                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.034056                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.057895                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.041953                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.942414                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.942414                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.954027                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.954027                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.389916                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.389916                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.030944                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.030944                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.296596                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.296596                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.034056                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.057895                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.030944                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.323496                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.132421                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.034056                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.057895                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.030944                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.323496                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.132421                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21119.617225                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 22051.136364                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21545.454545                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20697.230552                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20697.230552                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21466.224208                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21466.224208                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      2674000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      2674000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50999.588543                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50999.588543                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 43728.548454                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 43728.548454                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23293.844958                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23293.844958                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21119.617225                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 22051.136364                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 43728.548454                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32919.793223                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34512.229969                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21119.617225                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 22051.136364                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 43728.548454                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32919.793223                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34512.229969                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        39052                       # number of writebacks
system.cpu1.l2cache.writebacks::total           39052                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          295                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total          295                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data          295                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total          295                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data          295                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total          295                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          209                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          176                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          385                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2890                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total         2890                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        35042                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        35042                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28345                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28345                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22827                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22827                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        37376                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        37376                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        19276                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        19276                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        70755                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        70755                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          209                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          176                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        19276                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       108131                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       127792                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          209                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          176                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        19276                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       108131                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        35042                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       162834                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3143                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3320                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2520                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2520                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5663                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5840                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      3160000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      2825000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      5985000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   2001835233                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   2001835233                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    631483000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    631483000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    426660000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    426660000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5054000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      5054000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1652764500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1652764500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    727255500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    727255500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1223626000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1223626000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      3160000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2825000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    727255500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2876390500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   3609631000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      3160000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2825000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    727255500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2876390500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   2001835233                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   5611466233                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22647500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    395196500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    417844000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    277400500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    277400500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22647500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    672597000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    695244500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.034056                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057895                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.041953                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.942414                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.942414                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.954027                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.954027                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.386863                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.386863                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.030944                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.030944                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.296596                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.296596                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.034056                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057895                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.030944                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.322615                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.132116                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.034056                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057895                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.030944                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.322615                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.168343                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15545.454545                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57126.740283                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22278.461810                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22278.461810                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      2527000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      2527000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      1936586                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       978536                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        13921                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       103851                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       103732                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          119                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         19887                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       919525                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2520                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2520                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       223940                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       770866                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        41722                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        69543                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41698                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        86819                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           50                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq       103431                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp       101180                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       622926                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       309787                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           46                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1858177                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      1153867                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8365                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        17379                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3037788                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     39867972                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     35780458                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        12160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24548                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          75685138                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     354401                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      2220337                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.063895                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.244785                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           2078588     93.62%     93.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            141630      6.38%     99.99% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2               119      0.01%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       2220337                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1156529000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80617594                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    934566000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    534214495                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      5325000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     11246990                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31011                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31011                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56596                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107910                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72956                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72956                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71540                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162790                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484054                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40088000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186504974                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84712000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36780000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36460                       # number of replacements
system.iocache.tags.tagsinuse               14.383048                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36476                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         290140338000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.383048                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898940                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898940                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328302                       # Number of tag accesses
system.iocache.tags.data_accesses              328302                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          254                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              254                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          254                       # number of demand (read+write) misses
system.iocache.demand_misses::total               254                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          254                       # number of overall misses
system.iocache.overall_misses::total              254                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     33010877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     33010877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4717790097                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4717790097                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     33010877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     33010877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     33010877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     33010877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          254                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            254                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          254                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             254                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          254                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            254                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 129964.082677                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129964.082677                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129964.082677                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129964.082677                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129964.082677                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            25                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    7                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     3.571429                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          254                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          254                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          254                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          254                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          254                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          254                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20310877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20310877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2906590097                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2906590097                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     20310877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     20310877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     20310877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     20310877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79964.082677                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 79964.082677                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80239.346759                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80239.346759                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 79964.082677                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 79964.082677                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 79964.082677                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 79964.082677                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   127982                       # number of replacements
system.l2c.tags.tagsinuse                63841.400540                       # Cycle average of tags in use
system.l2c.tags.total_refs                     386797                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   192628                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.008000                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12055.995118                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.049810                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.047185                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7486.510812                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2815.662270                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37403.783442                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1406.932882                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      489.801266                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2179.617757                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.183960                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000047                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.114235                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042964                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.570736                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.021468                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.007474                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.033258                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.974142                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        31928                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32714                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           74                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4325                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        27529                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2359                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        30054                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.487183                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.499176                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5261289                       # Number of tag accesses
system.l2c.tags.data_accesses                 5261289                       # Number of data accesses
system.l2c.Writeback_hits::writebacks          224862                       # number of Writeback hits
system.l2c.Writeback_hits::total               224862                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1507                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1131                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2638                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           135                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           177                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               312                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3596                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1989                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5585                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           55                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           33                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        23888                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        41259                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        41598                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           52                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           64                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        16804                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        11932                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         9486                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           145171                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker            55                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            33                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               23888                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               44855                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        41598                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            52                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            64                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               16804                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               13921                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         9486                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  150756                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           55                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           33                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              23888                       # number of overall hits
system.l2c.overall_hits::cpu0.data              44855                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        41598                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           52                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           64                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              16804                       # number of overall hits
system.l2c.overall_hits::cpu1.data              13921                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         9486                       # number of overall hits
system.l2c.overall_hits::total                 150756                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          6940                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4223                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11163                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          425                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1268                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1693                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11072                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8126                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19198                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            6                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17201                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8649                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       128053                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2469                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1018                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher        10524                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         167922                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17201                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19721                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       128053                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2469                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9144                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        10524                       # number of demand (read+write) misses
system.l2c.demand_misses::total                187120                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17201                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19721                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       128053                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2469                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9144                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        10524                       # number of overall misses
system.l2c.overall_misses::total               187120                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     17802500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     17716000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     35518500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2579000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2637000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      5216000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1610292500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1065510000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2675802500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       810000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       272000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2259930500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1181087500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  18423338040                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    329532000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    141154500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher   1816453330                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  24152577870                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       810000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       272000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2259930500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2791380000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  18423338040                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    329532000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1206664500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   1816453330                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     26828380370                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       810000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       272000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2259930500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2791380000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  18423338040                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    329532000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1206664500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1816453330                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    26828380370                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks       224862                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           224862                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         8447                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5354                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           13801                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          560                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1445                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2005                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        14668                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10115                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24783                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           61                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           35                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        41089                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        49908                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       169651                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           52                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           64                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        19273                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        12950                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        20010                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       313093                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker           61                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           35                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           41089                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           64576                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       169651                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           52                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           64                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           19273                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           23065                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        20010                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              337876                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker           61                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           35                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          41089                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          64576                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       169651                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           52                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           64                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          19273                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          23065                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        20010                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             337876                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.821593                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.788756                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.808854                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.758929                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.877509                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.844389                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.754840                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.803361                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.774644                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.098361                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.057143                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.418628                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.173299                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.754803                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.128107                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.078610                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.525937                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.536333                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.098361                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.057143                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.418628                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.305392                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.754803                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.128107                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.396445                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.525937                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.553813                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.098361                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.057143                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.418628                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.305392                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.754803                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.128107                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.396445                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.525937                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.553813                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2565.201729                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4195.121951                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3181.805966                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6068.235294                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2079.652997                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3080.921441                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145438.267702                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131123.554024                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 139379.232212                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       135000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       136000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131383.669554                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136557.694531                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133467.800729                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138658.644401                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 143832.123665                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 131383.669554                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 141543.532275                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 133467.800729                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131962.434383                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 143375.269186                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       135000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 131383.669554                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 141543.532275                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 133467.800729                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131962.434383                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 143375.269186                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               98758                       # number of writebacks
system.l2c.writebacks::total                    98758                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           13                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           18                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3008                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3008                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         6940                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4223                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11163                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          425                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1268                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1693                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11072                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8126                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19198                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            6                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17196                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8649                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       128053                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2456                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         1018                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher        10524                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       167904                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17196                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19721                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       128053                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2456                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9144                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        10524                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           187102                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17196                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19721                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       128053                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2456                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9144                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        10524                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          187102                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31738                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3139                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44076                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28393                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2520                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30913                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60131                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5659                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        74989                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    527536000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    312350000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    839886000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     32879500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     97434000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    130313500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1499572500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    984250000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2483822500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       750000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       252000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2087455500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1094597500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  17142808040                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    303361000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    130974500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1711213330                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  22471411870                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       750000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       252000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2087455500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2594170000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  17142808040                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    303361000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1115224500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   1711213330                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  24955234370                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       750000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       252000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2087455500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2594170000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  17142808040                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    303361000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1115224500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1711213330                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  24955234370                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5449526500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19461500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    338634500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6831437500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4390566000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    234560000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4625126000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9840092500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19461500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    573194500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11456563500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.821593                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.788756                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.808854                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.758929                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.877509                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.844389                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.754840                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.803361                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.774644                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.098361                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.057143                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.418506                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.173299                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.754803                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.127432                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.078610                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.525937                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.536275                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.098361                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.057143                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.418506                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.305392                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.754803                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.127432                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.396445                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.525937                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.553759                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.098361                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.057143                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.418506                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.305392                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.754803                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.127432                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.396445                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.525937                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.553759                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       125000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 133377.699704                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 133377.699704                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               44076                       # Transaction distribution
system.membus.trans_dist::ReadResp             212234                       # Transaction distribution
system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
system.membus.trans_dist::Writeback            134964                       # Transaction distribution
system.membus.trans_dist::CleanEvict            15319                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            74839                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40260                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12961                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39815                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19093                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        168158                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107910                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13734                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664805                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       786483                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108936                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108936                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 895419                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162790                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27468                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18323720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18514046                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20832190                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123434                       # Total snoops (count)
system.membus.snoop_fanout::samples            584834                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  584834    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              584834                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88258000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11355499                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           974246641                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1126274005                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64655929                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       910965                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       460102                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       151032                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          21991                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        21404                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          587                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              44080                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            476819                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           359850                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           80476                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           77372                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40572                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         117944                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           97                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           97                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51046                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51046                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       432754                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1048506                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       332828                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1381334                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     29760096                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6517470                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               36277566                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          449108                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1186895                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.300945                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.459746                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 830292     69.95%     69.95% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 356016     30.00%     99.95% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    587      0.05%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1186895                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          806375018                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           359119                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         593704114                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         252660411                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------