path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.871782                       # Number of seconds simulated
sim_ticks                                2871782342000                       # Number of ticks simulated
final_tick                               2871782342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 937604                       # Simulator instruction rate (inst/s)
host_op_rate                                  1134083                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            20478123685                       # Simulator tick rate (ticks/s)
host_mem_usage                                 614632                       # Number of bytes of host memory used
host_seconds                                   140.24                       # Real time elapsed on the host
sim_insts                                   131486349                       # Number of instructions simulated
sim_ops                                     159039994                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1156004                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1264932                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8602496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           151508                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           548500                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       349120                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12074032                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1156004                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       151508                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1307512                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8524352                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8541916                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26516                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20284                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134414                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2522                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8591                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5455                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                197805                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          133193                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               137584                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           111                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              402539                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              440469                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2995525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52757                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              190996                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       121569                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4204369                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         402539                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52757                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             455296                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2968314                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6102                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2974430                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2968314                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             402539                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             446571                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2995525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52757                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             191010                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       121569                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7178799                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        197805                       # Number of read requests accepted
system.physmem.writeReqs                       137584                       # Number of write requests accepted
system.physmem.readBursts                      197805                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     137584                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12650304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9216                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8554240                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12074032                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8541916                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      144                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11699                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11843                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11790                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11735                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20524                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11797                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12442                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12572                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12187                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12631                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11774                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11306                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11587                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11723                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11020                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11031                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8350                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8610                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8670                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8312                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8160                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8304                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8940                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8786                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8636                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9040                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8341                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8261                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8330                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7860                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7712                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7348                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
system.physmem.totGap                    2871781902000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  188045                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 133193                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    138723                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15603                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10240                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8695                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6977                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4557                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3359                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        91                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       65                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       14                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6358                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      107                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        87582                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      242.110023                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     136.595388                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     304.444001                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46635     53.25%     53.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17297     19.75%     73.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6011      6.86%     79.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3421      3.91%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2493      2.85%     86.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1531      1.75%     88.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          857      0.98%     89.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          971      1.11%     90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8366      9.55%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          87582                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6415                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.812159                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      590.882305                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6413     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6415                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6415                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.835542                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.951972                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.109397                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5337     83.20%     83.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             463      7.22%     90.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              65      1.01%     91.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              41      0.64%     92.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              43      0.67%     92.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              15      0.23%     92.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              61      0.95%     93.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              12      0.19%     94.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             120      1.87%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              12      0.19%     96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               8      0.12%     96.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              12      0.19%     96.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              75      1.17%     97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.14%     97.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     97.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              25      0.39%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              75      1.17%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.03%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.05%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.17%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             3      0.05%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             5      0.08%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6415                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4510532456                       # Total ticks spent queuing
system.physmem.totMemAccLat                8216676206                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    988305000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       22819.54                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  41569.54                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.41                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.88                       # Average write queue length when enqueuing
system.physmem.readRowHits                     165067                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     78671                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  58.85                       # Row buffer hit rate for writes
system.physmem.avgGap                      8562540.52                       # Average gap between requests
system.physmem.pageHitRate                      73.56                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  341273520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  186210750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 814335600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                441495360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187570659120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            86023351485                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1647608604750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1922985930585                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.614762                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2740794855198                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95895020000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35089613552                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  320846400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  175065000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 727412400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                424621440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187570659120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            84787415640                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1648692759000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1922698779000                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.514771                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2742610583350                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95895020000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     33276576650                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     8793                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                8793                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1631                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7162                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         8793                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           8793    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         8793                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7275                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5725.376750                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6764     92.98%     92.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          475      6.53%     99.51% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151           28      0.38%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::49152-65535            4      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455            2      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::147456-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7275                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1809726500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5691     78.23%     78.23% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1584     21.77%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7275                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8793                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8793                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7275                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7275                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        16068                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25747110                       # DTB read hits
system.cpu0.dtb.read_misses                      7587                       # DTB read misses
system.cpu0.dtb.write_hits                   19248161                       # DTB write hits
system.cpu0.dtb.write_misses                     1206                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3752                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1822                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      321                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25754697                       # DTB read accesses
system.cpu0.dtb.write_accesses               19249367                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         44995271                       # DTB hits
system.cpu0.dtb.misses                           8793                       # DTB misses
system.cpu0.dtb.accesses                     45004064                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3674                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3674                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3354                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3674                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3674    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3674                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7309.377161                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767         2541     98.64%     98.64% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535           33      1.28%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1809154500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2256     87.58%     87.58% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          320     12.42%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2576                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2576                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2576                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6250                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   121581439                       # ITB inst hits
system.cpu0.itb.inst_misses                      3674                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2371                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               121585113                       # ITB inst accesses
system.cpu0.itb.hits                        121581439                       # DTB hits
system.cpu0.itb.misses                           3674                       # DTB misses
system.cpu0.itb.accesses                    121585113                       # DTB accesses
system.cpu0.numCycles                      5743564684                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1899                       # number of quiesce instructions executed
system.cpu0.committedInsts                  117764996                       # Number of instructions committed
system.cpu0.committedOps                    142323546                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            125936873                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                 11483                       # Number of float alu accesses
system.cpu0.num_func_calls                   12772448                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     16008688                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   125936873                       # number of integer instructions
system.cpu0.num_fp_insts                        11483                       # number of float instructions
system.cpu0.num_int_register_reads          231719006                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          87450436                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                8771                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2716                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           515468589                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           53496392                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     46152180                       # number of memory refs
system.cpu0.num_load_insts                   26006060                       # Number of load instructions
system.cpu0.num_store_insts                  20146120                       # Number of store instructions
system.cpu0.num_idle_cycles              5455990176.452100                       # Number of idle cycles
system.cpu0.num_busy_cycles              287574507.547900                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050069                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949931                       # Percentage of idle cycles
system.cpu0.Branches                         29546529                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2315      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 99842345     68.33%     68.33% # Class of executed instruction
system.cpu0.op_class::IntMult                  112141      0.08%     68.41% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8311      0.01%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::MemRead                26006060     17.80%     86.21% # Class of executed instruction
system.cpu0.op_class::MemWrite               20146120     13.79%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 146117292                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           732778                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          487.345221                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           44083181                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           733290                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            60.116981                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1836359000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   487.345221                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.951846                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.951846                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         90667478                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        90667478                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     24441740                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       24441740                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     18494582                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18494582                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       326232                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       326232                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374079                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374079                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371656                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       371656                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     42936322                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        42936322                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     43262554                       # number of overall hits
system.cpu0.dcache.overall_hits::total       43262554                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       418013                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       418013                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       337667                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       337667                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133440                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       133440                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22337                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22337                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19808                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19808                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       755680                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        755680                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       889120                       # number of overall misses
system.cpu0.dcache.overall_misses::total       889120                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5665137000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5665137000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6926542000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6926542000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    343483500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    343483500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    502731000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    502731000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1840500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1840500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  12591679000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  12591679000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  12591679000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  12591679000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24859753                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24859753                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18832249                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18832249                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       459672                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       459672                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396416                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       396416                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391464                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       391464                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     43692002                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     43692002                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     44151674                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     44151674                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016815                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016815                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017930                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017930                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.290294                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.290294                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056347                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056347                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050600                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050600                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017296                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.017296                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020138                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.020138                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16662.713053                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14161.956766                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14161.956766                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       732778                       # number of writebacks
system.cpu0.dcache.writebacks::total           732778                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25286                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25286                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            2                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15664                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15664                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25288                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25288                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25288                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25288                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       392727                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       392727                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337665                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       337665                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106338                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       106338                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6673                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6673                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19808                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19808                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       730392                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       730392                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       836730                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       836730                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31820                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31820                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60319                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60319                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4843447000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4843447000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6588824500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6588824500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1737105000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1737105000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    102846500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102846500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    482970000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    482970000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1793500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1793500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11432271500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  11432271500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13169376500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13169376500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6629050000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6629050000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5400878000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5400878000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12029928000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12029928000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015798                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015798                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017930                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017930                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231335                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.231335                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016833                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016833                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050600                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050600                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016717                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016717                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018951                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018951                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1147265                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.321425                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          120433653                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1147777                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           104.927746                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14862010000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321425                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998675                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998675                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        244310664                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       244310664                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    120433653                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      120433653                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    120433653                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       120433653                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    120433653                       # number of overall hits
system.cpu0.icache.overall_hits::total      120433653                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1147786                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1147786                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1147786                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1147786                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1147786                       # number of overall misses
system.cpu0.icache.overall_misses::total      1147786                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12247651500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  12247651500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  12247651500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  12247651500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  12247651500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  12247651500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    121581439                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    121581439                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    121581439                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    121581439                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    121581439                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    121581439                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009440                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009440                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009440                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009440                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009440                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009440                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10670.675108                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10670.675108                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10670.675108                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10670.675108                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10670.675108                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10670.675108                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1147265                       # number of writebacks
system.cpu0.icache.writebacks::total          1147265                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1147786                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1147786                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1147786                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1147786                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1147786                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1147786                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11673758500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11673758500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11673758500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11673758500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11673758500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11673758500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009440                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009440                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009440                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009440                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009440                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009440                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10170.675108                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10170.675108                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10170.675108                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10170.675108                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10170.675108                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10170.675108                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1935691                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1935756                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           57                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       245684                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          272679                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16060.422672                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3064880                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          288783                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           10.613090                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14559.127845                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     0.514376                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.125186                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1500.655266                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.888619                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000031                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.091593                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.980250                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1021                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15080                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          262                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          312                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          434                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3313                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7651                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3839                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062317                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.920410                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        62824015                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       62824015                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10929                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4820                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         15749                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       500939                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       500939                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1350193                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1350193                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       238805                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       238805                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1101574                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1101574                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       411559                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       411559                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10929                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4820                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1101574                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       650364                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1767687                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        10929                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4820                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1101574                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       650364                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1767687                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          174                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           78                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          252                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55084                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55084                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19799                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19799                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            9                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            9                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43776                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43776                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        46212                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        46212                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94179                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        94179                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          174                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker           78                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        46212                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       137955                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       184419                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          174                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker           78                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        46212                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       137955                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       184419                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4564500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2175000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total      6739500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    163061000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    163061000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     40358000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     40358000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1721497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1721497                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2789761000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2789761000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3290416000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3290416000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3238432000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3238432000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4564500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2175000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3290416000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6028193000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   9325348500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4564500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2175000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3290416000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6028193000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   9325348500                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        11103                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4898                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        16001                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       500939                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       500939                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1350193                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1350193                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55084                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55084                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19799                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19799                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            9                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            9                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       282581                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       282581                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1147786                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1147786                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       505738                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       505738                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        11103                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4898                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1147786                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       788319                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1952106                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        11103                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4898                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1147786                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       788319                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1952106                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.015671                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.015925                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.015749                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154915                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154915                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040262                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040262                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186221                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186221                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.015671                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.015925                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040262                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.174999                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.094472                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.015671                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.015925                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040262                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.174999                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.094472                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26232.758621                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27884.615385                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26744.047619                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  2960.224385                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  2960.224385                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2038.385777                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2038.385777                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 191277.444444                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 191277.444444                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63728.093019                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63728.093019                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71202.631351                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71202.631351                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34385.924675                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34385.924675                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26232.758621                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27884.615385                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71202.631351                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43696.806930                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 50566.094058                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26232.758621                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27884.615385                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71202.631351                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43696.806930                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 50566.094058                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       231522                       # number of writebacks
system.cpu0.l2cache.writebacks::total          231522                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1822                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1822                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           60                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           60                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1882                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1882                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1882                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1882                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          174                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           78                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264994                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       264994                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55084                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55084                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19799                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19799                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            9                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            9                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41954                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41954                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46212                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46212                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94119                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94119                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          174                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           78                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        46212                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136073                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       182537                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          174                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           78                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46212                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136073                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264994                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       447531                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31820                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40842                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60319                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69341                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3520500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1707000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5227500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20400229755                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20400229755                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1407285500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1407285500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    334701500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    334701500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1439497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1439497                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2354527500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2354527500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3013144000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3013144000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2666489000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2666489000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3520500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1707000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3013144000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5021016500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8039388000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3520500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1707000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3013144000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5021016500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20400229755                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  28439617755                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6374077000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7560288500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5187014000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5187014000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11561091000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12747302500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.015671                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015925                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.015749                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148467                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148467                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040262                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040262                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186102                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.186102                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.015671                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015925                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040262                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.172612                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093508                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.015671                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015925                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040262                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.172612                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229255                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20744.047619                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76983.742104                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25547.990342                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25547.990342                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16904.969948                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16904.969948                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 159944.111111                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 159944.111111                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56121.645135                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56121.645135                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65202.631351                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65202.631351                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28331.038366                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28331.038366                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65202.631351                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36899.432657                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44042.511929                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65202.631351                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36899.432657                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      3905249                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1969182                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        28911                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       320342                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       316677                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3665                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq         63843                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1765873                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       732965                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1379104                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       189043                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       312150                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        85708                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41941                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112560                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       301555                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       298207                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1147786                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       575214                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3299                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3460881                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2681738                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11926                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27058                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6181603                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    146919352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    101652834                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        19592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        44412                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         248636190                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     986669                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      2981108                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.123159                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.332339                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2617624     87.81%     87.81% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            359819     12.07%     99.88% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              3665      0.12%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2981108                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3885976496                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115188451                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1730701000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1266054481                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7028000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     15961487                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     2346                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                2346                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          473                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1873                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         2346                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           2346    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         2346                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1700                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5957.546231                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         1554     91.41%     91.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          135      7.94%     99.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            5      0.29%     99.65% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            5      0.29%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1700                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1207257828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1207257828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1207257828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1227     72.18%     72.18% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          473     27.82%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1700                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2346                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2346                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1700                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1700                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         4046                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3334779                       # DTB read hits
system.cpu1.dtb.read_misses                      1954                       # DTB read misses
system.cpu1.dtb.write_hits                    2915242                       # DTB write hits
system.cpu1.dtb.write_misses                      392                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1652                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      124                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3336733                       # DTB read accesses
system.cpu1.dtb.write_accesses                2915634                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6250021                       # DTB hits
system.cpu1.dtb.misses                           2346                       # DTB misses
system.cpu1.dtb.accesses                      6252367                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1376                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1376                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          134                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1242                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1376                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1376    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1376                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          819                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5150.797327                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          116     14.16%     14.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          577     70.45%     84.62% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383           76      9.28%     93.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            8      0.98%     94.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.24%     95.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           22      2.69%     97.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            8      0.98%     98.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     98.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.61%     99.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.24%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            2      0.24%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          819                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1208095828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1208095828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1208095828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          685     83.64%     83.64% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          134     16.36%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          819                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1376                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1376                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          819                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          819                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2195                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    13920333                       # ITB inst hits
system.cpu1.itb.inst_misses                      1376                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     883                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                13921709                       # ITB inst accesses
system.cpu1.itb.hits                         13920333                       # DTB hits
system.cpu1.itb.misses                           1376                       # DTB misses
system.cpu1.itb.accesses                     13921709                       # DTB accesses
system.cpu1.numCycles                      5742623362                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2722                       # number of quiesce instructions executed
system.cpu1.committedInsts                   13721353                       # Number of instructions committed
system.cpu1.committedOps                     16716448                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             15155011                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     915079                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1497955                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    15155011                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads           27537464                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          10698089                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            61338598                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            5194112                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      6464162                       # number of memory refs
system.cpu1.num_load_insts                    3439477                       # Number of load instructions
system.cpu1.num_store_insts                   3024685                       # Number of store instructions
system.cpu1.num_idle_cycles              5696031009.438875                       # Number of idle cycles
system.cpu1.num_busy_cycles              46592352.561125                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.008113                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.991887                       # Percentage of idle cycles
system.cpu1.Branches                          2464329                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   24      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 10543721     61.89%     61.89% # Class of executed instruction
system.cpu1.op_class::IntMult                   24250      0.14%     62.04% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3188      0.02%     62.05% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.05% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.05% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.05% # Class of executed instruction
system.cpu1.op_class::MemRead                 3439477     20.19%     82.24% # Class of executed instruction
system.cpu1.op_class::MemWrite                3024685     17.76%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  17035345                       # Class of executed instruction
system.cpu1.dcache.tags.replacements           148314                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          469.091453                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6019898                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           148666                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            40.492769                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     106291978000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   469.091453                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.916194                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.916194                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          352                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           33                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12680697                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12680697                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3066133                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3066133                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2748576                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2748576                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41842                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        41842                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69851                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        69851                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61610                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        61610                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5814709                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5814709                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      5856551                       # number of overall hits
system.cpu1.dcache.overall_hits::total        5856551                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       112800                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       112800                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        79377                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        79377                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24461                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24461                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16636                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16636                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23088                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23088                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       192177                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        192177                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       216638                       # number of overall misses
system.cpu1.dcache.overall_misses::total       216638                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1758096000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1758096000                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2710284000                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2710284000                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    320294000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    320294000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    628163500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    628163500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3848000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3848000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4468380000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4468380000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4468380000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4468380000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3178933                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3178933                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2827953                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2827953                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66303                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        66303                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86487                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        86487                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84698                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        84698                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      6006886                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      6006886                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6073189                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6073189                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035484                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035484                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028069                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.028069                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.368927                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.368927                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.192353                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.192353                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.272592                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.272592                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031993                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031993                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035671                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035671                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       148314                       # number of writebacks
system.cpu1.dcache.writebacks::total           148314                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          199                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          199                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11732                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11732                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          199                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          199                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          199                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          199                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       112601                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       112601                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79377                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        79377                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        24003                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        24003                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4904                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4904                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23088                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23088                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       191978                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       191978                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       215981                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       215981                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3083                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3083                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2425                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2425                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5508                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5508                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1635811500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1635811500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2630907000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2630907000                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    431572500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    431572500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89921000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89921000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    605110500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    605110500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3813000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3813000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4266718500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4266718500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4698291000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4698291000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    439541500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    439541500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    303268000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    303268000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    742809500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    742809500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035421                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035421                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028069                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028069                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.362020                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.362020                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056702                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056702                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.272592                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.272592                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031960                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031960                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035563                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035563                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           463432                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.310833                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           13456384                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           463944                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            29.004328                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     106360036500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.310833                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973263                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973263                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         28304600                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        28304600                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     13456384                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       13456384                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     13456384                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        13456384                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     13456384                       # number of overall hits
system.cpu1.icache.overall_hits::total       13456384                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       463944                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       463944                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       463944                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        463944                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       463944                       # number of overall misses
system.cpu1.icache.overall_misses::total       463944                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4214272500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4214272500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4214272500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4214272500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4214272500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4214272500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     13920328                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     13920328                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     13920328                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     13920328                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     13920328                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     13920328                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033329                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.033329                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033329                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.033329                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033329                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.033329                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9083.580130                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9083.580130                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9083.580130                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9083.580130                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9083.580130                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9083.580130                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       463432                       # number of writebacks
system.cpu1.icache.writebacks::total           463432                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       463944                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       463944                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       463944                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       463944                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       463944                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       463944                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3982300500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3982300500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3982300500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3982300500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3982300500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3982300500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     23546500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     23546500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033329                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.033329                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033329                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.033329                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8583.580130                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8583.580130                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8583.580130                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8583.580130                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8583.580130                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8583.580130                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       118303                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       118321                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit           16                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        50079                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           31154                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14935.857031                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1041086                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           46286                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           22.492460                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14446.292104                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.202140                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.081939                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   484.280848                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.881732                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000195                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.029558                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.911612                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          981                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14113                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           47                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          926                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1668                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12049                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059875                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002319                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.861389                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        21151055                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       21151055                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2455                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1474                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          3929                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        92001                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        92001                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       509646                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       509646                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18183                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        18183                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       455037                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       455037                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        77628                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        77628                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2455                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1474                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       455037                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data        95811                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         554777                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2455                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1474                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       455037                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data        95811                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        554777                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          348                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          300                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          648                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28973                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28973                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23087                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23087                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32221                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32221                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst         8907                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total         8907                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        63880                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        63880                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          348                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          300                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         8907                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        96101                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       105656                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          348                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          300                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         8907                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        96101                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       105656                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      7097500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5968000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     13065500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     64302000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     64302000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     54899500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     54899500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3760000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3760000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1640601500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1640601500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    530446000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    530446000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1436061500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1436061500                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      7097500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5968000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    530446000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3076663000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3620174500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      7097500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5968000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    530446000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3076663000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3620174500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         2803                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1774                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         4577                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        92001                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        92001                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       509646                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       509646                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28973                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        28973                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23087                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23087                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50404                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50404                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       463944                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       463944                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       141508                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       141508                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         2803                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1774                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       463944                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       191912                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       660433                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         2803                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1774                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       463944                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       191912                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       660433                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.124153                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.169109                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.141577                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.639255                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.639255                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.019198                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.019198                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.451423                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.451423                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.124153                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.169109                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.019198                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.500756                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.159980                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.124153                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.169109                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.019198                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.500756                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.159980                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20395.114943                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19893.333333                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20162.808642                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2219.376661                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2219.376661                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2377.939966                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2377.939966                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3760000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3760000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50917.150306                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50917.150306                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59553.834063                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59553.834063                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22480.612085                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22480.612085                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20395.114943                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19893.333333                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59553.834063                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32014.890584                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34263.785303                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20395.114943                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19893.333333                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59553.834063                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32014.890584                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34263.785303                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        25848                       # number of writebacks
system.cpu1.l2cache.writebacks::total           25848                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           72                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           72                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           72                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           72                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           72                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           72                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          348                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          300                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          648                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        21105                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        21105                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28973                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28973                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23087                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23087                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32149                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32149                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst         8907                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8907                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63880                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        63880                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          348                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          300                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         8907                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        96029                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       105584                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          348                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          300                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         8907                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        96029                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        21105                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       126689                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3083                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3260                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2425                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2425                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5508                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5685                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      5009500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4168000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9177500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    934365172                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    934365172                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    576596500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    576596500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    431875500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    431875500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3550000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3550000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1440609000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1440609000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    477004000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    477004000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1052781500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1052781500                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      5009500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4168000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    477004000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2493390500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2979572000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      5009500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4168000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    477004000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2493390500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    934365172                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3913937172                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    414529000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    436748000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    285072000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    285072000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    699601000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    721820000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.124153                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.169109                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.141577                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637826                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637826                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019198                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.019198                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.451423                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451423                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.124153                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.169109                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.019198                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.500380                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159871                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.124153                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.169109                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.019198                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.500380                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191827                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      3550000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      3550000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      1324645                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       668824                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10099                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       169409                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       166956                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2453                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         10097                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       652790                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2425                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2425                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       119017                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       519745                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        86537                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        25449                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        70337                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40896                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        84740                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           48                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57665                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        55147                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       463944                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       215084                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           32                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1391674                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       722021                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4392                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7022                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2125109                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     59352772                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24485096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11212                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          83856176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     356096                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples       999531                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.187033                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.396182                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            815039     81.54%     81.54% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            182039     18.21%     99.75% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              2453      0.25%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total        999531                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1279051999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79434008                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    696093000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    318231000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      2618000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      4219000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31021                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31021                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48746500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                32500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                93500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               609000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               23500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6162500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            32045500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187117449                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36461                       # number of replacements
system.iocache.tags.tagsinuse               14.380044                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36477                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         290746348000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.380044                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898753                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898753                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          255                       # number of overall misses
system.iocache.overall_misses::total              255                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32874877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32874877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4582462572                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4582462572                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32874877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32874877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32874877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32874877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128921.086275                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128921.086275                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128921.086275                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128921.086275                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128921.086275                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs            19                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    3                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.333333                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20124877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20124877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2769551646                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2769551646                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     20124877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     20124877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     20124877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     20124877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 78921.086275                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 78921.086275                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   123661                       # number of replacements
system.l2c.tags.tagsinuse                63058.402721                       # Cycle average of tags in use
system.l2c.tags.total_refs                     421257                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   187718                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.244095                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13491.325958                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.985555                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.052859                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7361.006580                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2805.566875                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35728.682862                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954518                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1443.499308                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      410.819619                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1814.508588                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.205861                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000030                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.112320                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042810                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.545176                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.022026                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.006269                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.027687                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.962195                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32044                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32009                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          306                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5120                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        26618                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          402                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2325                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29253                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.488953                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.488419                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5830329                       # Number of tag accesses
system.l2c.tags.data_accesses                 5830329                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       257370                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          257370                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32263                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1924                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               34187                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2044                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           899                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              2943                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4115                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1385                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5500                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           95                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           72                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        28709                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        46783                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        47559                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           20                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           13                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst         6543                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         5065                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3419                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           138278                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker            95                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            72                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               28709                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               50898                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        47559                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            20                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            13                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                6543                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                6450                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3419                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  143778                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           95                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           72                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              28709                       # number of overall hits
system.l2c.overall_hits::cpu0.data              50898                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        47559                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           20                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           13                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               6543                       # number of overall hits
system.l2c.overall_hits::cpu1.data               6450                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3419                       # number of overall hits
system.l2c.overall_hits::total                 143778                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9386                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2249                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11635                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          587                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1308                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1895                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11114                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7777                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              18891                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            5                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17503                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8876                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134571                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2364                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          804                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5455                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         169581                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17503                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             19990                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       134571                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2364                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8581                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5455                       # number of demand (read+write) misses
system.l2c.demand_misses::total                188472                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17503                       # number of overall misses
system.l2c.overall_misses::cpu0.data            19990                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       134571                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2364                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8581                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5455                       # number of overall misses
system.l2c.overall_misses::total               188472                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     30248000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5203000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     35451000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3836500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2726000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      6562500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1620087000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1017624500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2637711500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       677000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       362000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2302051000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1209307000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19566804778                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       146500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    313582000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    113115000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    857081845                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  24363127123                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       677000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       362000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2302051000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2829394000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19566804778                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       146500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    313582000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1130739500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    857081845                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     27000838623                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       677000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       362000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2302051000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2829394000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19566804778                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       146500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    313582000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1130739500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    857081845                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    27000838623                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       257370                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       257370                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        41649                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4173                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45822                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2631                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2207                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4838                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15229                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9162                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24391                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          100                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           74                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        46212                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        55659                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       182130                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           21                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           13                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst         8907                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         5869                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8874                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       307859                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          100                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           74                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           46212                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           70888                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       182130                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           21                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           13                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            8907                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           15031                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8874                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              332250                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          100                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           74                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          46212                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          70888                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       182130                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           21                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           13                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           8907                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          15031                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8874                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             332250                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.225360                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.538941                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.253917                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.223109                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.592660                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.391691                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.729792                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.848832                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.774507                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.050000                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.027027                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.378754                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159471                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.265409                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.136991                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.550840                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.050000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.027027                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.378754                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.281994                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.265409                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.570887                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.567260                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.050000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.027027                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.378754                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.281994                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.047619                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.265409                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.570887                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.567260                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3222.672065                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2313.472655                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3046.927374                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6535.775128                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2084.097859                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3463.060686                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145769.929818                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130850.520766                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 139627.944524                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       135400                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       181000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131523.224590                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136244.592159                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       146500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132648.900169                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140690.298507                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 143666.608423                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135400                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       181000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 131523.224590                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 141540.470235                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       146500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132648.900169                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131772.462417                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 143261.803467                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       135400                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       181000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 131523.224590                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 141540.470235                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       146500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132648.900169                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131772.462417                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 143261.803467                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96987                       # number of writebacks
system.l2c.writebacks::total                    96987                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         2809                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         2809                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9386                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2249                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11635                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          587                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1308                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1895                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11114                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7777                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         18891                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            5                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17501                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8876                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134571                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2357                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          804                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5455                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       169572                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17501                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        19990                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134571                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2357                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8581                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5455                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           188463                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17501                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        19990                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134571                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2357                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8581                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5455                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          188463                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31820                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3080                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44099                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2425                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30924                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60319                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5505                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        75023                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    682643500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    162589000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    845232500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     43754500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     96726500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    140481000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1508944512                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    939851506                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2448796018                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       627000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       342000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2126838009                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1120542510                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  18221057894                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       136500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    289400510                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    105072505                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    802516896                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  22666533824                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       627000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       342000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2126838009                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2629487022                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  18221057894                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       136500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    289400510                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1044924011                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    802516896                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  25115329842                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       627000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       342000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2126838009                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2629487022                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18221057894                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       136500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    289400510                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1044924011                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    802516896                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  25115329842                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5801306000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    359044000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7203197500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4702516500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    243805501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4946322001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10503822500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    602849501                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12149519501                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.225360                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.538941                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.253917                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.223109                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.592660                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.391691                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.729792                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.848832                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.774507                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.050000                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027027                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.378711                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159471                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.047619                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.264623                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.136991                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.550811                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.050000                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027027                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.378711                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.281994                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.047619                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.264623                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.570887                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.567233                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.050000                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027027                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.378711                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.281994                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738873                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.047619                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.264623                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.570887                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614717                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.567233                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       125400                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       171000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       136500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125400                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       171000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       136500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 133263.982012                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125400                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       171000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       136500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 133263.982012                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               44099                       # Transaction distribution
system.membus.trans_dist::ReadResp             213926                       # Transaction distribution
system.membus.trans_dist::WriteReq              30924                       # Transaction distribution
system.membus.trans_dist::WriteResp             30924                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       133193                       # Transaction distribution
system.membus.trans_dist::CleanEvict            14771                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            73670                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          39871                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39385                       # Transaction distribution
system.membus.trans_dist::ReadExResp            18791                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        169827                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13776                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       650336                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       772080                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72955                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72955                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 845035                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27552                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18297804                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18488238                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20806382                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           121083                       # Total snoops (count)
system.membus.snoop_fanout::samples            581994                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  581994    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              581994                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88286500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11391000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           968108262                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1106274782                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1388877                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       960339                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       518534                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       139328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20435                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        19626                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          809                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              44102                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            468032                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30924                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30924                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       390589                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          105128                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          107757                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         42814                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         150571                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           82                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           82                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50426                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50426                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       423945                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1240075                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       253445                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1493520                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34222158                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3776032                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               37998190                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          438746                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           896439                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.337268                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.474682                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 594908     66.36%     66.36% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 300722     33.55%     99.91% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    809      0.09%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             896439                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          863728414                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360123                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         645946273                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         202615858                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------