path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.868721                       # Number of seconds simulated
sim_ticks                                2868720569000                       # Number of ticks simulated
final_tick                               2868720569000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 718623                       # Simulator instruction rate (inst/s)
host_op_rate                                   869205                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            15661016649                       # Simulator tick rate (ticks/s)
host_mem_usage                                 645712                       # Number of bytes of host memory used
host_seconds                                   183.18                       # Real time elapsed on the host
sim_insts                                   131634295                       # Number of instructions simulated
sim_ops                                     159217322                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1149540                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1292388                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8590592                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           151892                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           585104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       399936                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12171052                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1149540                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       151892                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1301432                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8736704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8754268                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26415                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20713                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134228                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2528                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9162                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         6249                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                199320                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          136511                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               140902                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              400715                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              450510                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2994573                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52948                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              203960                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       139413                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4242676                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         400715                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52948                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             453663                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3045505                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6109                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3051628                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3045505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             400715                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             456619                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2994573                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52948                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             203974                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       139413                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7294304                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        199320                       # Number of read requests accepted
system.physmem.writeReqs                       140902                       # Number of write requests accepted
system.physmem.readBursts                      199320                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     140902                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12746944                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8766656                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12171052                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8754268                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          49030                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12070                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11831                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12274                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12388                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20676                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12594                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12033                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12197                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12580                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12376                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11749                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11049                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11595                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11646                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10943                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11170                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8793                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8761                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9161                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8988                       # Per bank write bursts
system.physmem.perBankWrBursts::4                8395                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9123                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8851                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8630                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9078                       # Per bank write bursts
system.physmem.perBankWrBursts::9                8912                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8485                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8089                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8403                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8019                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7666                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7625                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          43                       # Number of times write queue was full causing retry
system.physmem.totGap                    2868720108500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9731                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  189561                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 136511                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    138723                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15961                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10493                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3946                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3444                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4887                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6725                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      214                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      131                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88863                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      242.097791                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     137.224347                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     303.120448                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46751     52.61%     52.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        18086     20.35%     72.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6032      6.79%     79.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3695      4.16%     83.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2426      2.73%     86.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1553      1.75%     88.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1048      1.18%     89.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          926      1.04%     90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8346      9.39%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88863                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6835                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.139722                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      544.203282                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6833     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6835                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6835                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.040819                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.588322                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.942463                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5790     84.71%     84.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             288      4.21%     88.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             181      2.65%     91.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              61      0.89%     92.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              66      0.97%     93.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             161      2.36%     95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              22      0.32%     96.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.15%     96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              10      0.15%     96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               9      0.13%     96.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.13%     96.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              11      0.16%     96.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             163      2.38%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               7      0.10%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.07%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               8      0.12%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.09%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.04%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.01%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.19%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             4      0.06%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6835                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4713712824                       # Total ticks spent queuing
system.physmem.totMemAccLat                8448169074                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    995855000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       23666.66                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42416.66                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.06                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.05                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        27.14                       # Average write queue length when enqueuing
system.physmem.readRowHits                     166377                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     80909                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.06                       # Row buffer hit rate for writes
system.physmem.avgGap                      8431906.54                       # Average gap between requests
system.physmem.pageHitRate                      73.56                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  348886440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  190364625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 827283600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                458148960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187370795040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            84523956795                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1647087865500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1920807300960                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.569582                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2739939393002                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95792840000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32988240498                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  322917840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  176195250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 726242400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                429474960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187370795040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            83768933655                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1647750166500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1920544725645                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.478051                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2741046257852                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95792840000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31880394648                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     7828                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7828                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1457                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6371                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         7828                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7828    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7828                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6434                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 10362.060926                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  9317.145265                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5859.670820                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6278     97.58%     97.58% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          144      2.24%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            7      0.11%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            4      0.06%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::212992-229375            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6434                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1109412500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1109412500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1109412500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5016     77.96%     77.96% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1418     22.04%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6434                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7828                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7828                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6434                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6434                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        14262                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    22804186                       # DTB read hits
system.cpu0.dtb.read_misses                      6713                       # DTB read misses
system.cpu0.dtb.write_hits                   17553531                       # DTB write hits
system.cpu0.dtb.write_misses                     1115                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3455                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1817                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                22810899                       # DTB read accesses
system.cpu0.dtb.write_accesses               17554646                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         40357717                       # DTB hits
system.cpu0.dtb.misses                           7828                       # DTB misses
system.cpu0.dtb.accesses                     40365545                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3348                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3348                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          298                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3050                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10683.319039                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  9538.524469                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5751.182189                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          887     38.04%     38.04% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1322     56.69%     94.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575           85      3.64%     98.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           28      1.20%     99.57% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959            7      0.30%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::114688-122879            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1109040500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1109040500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1109040500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2034     87.22%     87.22% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          298     12.78%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2332                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5680                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   108563333                       # ITB inst hits
system.cpu0.itb.inst_misses                      3348                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2150                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               108566681                       # ITB inst accesses
system.cpu0.itb.hits                        108563333                       # DTB hits
system.cpu0.itb.misses                           3348                       # DTB misses
system.cpu0.itb.accesses                    108566681                       # DTB accesses
system.cpu0.numCycles                      5737441138                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  105480509                       # Number of instructions committed
system.cpu0.committedOps                    127164191                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            112285314                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9820                       # Number of float alu accesses
system.cpu0.num_func_calls                   10414111                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     14574473                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   112285314                       # number of integer instructions
system.cpu0.num_fp_insts                         9820                       # number of float instructions
system.cpu0.num_int_register_reads          205015592                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          77505457                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7560                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           459494635                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           48916829                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     41493426                       # number of memory refs
system.cpu0.num_load_insts                   23055800                       # Number of load instructions
system.cpu0.num_store_insts                  18437626                       # Number of store instructions
system.cpu0.num_idle_cycles              5489199817.904087                       # Number of idle cycles
system.cpu0.num_busy_cycles              248241320.095913                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.043267                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.956733                       # Percentage of idle cycles
system.cpu0.Branches                         25703635                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 88750967     68.09%     68.09% # Class of executed instruction
system.cpu0.op_class::IntMult                   92819      0.07%     68.16% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8217      0.01%     68.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.17% # Class of executed instruction
system.cpu0.op_class::MemRead                23055800     17.69%     85.86% # Class of executed instruction
system.cpu0.op_class::MemWrite               18437626     14.14%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 130347702                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1862                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           694931                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          494.123274                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           39503506                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           695443                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            56.803370                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1135131000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.123274                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.965085                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.965085                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         81393420                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        81393420                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     21551304                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       21551304                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     16831338                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      16831338                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       318322                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       318322                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       365658                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       365658                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       362750                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       362750                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     38382642                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        38382642                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     38700964                       # number of overall hits
system.cpu0.dcache.overall_hits::total       38700964                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       398253                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       398253                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       324071                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       324071                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       128299                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       128299                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21791                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21791                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19751                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19751                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       722324                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        722324                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       850623                       # number of overall misses
system.cpu0.dcache.overall_misses::total       850623                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5056802000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5056802000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5106772500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   5106772500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    332740500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    332740500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    437773500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    437773500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1801500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1801500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  10163574500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  10163574500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  10163574500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  10163574500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     21949557                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     21949557                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     17155409                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     17155409                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446621                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       446621                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       387449                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       387449                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       382501                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       382501                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     39104966                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     39104966                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     39551587                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     39551587                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.018144                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.018144                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018890                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018890                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.287266                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.287266                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056242                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056242                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051636                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051636                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018471                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.018471                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021507                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.021507                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12697.461162                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12697.461162                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15758.190335                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15758.190335                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15269.629664                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15269.629664                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22164.624576                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22164.624576                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14070.658735                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14070.658735                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11948.389004                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11948.389004                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       507088                       # number of writebacks
system.cpu0.dcache.writebacks::total           507088                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25317                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25317                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15125                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15125                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25317                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25317                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25317                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25317                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       372936                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       372936                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324071                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       324071                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100997                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       100997                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6666                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6666                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19751                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19751                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       697007                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       697007                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       798004                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       798004                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21110                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19686                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40796                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4291277500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4291277500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4782701500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4782701500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1606991500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1606991500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    101428000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    101428000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    418075500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    418075500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1748500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1748500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9073979000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   9073979000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10680970500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  10680970500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   4433767500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4433767500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3394597500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3394597500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   7828365000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7828365000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016991                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016991                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018890                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018890                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.226136                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.226136                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017205                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.017205                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051636                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051636                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.017824                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.017824                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020176                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.020176                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11506.739762                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11506.739762                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14758.190335                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14758.190335                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15911.279543                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15911.279543                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15215.721572                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15215.721572                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21167.307984                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21167.307984                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13018.490489                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13018.490489                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13384.607721                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13384.607721                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210031.620085                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210031.620085                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172437.138068                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172437.138068                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191890.503971                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191890.503971                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1106064                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.455953                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          107456748                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1106576                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            97.107427                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      13496677000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.455953                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998937                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998937                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        218233251                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       218233251                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    107456748                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      107456748                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    107456748                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       107456748                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    107456748                       # number of overall hits
system.cpu0.icache.overall_hits::total      107456748                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1106585                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1106585                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1106585                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1106585                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1106585                       # number of overall misses
system.cpu0.icache.overall_misses::total      1106585                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10879255500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10879255500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10879255500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10879255500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10879255500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10879255500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    108563333                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    108563333                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    108563333                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    108563333                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    108563333                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    108563333                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010193                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010193                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010193                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010193                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010193                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010193                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9831.378069                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9831.378069                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9831.378069                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9831.378069                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9831.378069                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9831.378069                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1106585                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1106585                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1106585                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1106585                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1106585                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1106585                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10325963000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  10325963000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10325963000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  10325963000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10325963000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  10325963000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    800795500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    800795500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    800795500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    800795500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010193                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010193                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010193                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010193                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9331.378069                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  9331.378069                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9331.378069                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  9331.378069                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1850657                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1850711                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           45                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       237577                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          266648                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16090.167348                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3241094                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          282873                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           11.457771                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle    2844827650500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7840.907632                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.369036                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.138555                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4562.781634                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1957.525775                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1727.444715                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.478571                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000084                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.278490                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119478                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.105435                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.982066                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1088                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15130                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           11                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          286                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          359                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          432                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3231                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7855                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3884                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.066406                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.923462                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        60109727                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       60109727                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         8002                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3594                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         11596                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       507087                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       507087                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28350                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28350                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1666                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1666                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       228036                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       228036                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1059903                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1059903                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       386161                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       386161                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         8002                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3594                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1059903                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       614197                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1685696                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         8002                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3594                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1059903                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       614197                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1685696                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          229                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          110                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          339                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26033                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26033                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18081                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18081                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        41652                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        41652                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        46682                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        46682                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94438                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        94438                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          229                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          110                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        46682                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       136090                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       183111                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          229                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          110                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        46682                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       136090                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       183111                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      5419000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2507000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total      7926000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    480959500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    480959500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    368223000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    368223000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1666996                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1666996                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1951085500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1951085500                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   2317097000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   2317097000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   2767769000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   2767769000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      5419000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2507000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2317097000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   4718854500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   7043877500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      5419000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2507000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2317097000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   4718854500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   7043877500                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         8231                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3704                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        11935                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       507087                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       507087                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54383                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        54383                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19747                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19747                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269688                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269688                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1106585                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1106585                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       480599                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       480599                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         8231                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3704                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1106585                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       750287                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1868807                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         8231                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3704                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1106585                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       750287                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1868807                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.028404                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.478697                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.478697                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.915633                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.915633                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154445                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154445                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042186                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042186                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.196501                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.196501                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042186                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.181384                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.097983                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027822                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.029698                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042186                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.181384                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.097983                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23380.530973                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18474.993278                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18474.993278                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20365.189978                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20365.189978                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       416749                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       416749                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46842.540574                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46842.540574                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49635.769676                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49635.769676                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29307.789237                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29307.789237                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49635.769676                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34674.513190                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 38467.800951                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23663.755459                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22790.909091                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49635.769676                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34674.513190                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 38467.800951                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       195259                       # number of writebacks
system.cpu0.l2cache.writebacks::total          195259                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1202                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1202                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           29                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           29                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1231                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1231                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1231                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1231                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          229                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          110                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks         8231                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total         8231                       # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       244881                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       244881                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26033                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26033                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18081                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18081                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40450                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        40450                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46682                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46682                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94409                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94409                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          229                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          110                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        46682                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       134859                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       181880                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          229                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          110                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46682                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       134859                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       244881                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       426761                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        30132                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        19686                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        49818                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5892000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13903852400                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13903852400                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    522651500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    522651500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    269507500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    269507500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1348996                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1348996                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1589383000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1589383000                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   2037005000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   2037005000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2197124000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2197124000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2037005000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3786507000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   5829404000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      4045000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1847000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2037005000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3786507000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13903852400                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  19733256400                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    733130500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   4264886500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4998017000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   3246952500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   3246952500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    733130500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   7511839000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   8244969500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.028404                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.478697                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.478697                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.915633                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.915633                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149988                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149988                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042186                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.196440                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.196440                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.179743                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.097324                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.027822                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.029698                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042186                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.179743                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.228360                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17380.530973                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56777.995843                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20076.499059                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20076.499059                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14905.563852                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14905.563852                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       337249                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       337249                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39292.533993                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39292.533993                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43635.769676                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23272.399877                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23272.399877                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28077.525415                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32050.824720                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43635.769676                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28077.525415                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46239.596402                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202031.572714                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165870.735431                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164937.138068                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164937.138068                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 184131.753113                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165501.816612                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq         64679                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1685922                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        30913                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        19686                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       869596                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1383128                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       312557                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        88259                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42246                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       111569                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           44                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       298532                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       285304                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1106585                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       579491                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3316089                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2519725                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10102                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        22430                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5868346                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70857528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84663704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        32924                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         155568972                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    1147635                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4840235                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       1.218671                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.413345                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           3781818     78.13%     78.13% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2           1058417     21.87%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4840235                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    2418139995                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    114234000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1668899500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1193519480                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6398000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     14203990                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     3364                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3364                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          665                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2699                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         3364                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3364    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3364                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2594                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 10057.247494                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  9203.479719                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5035.039152                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         1036     39.94%     39.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         1440     55.51%     95.45% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           55      2.12%     97.57% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           56      2.16%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            6      0.23%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2594                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1650887468                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1650887468    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1650887468                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1937     74.67%     74.67% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          657     25.33%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2594                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3364                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3364                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2594                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2594                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5958                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     6310579                       # DTB read hits
system.cpu1.dtb.read_misses                      2859                       # DTB read misses
system.cpu1.dtb.write_hits                    4631996                       # DTB write hits
system.cpu1.dtb.write_misses                      505                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2036                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   323                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 6313438                       # DTB read accesses
system.cpu1.dtb.write_accesses                4632501                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         10942575                       # DTB hits
system.cpu1.dtb.misses                           3364                       # DTB misses
system.cpu1.dtb.accesses                     10945939                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1578                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10738.482385                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  9680.648713                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5669.589944                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          351     31.71%     31.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          484     43.72%     75.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          202     18.25%     93.68% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479           20      1.81%     95.48% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.09%     95.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           23      2.08%     97.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           15      1.36%     99.01% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            5      0.45%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            6      0.54%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1650350468                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1650350468    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1650350468                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    27093131                       # ITB inst hits
system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1148                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                27094877                       # ITB inst accesses
system.cpu1.itb.hits                         27093131                       # DTB hits
system.cpu1.itb.misses                           1746                       # DTB misses
system.cpu1.itb.accesses                     27094877                       # DTB accesses
system.cpu1.numCycles                      5736521358                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   26153786                       # Number of instructions committed
system.cpu1.committedOps                     32053131                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             28968286                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1857                       # Number of float alu accesses
system.cpu1.num_func_calls                    3299674                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2947168                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    28968286                       # number of integer instructions
system.cpu1.num_fp_insts                         1857                       # number of float instructions
system.cpu1.num_int_register_reads           54552282                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          20759353                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           117965505                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            9826508                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     11178844                       # number of memory refs
system.cpu1.num_load_insts                    6422284                       # Number of load instructions
system.cpu1.num_store_insts                   4756560                       # Number of store instructions
system.cpu1.num_idle_cycles              5660914446.273914                       # Number of idle cycles
system.cpu1.num_busy_cycles              75606911.726086                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.013180                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.986820                       # Percentage of idle cycles
system.cpu1.Branches                          6348758                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 21763864     65.97%     65.97% # Class of executed instruction
system.cpu1.op_class::IntMult                   43243      0.13%     66.10% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     66.10% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3315      0.01%     66.11% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     66.11% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     66.11% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     66.11% # Class of executed instruction
system.cpu1.op_class::MemRead                 6422284     19.47%     85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite                4756560     14.42%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  32989332                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2773                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements           185916                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          465.807736                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           10656106                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           186281                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            57.204471                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     104850302500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   465.807736                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.909781                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.909781                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           66                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         22064450                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        22064450                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      5988472                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        5988472                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4434786                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4434786                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        48931                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        48931                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        78766                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        78766                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        70801                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        70801                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     10423258                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        10423258                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     10472189                       # number of overall hits
system.cpu1.dcache.overall_hits::total       10472189                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       133050                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       133050                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        91601                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        91601                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30372                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30372                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17242                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17242                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23381                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23381                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       224651                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        224651                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       255023                       # number of overall misses
system.cpu1.dcache.overall_misses::total       255023                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1943965500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1943965500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2376775500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2376775500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    323304000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    323304000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    547906000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    547906000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2312500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2312500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4320741000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4320741000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4320741000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4320741000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      6121522                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      6121522                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4526387                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4526387                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        79303                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        79303                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96008                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96008                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94182                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94182                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     10647909                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     10647909                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     10727212                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     10727212                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.021735                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.021735                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.020237                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.020237                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.382987                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.382987                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.179589                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.179589                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.248253                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.248253                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.021098                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.021098                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.023773                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.023773                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14610.789177                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14610.789177                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25947.047521                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25947.047521                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18750.956966                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18750.956966                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23433.813780                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23433.813780                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19233.126049                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 19233.126049                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16942.554201                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16942.554201                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       116022                       # number of writebacks
system.cpu1.dcache.writebacks::total           116022                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          266                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12054                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12054                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          266                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          266                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          266                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          266                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       132784                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       132784                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        91601                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        91601                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29597                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29597                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5188                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5188                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23381                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23381                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       224385                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       224385                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       253982                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       253982                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        13773                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        13773                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        11227                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        25000                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        25000                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1804303500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1804303500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2285174500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2285174500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    494107000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    494107000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90251000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90251000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    524565000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    524565000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2272500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2272500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4089478000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4089478000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4583585000                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4583585000                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2232716000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   2232716000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1768357000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   1768357000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   4001073000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   4001073000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.021691                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.021691                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.020237                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.020237                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.373214                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.373214                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054037                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054037                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.248253                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.248253                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.021073                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.021073                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.023676                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.023676                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13588.259881                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13588.259881                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24947.047521                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24947.047521                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16694.496064                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16694.496064                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17396.106399                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17396.106399                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22435.524571                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22435.524571                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18225.273525                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18225.273525                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18046.889150                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18046.889150                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162108.182676                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162108.182676                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157509.307918                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157509.307918                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160042.920000                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160042.920000                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           505537                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.573002                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           26587077                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           506049                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            52.538543                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      84702248000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.573002                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973775                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973775                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          392                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          117                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         54692301                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        54692301                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     26587077                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       26587077                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     26587077                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        26587077                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     26587077                       # number of overall hits
system.cpu1.icache.overall_hits::total       26587077                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       506049                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       506049                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       506049                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        506049                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       506049                       # number of overall misses
system.cpu1.icache.overall_misses::total       506049                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4455517000                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4455517000                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4455517000                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4455517000                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4455517000                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4455517000                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     27093126                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     27093126                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     27093126                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     27093126                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     27093126                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     27093126                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.018678                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.018678                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.018678                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.018678                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.018678                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.018678                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8804.516954                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8804.516954                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8804.516954                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8804.516954                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8804.516954                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8804.516954                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       506049                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       506049                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       506049                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       506049                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       506049                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       506049                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4202492500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   4202492500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4202492500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   4202492500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4202492500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   4202492500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15340000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15340000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15340000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     15340000                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018678                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.018678                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018678                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.018678                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8304.516954                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8304.516954                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8304.516954                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8304.516954                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86666.666667                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86666.666667                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       199458                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       199458                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        58862                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           46506                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15029.734126                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1265349                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           61182                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           20.681720                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  8657.593794                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.281679                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.079815                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3148.961374                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2173.187241                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  1044.630222                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.528418                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000200                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.192197                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.132641                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.063759                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.917342                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1197                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13460                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           35                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1156                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           13                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1596                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11590                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.073059                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001160                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.821533                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        23794594                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       23794594                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3091                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1709                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          4800                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       116022                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       116022                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1472                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1472                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          842                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          842                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        27319                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        27319                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       492294                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       492294                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99296                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        99296                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3091                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1709                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       492294                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       126615                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         623709                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3091                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1709                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       492294                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       126615                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        623709                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          314                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          266                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          580                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28095                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28095                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22537                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22537                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        34715                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        34715                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13755                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        13755                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        68273                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        68273                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          314                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          266                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        13755                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       102988                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       117323                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          314                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          266                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        13755                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       102988                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       117323                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6334500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5311000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     11645500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    538209000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    538209000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    450797500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    450797500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2212500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2212500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1336972500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1336972500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    492390500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    492390500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1491495000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1491495000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6334500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5311000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    492390500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2828467500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3332503500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6334500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5311000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    492390500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2828467500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3332503500                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3405                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1975                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         5380                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       116022                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       116022                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29567                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29567                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23379                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23379                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        62034                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        62034                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       506049                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       506049                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       167569                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       167569                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3405                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1975                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       506049                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       229603                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       741032                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3405                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1975                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       506049                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       229603                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       741032                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.107807                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950215                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950215                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.963985                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.963985                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.559612                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.559612                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.027181                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.027181                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.407432                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.407432                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.027181                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.448548                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.158324                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.092217                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.134684                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.027181                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.448548                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.158324                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20078.448276                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19156.753871                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19156.753871                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20002.551360                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20002.551360                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1106250                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1106250                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38512.818666                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38512.818666                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35797.201018                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35797.201018                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21846.044556                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21846.044556                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35797.201018                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27464.049210                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 28404.520000                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20173.566879                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19966.165414                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35797.201018                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27464.049210                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 28404.520000                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        30696                       # number of writebacks
system.cpu1.l2cache.writebacks::total           30696                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           90                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           90                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           90                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           90                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           90                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           90                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          314                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          266                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          580                       # number of ReadReq MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks         2031                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total         2031                       # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        23725                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        23725                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28095                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28095                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22537                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22537                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        34625                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        34625                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        13755                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        13755                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        68273                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        68273                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          314                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          266                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        13755                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       102898                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       117233                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          314                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          266                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        13755                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       102898                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        23725                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       140958                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        13773                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        13950                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        11227                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        25000                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        25177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      8165500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    839425646                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    839425646                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    455073500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    455073500                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    349086500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    349086500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1972500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1972500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1119618000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1119618000                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    409860500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    409860500                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1081857000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1081857000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    409860500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2201475000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2619501000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4450500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3715000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    409860500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2201475000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    839425646                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3458926646                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14012500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   2122532000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   2136544500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   1684154500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   1684154500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14012500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3806686500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3820699000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.107807                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950215                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950215                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.963985                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.963985                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.558162                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.558162                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.027181                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.407432                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.407432                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.448156                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.158202                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.092217                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.134684                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.027181                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.448156                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.190219                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14078.448276                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35381.481391                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16197.668624                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16197.668624                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15489.483960                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15489.483960                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       986250                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       986250                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32335.537906                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32335.537906                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29797.201018                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15846.044556                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15846.044556                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21394.730704                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22344.399614                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29797.201018                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21394.730704                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24538.704054                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154108.182676                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153157.311828                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150009.307918                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150009.307918                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152267.460000                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 151753.544902                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq         53469                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       734633                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        30913                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        11227                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       478531                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict       680350                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        29761                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        73690                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41411                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85868                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           55                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        84408                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        66733                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       506049                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       504061                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1509072                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       874243                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5299                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9468                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2398082                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     32387844                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24934344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7900                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13620                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          57343708                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    1094784                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      2530004                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       1.405048                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.490902                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1           1505230     59.50%     59.50% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2           1024774     40.50%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       2530004                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     878944000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80122000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    759250500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    390308000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      6063998                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31015                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31015                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59422                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59422                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56602                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180874                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71546                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162796                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40091000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           187549442                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84718000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.390664                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         288350117000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.390664                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.899417                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.899417                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          255                       # number of overall misses
system.iocache.overall_misses::total              255                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32656876                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32656876                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4281964566                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4281964566                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32656876                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32656876                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32656876                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32656876                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128066.180392                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128066.180392                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118207.944070                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118207.944070                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128066.180392                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128066.180392                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128066.180392                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128066.180392                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           265                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs   132.500000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     19906876                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     19906876                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2470764566                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2470764566                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     19906876                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     19906876                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     19906876                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     19906876                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78066.180392                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 78066.180392                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68207.944070                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68207.944070                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 78066.180392                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 78066.180392                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 78066.180392                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 78066.180392                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   130439                       # number of replacements
system.l2c.tags.tagsinuse                63983.082008                       # Cycle average of tags in use
system.l2c.tags.total_refs                     387954                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   194793                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.991622                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12138.175325                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.910023                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.041062                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7215.667264                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2903.196215                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37504.021978                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.955808                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1528.247767                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      561.168860                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  2127.697705                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.185214                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000060                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.110102                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.044299                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.572266                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.023319                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.008563                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.032466                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.976304                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32301                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32046                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          164                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4667                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        27470                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1924                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29877                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.492874                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.488983                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5300600                       # Number of tag accesses
system.l2c.tags.data_accesses                 5300600                       # Number of data accesses
system.l2c.Writeback_hits::writebacks          225955                       # number of Writeback hits
system.l2c.Writeback_hits::total               225955                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            2137                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             661                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2798                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           135                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           145                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               280                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3821                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1461                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5282                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           91                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           51                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        29278                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        45470                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        44948                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           27                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           27                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        11381                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         8374                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         5310                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           144957                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker            91                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            51                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               29278                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               49291                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        44948                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            27                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            27                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               11381                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                9835                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5310                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  150239                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           91                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           51                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              29278                       # number of overall hits
system.l2c.overall_hits::cpu0.data              49291                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        44948                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           27                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           27                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              11381                       # number of overall hits
system.l2c.overall_hits::cpu1.data               9835                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5310                       # number of overall hits
system.l2c.overall_hits::total                 150239                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          8391                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2650                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11041                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          492                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1207                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1699                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11580                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8214                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19794                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17402                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8820                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134398                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2367                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          942                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         6249                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         170188                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17402                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20400                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       134398                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2367                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9156                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) misses
system.l2c.demand_misses::total                189982                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17402                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20400                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       134398                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2367                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9156                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         6249                       # number of overall misses
system.l2c.overall_misses::total               189982                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data      8210000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2280000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     10490000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1358000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1106500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      2464500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1018907000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    666031500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1684938500                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       606500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       166000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   1402771500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    762849500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  13087577967                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker        82500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    194012000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data     84119500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    729023182                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  16261208649                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       606500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       166000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1402771500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1781756500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13087577967                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        82500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    194012000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    750151000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    729023182                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     17946147149                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       606500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       166000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1402771500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1781756500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13087577967                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        82500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    194012000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    750151000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    729023182                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    17946147149                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks       225955                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           225955                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        10528                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3311                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           13839                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          627                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1352                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1979                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15401                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9675                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25076                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           98                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           53                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        46680                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        54290                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       179346                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           28                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           27                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        13748                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         9316                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        11559                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       315145                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker           98                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           53                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           46680                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           69691                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       179346                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           28                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           27                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           13748                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           18991                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11559                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              340221                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker           98                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           53                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          46680                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          69691                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       179346                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           28                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           27                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          13748                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          18991                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11559                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             340221                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.797017                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.800362                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.797818                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.784689                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.892751                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.858514                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.751899                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.848992                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.789360                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.372793                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.162461                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.172170                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.101116                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.540031                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.372793                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.292721                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.172170                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.482123                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.558408                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.071429                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.037736                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.372793                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.292721                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.035714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.172170                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.482123                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.558408                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   978.429269                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   860.377358                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   950.095100                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2760.162602                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   916.735708                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  1450.559152                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87988.514680                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81084.915997                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 85123.699101                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker        83000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80609.786231                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86490.873016                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker        82500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 81965.356992                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89298.832272                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 95548.503120                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80609.786231                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 87341.004902                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81965.356992                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81929.991263                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 94462.355113                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86642.857143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        83000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80609.786231                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 87341.004902                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81965.356992                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81929.991263                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 94462.355113                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              100321                       # number of writebacks
system.l2c.writebacks::total                   100321                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  6                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 6                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         3050                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         3050                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8391                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2650                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11041                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          492                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1207                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1699                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11580                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8214                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19794                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17400                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8820                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134398                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2363                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          942                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       170182                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17400                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20400                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134398                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2363                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9156                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           189976                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17400                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20400                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134398                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2363                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9156                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         6249                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          189976                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        21110                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        13769                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44078                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        19686                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11227                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30913                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        40796                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        24996                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        74991                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    174583000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     55064000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    229647000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     10311000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     25083500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     35394500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    903107000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    583891500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1486998500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       146000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   1228508000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    674649500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11743597967                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    170183500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     74699500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  14558926649                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       146000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1228508000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1577756500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11743597967                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    170183500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    658591000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  16045925149                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       536500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       146000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1228508000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1577756500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11743597967                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    170183500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    658591000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    666533182                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  16045925149                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    570734000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3884897500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10826500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1874631500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6341089500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2912289500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1493293500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4405583000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    570734000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   6797187000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10826500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3367925000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10746672500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.797017                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.800362                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.797818                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784689                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.892751                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.858514                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.751899                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.848992                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.789360                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.162461                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.101116                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.540012                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.292721                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.482123                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.558390                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.071429                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.037736                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.372751                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.292721                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.749378                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.035714                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.171880                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.482123                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.540618                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.558390                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20805.982600                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20778.867925                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.474685                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20957.317073                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20781.690141                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20832.548558                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77988.514680                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71084.915997                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 75123.699101                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76490.873016                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79298.832272                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85549.157073                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77341.004902                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71929.991263                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 84462.906625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        73000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70603.908046                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77341.004902                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72020.101566                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71929.991263                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 84462.906625                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184031.146376                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136148.703610                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143860.644766                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147937.087270                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133009.129776                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142515.543622                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166614.055300                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134738.558169                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 143306.163406                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               44078                       # Transaction distribution
system.membus.trans_dist::ReadResp             214515                       # Transaction distribution
system.membus.trans_dist::WriteReq              30913                       # Transaction distribution
system.membus.trans_dist::WriteResp             30913                       # Transaction distribution
system.membus.trans_dist::Writeback            136511                       # Transaction distribution
system.membus.trans_dist::CleanEvict            15728                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            75283                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40251                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12822                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            4                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40262                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19712                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        170437                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107916                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13732                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       672670                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       794352                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108921                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108921                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 903273                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162796                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27464                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18608200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18798528                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                21115648                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123870                       # Total snoops (count)
system.membus.snoop_fanout::samples            589976                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  589976    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              589976                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88273000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11464500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1021914451                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1141120383                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64390592                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq              44082                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            479204                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30913                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30913                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           362509                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           82484                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           77999                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40531                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         118530                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           93                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           93                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51218                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51218                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       435137                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1069100                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       319954                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1389054                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31596740                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4900924                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               36497664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          452334                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1194337                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.170309                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.375904                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 990931     82.97%     82.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 203406     17.03%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1194337                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          799819351                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         609335323                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         239074701                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------