path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.675181                       # Number of seconds simulated
sim_ticks                                2675180779000                       # Number of ticks simulated
final_tick                               2675180779000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 349036                       # Simulator instruction rate (inst/s)
host_op_rate                                   416751                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            14917331050                       # Simulator tick rate (ticks/s)
host_mem_usage                                 433588                       # Number of bytes of host memory used
host_seconds                                   179.33                       # Real time elapsed on the host
sim_insts                                    62593972                       # Number of instructions simulated
sim_ops                                      74737529                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           120908                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data           513788                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      6659968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst            37828                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           531832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher      3262144                       # Number of bytes read from this memory
system.physmem.bytes_read::total            135383236                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       120908                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst        37828                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          158736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4300032                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7329168                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst              8117                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data              8087                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       104062                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst               682                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8328                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher        50971                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15712287                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           67188                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               824472                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46447798                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            48                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            96                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               45196                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              192057                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2489539                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            48                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               14140                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              198802                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher      1219411                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50607135                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          45196                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          14140                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              59337                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1607380                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6355                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            1125956                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2739691                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1607380                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46447798                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           48                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           96                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              45196                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             198412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2489539                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           48                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              14140                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1324758                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher      1219411                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53346826                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15712287                       # Number of read requests accepted
system.physmem.writeReqs                       824472                       # Number of write requests accepted
system.physmem.readBursts                    15712287                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     824472                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM               1005465984                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    120384                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7344256                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 135383236                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7329168                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1881                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709695                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          15472                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              981539                       # Per bank write bursts
system.physmem.perBankRdBursts::1              981448                       # Per bank write bursts
system.physmem.perBankRdBursts::2              981211                       # Per bank write bursts
system.physmem.perBankRdBursts::3              981521                       # Per bank write bursts
system.physmem.perBankRdBursts::4              988300                       # Per bank write bursts
system.physmem.perBankRdBursts::5              981533                       # Per bank write bursts
system.physmem.perBankRdBursts::6              981210                       # Per bank write bursts
system.physmem.perBankRdBursts::7              981071                       # Per bank write bursts
system.physmem.perBankRdBursts::8              981831                       # Per bank write bursts
system.physmem.perBankRdBursts::9              982015                       # Per bank write bursts
system.physmem.perBankRdBursts::10             981421                       # Per bank write bursts
system.physmem.perBankRdBursts::11             980878                       # Per bank write bursts
system.physmem.perBankRdBursts::12             981926                       # Per bank write bursts
system.physmem.perBankRdBursts::13             981948                       # Per bank write bursts
system.physmem.perBankRdBursts::14             981516                       # Per bank write bursts
system.physmem.perBankRdBursts::15             981038                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7155                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7293                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6957                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6994                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7537                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7187                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7207                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7058                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7329                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7596                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7177                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6681                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7505                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7329                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7034                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6715                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2675178052500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    6799                       # Read request sizes (log2)
system.physmem.readPktSize::3                15532057                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  173431                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  67188                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1100287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    996591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    996926                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   1111424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   1006011                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   1072049                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2766642                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   2669294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   3474563                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                    133275                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                   114946                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                   106575                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                   103058                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20020                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    19187                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    18941                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      241                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       48                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                       35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                       23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4098                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4820                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6804                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7024                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1051606                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      963.108084                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     883.927529                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     220.726845                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          33004      3.14%      3.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22001      2.09%      5.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         9307      0.89%      6.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2514      0.24%      6.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3272      0.31%      6.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2167      0.21%      6.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8722      0.83%      7.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1051      0.10%      7.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       969568     92.20%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1051606                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6601                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      2380.003939                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    98592.588392                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-262143         6595     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-786431            1      0.02%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-1.04858e+06            2      0.03%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6601                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6601                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.384336                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.341066                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.250693                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2463     37.31%     37.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 32      0.48%     37.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               3686     55.84%     93.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                215      3.26%     96.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 85      1.29%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 50      0.76%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 28      0.42%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 18      0.27%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 14      0.21%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  7      0.11%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  3      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6601                       # Writes before turning the bus around for reads
system.physmem.totQLat                   408788863752                       # Total ticks spent queuing
system.physmem.totMemAccLat              703358976252                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  78552030000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26020.26                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44770.26                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         375.85                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.75                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.61                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.74                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.96                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.94                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         6.50                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                   14689438                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     84116                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.50                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.29                       # Row buffer hit rate for writes
system.physmem.avgGap                       161771.61                       # Average gap between requests
system.physmem.pageHitRate                      93.35                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     2326940534750                       # Time in different power states
system.physmem.memoryStateTime::REF       89330020000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      258906121500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                3975289920                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                3974851440                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                2169057000                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                2168817750                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0              61291097400                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1              61250069400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               371874240                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               371731680                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          174729519120                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          174729519120                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          149034867885                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          147923300340                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          1474373657250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          1475348716500                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            1865945362815                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            1865767006230                       # Total energy per rank (pJ)
system.physmem.averagePower::0             697.503604                       # Core power per rank (mW)
system.physmem.averagePower::1             697.436933                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           18                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           18                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           18                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq            16891737                       # Transaction distribution
system.membus.trans_dist::ReadResp           16891737                       # Transaction distribution
system.membus.trans_dist::WriteReq             769090                       # Transaction distribution
system.membus.trans_dist::WriteResp            769090                       # Transaction distribution
system.membus.trans_dist::Writeback             67188                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            56135                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          22757                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15472                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             15580                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8709                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384390                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13404                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2098                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      2043502                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4443432                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               35507496                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      2392696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4196                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18456148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     20879924                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               145136180                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            70292                       # Total snoops (count)
system.membus.snoop_fanout::samples            326383                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  326383    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              326383                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1567209495                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11789999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy             2092500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         18080219999                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4994463970                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        38410223885                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    91391                       # number of replacements
system.l2c.tags.tagsinuse                54779.294121                       # Cycle average of tags in use
system.l2c.tags.total_refs                     364235                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   156090                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.333493                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    8096.170170                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.060665                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     1.035962                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      869.411373                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     1869.125081                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.888363                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      410.348906                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     3214.362362                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.123538                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.013266                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.028521                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.446737                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000029                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.006261                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.049047                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.168450                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.835866                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        51568                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        13123                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2           28                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4964                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        46576                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          213                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1345                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        11561                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.786865                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000122                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.200241                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  4855174                       # Number of tag accesses
system.l2c.tags.data_accesses                 4855174                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker          111                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           56                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst               5971                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              15212                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        88244                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           87                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           25                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst               4855                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data              12536                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher        47744                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 174841                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          208041                       # number of Writeback hits
system.l2c.Writeback_hits::total               208041                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            3552                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1697                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                5249                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           114                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           201                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               315                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             2350                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             2153                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 4503                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker           111                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            56                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst                5971                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               17562                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        88244                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            87                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            25                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                4855                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               14689                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher        47744                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  179344                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker          111                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           56                       # number of overall hits
system.l2c.overall_hits::cpu0.inst               5971                       # number of overall hits
system.l2c.overall_hits::cpu0.data              17562                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        88244                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           87                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           25                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               4855                       # number of overall hits
system.l2c.overall_hits::cpu1.data              14689                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher        47744                       # number of overall hits
system.l2c.overall_hits::total                 179344                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             1474                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             3581                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       104062                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst              586                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             4041                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher        50971                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               164723                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          7774                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          5401                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             13175                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         1167                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1038                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            2205                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data           4506                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           4295                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total               8801                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              1474                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data              8087                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       104062                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst               586                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8336                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher        50971                       # number of demand (read+write) misses
system.l2c.demand_misses::total                173524                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             1474                       # number of overall misses
system.l2c.overall_misses::cpu0.data             8087                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       104062                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu1.inst              586                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8336                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher        50971                       # number of overall misses
system.l2c.overall_misses::total               173524                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       107000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       298500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    119004500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    272579750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher   9018021941                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       164250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst     50120250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    314939500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher   6107091681                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    15882327372                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     13917901                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      3379857                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     17297758                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       704472                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      4360812                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      5065284                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    330076436                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    308773222                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total    638849658                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       107000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       298500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    119004500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data    602656186                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher   9018021941                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       164250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst     50120250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    623712722                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher   6107091681                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     16521177030                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       107000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       298500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    119004500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data    602656186                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher   9018021941                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       164250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst     50120250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    623712722                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   6107091681                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    16521177030                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker          113                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           60                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst           7445                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          18793                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       192306                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           89                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           25                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst           5441                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data          16577                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        98715                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             339564                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       208041                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           208041                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11326                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         7098                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18424                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         1281                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1239                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2520                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data         6856                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         6448                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            13304                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          113                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           60                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst            7445                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           25649                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       192306                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           89                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           25                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            5441                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           23025                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        98715                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              352868                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          113                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           60                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst           7445                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          25649                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       192306                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           89                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           25                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           5441                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          23025                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        98715                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             352868                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.017699                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.066667                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.197985                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.190550                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.022472                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.107701                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.243771                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.485101                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.686385                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.760919                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.715100                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.911007                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.837772                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.875000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.657235                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.666098                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.661530                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.017699                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.066667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.197985                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.315295                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.022472                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.107701                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.362041                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.491753                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.017699                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.066667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.197985                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.315295                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.022472                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.107701                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.362041                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.491753                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        53500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74625                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80735.753053                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 76118.332868                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82125                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85529.436860                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77936.030685                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 96418.395561                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1790.313995                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   625.783559                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  1312.922808                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   603.660668                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4201.167630                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  2297.180952                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73252.648913                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71891.320605                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 72588.303375                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        53500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74625                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 80735.753053                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 74521.600841                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82125                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85529.436860                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74821.583733                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 95209.752138                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        53500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74625                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 80735.753053                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 74521.600841                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82125                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85529.436860                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74821.583733                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 95209.752138                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               67188                       # number of writebacks
system.l2c.writebacks::total                    67188                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         1474                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         3581                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       104062                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst          585                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         4041                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher        50971                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          164722                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         7774                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         5401                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        13175                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         1167                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1038                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         2205                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data         4506                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         4295                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total          8801                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         1474                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data         8087                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       104062                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst          585                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8336                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher        50971                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           173523                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         1474                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data         8087                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       104062                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst          585                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8336                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher        50971                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          173523                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        82500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       250000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    100663500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    227794750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher   7718948941                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       138750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     42844000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    264712000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher   5479054183                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  13834488624                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     78078748                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     54145386                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    132224134                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     11801161                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     10401535                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     22202696                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    273742064                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    254569278                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total    528311342                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        82500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       250000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    100663500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data    501536814                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher   7718948941                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       138750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst     42844000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    519281278                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher   5479054183                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  14362799966                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        82500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       250000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    100663500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data    501536814                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher   7718948941                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       138750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst     42844000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    519281278                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   5479054183                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  14362799966                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    352521750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 156454617998                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5602750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  10840620247                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167653362745                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1361015000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15491155851                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16852170851                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    352521750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 157815632998                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5602750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26331776098                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 184505533596                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.017699                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066667                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.197985                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.190550                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.022472                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.107517                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.243771                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.485099                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.686385                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.760919                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.715100                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.911007                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.837772                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.875000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.657235                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.666098                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.661530                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.017699                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.066667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.197985                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.315295                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.022472                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.107517                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.362041                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.491750                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.017699                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.066667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.197985                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.315295                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.541127                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.022472                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.107517                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.362041                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.516345                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.491750                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        41250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        69375                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        41250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        69375                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 82771.736116                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        41250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        69375                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 82771.736116                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            1633013                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           1633009                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            769090                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           769090                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           208041                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           61292                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         23072                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          84364                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           39                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           39                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            23321                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           23321                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      2956029                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      2099720                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               5055749                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     25795270                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     15582958                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               41378228                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          171942                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           753795                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean                   1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev                  0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 753795    100.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             753795                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         2576673570                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2390227339                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1329617427                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq             16716140                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16716140                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8087                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8087                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30962                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8820                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1044                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2384390                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     31064064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     31064064                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                33448454                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        40731                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio        17640                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio         2088                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total      2392696                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                126648952                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             21726000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4416000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               528000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy         15532032000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2376303000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         39178496115                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     7131006                       # DTB read hits
system.cpu0.dtb.read_misses                      3644                       # DTB read misses
system.cpu0.dtb.write_hits                    6127729                       # DTB write hits
system.cpu0.dtb.write_misses                      663                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1893                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   116                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 7134650                       # DTB read accesses
system.cpu0.dtb.write_accesses                6128392                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         13258735                       # DTB hits
system.cpu0.dtb.misses                           4307                       # DTB misses
system.cpu0.dtb.accesses                     13263042                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    31182741                       # ITB inst hits
system.cpu0.itb.inst_misses                      2176                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1281                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                31184917                       # ITB inst accesses
system.cpu0.itb.hits                         31182741                       # DTB hits
system.cpu0.itb.misses                           2176                       # DTB misses
system.cpu0.itb.accesses                     31184917                       # DTB accesses
system.cpu0.numCycles                      5349463018                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   30507218                       # Number of instructions committed
system.cpu0.committedOps                     36803230                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             32859018                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5449                       # Number of float alu accesses
system.cpu0.num_func_calls                    1290775                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      3957686                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    32859018                       # number of integer instructions
system.cpu0.num_fp_insts                         5449                       # number of float instructions
system.cpu0.num_int_register_reads           60131579                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          21902535                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                4535                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                916                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           133610661                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           14490121                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     13795466                       # number of memory refs
system.cpu0.num_load_insts                    7343231                       # Number of load instructions
system.cpu0.num_store_insts                   6452235                       # Number of store instructions
system.cpu0.num_idle_cycles              4898257252.279955                       # Number of idle cycles
system.cpu0.num_busy_cycles              451205765.720045                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.084346                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.915654                       # Percentage of idle cycles
system.cpu0.Branches                          5660514                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                16321      0.04%      0.04% # Class of executed instruction
system.cpu0.op_class::IntAlu                 23591543     62.99%     63.03% # Class of executed instruction
system.cpu0.op_class::IntMult                   47189      0.13%     63.16% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     63.16% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              1591      0.00%     63.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     63.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     63.17% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     63.17% # Class of executed instruction
system.cpu0.op_class::MemRead                 7343231     19.61%     82.77% # Class of executed instruction
system.cpu0.op_class::MemWrite                6452235     17.23%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  37452110                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   51950                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           369506                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.465010                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           30812705                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           370018                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            83.273530                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10201796750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.465010                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998955                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998955                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          506                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         62735467                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        62735467                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     30812705                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       30812705                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     30812705                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        30812705                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     30812705                       # number of overall hits
system.cpu0.icache.overall_hits::total       30812705                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       370019                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       370019                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       370019                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        370019                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       370019                       # number of overall misses
system.cpu0.icache.overall_misses::total       370019                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   3209345752                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   3209345752                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   3209345752                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   3209345752                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   3209345752                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   3209345752                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     31182724                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     31182724                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     31182724                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     31182724                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     31182724                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     31182724                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011866                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011866                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011866                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011866                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011866                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011866                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8673.462044                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8673.462044                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8673.462044                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8673.462044                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8673.462044                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8673.462044                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       370019                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       370019                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       370019                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       370019                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       370019                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       370019                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   2653955748                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   2653955748                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   2653955748                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   2653955748                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   2653955748                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   2653955748                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    531257750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    531257750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    531257750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    531257750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011866                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011866                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011866                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.011866                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011866                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.011866                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7172.485056                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7172.485056                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7172.485056                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7172.485056                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7172.485056                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7172.485056                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified      4129417                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       113341                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      3763718                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          300                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           22                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued       252036                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page       312183                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements          213190                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16168.240053                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs            848978                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          228702                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.712158                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      7921739000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  4749.054127                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.517230                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.260718                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   821.211493                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1542.145038                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  9052.051448                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.289859                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000215                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000016                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.050123                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.094125                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.552493                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.986831                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8284                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7219                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1260                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         1944                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         5080                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         1775                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         1943                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3501                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.505615                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000549                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.440613                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        17864213                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       17864213                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         4737                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         2374                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst       361048                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       184302                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        552461                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       286361                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       286361                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data         5612                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total         5612                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data          831                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total          831                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       133749                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       133749                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         4737                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         2374                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst       361048                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       318051                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total         686210                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         4737                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         2374                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst       361048                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       318051                       # number of overall hits
system.cpu0.l2cache.overall_hits::total        686210                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          225                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          146                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst         8693                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        48360                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        57424                       # number of ReadReq misses
system.cpu0.l2cache.Writeback_misses::writebacks            2                       # number of Writeback misses
system.cpu0.l2cache.Writeback_misses::total            2                       # number of Writeback misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        18405                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        18405                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        10323                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        10323                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        24100                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        24100                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          225                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          146                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst         8693                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data        72460                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total        81524                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          225                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          146                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst         8693                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data        72460                       # number of overall misses
system.cpu0.l2cache.overall_misses::total        81524                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4897000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      3307000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst    300815745                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   1253383203                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1562402948                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    288253128                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    288253128                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    204026156                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    204026156                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1056000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1056000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data    855610215                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total    855610215                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4897000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      3307000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst    300815745                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   2108993418                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   2418013163                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4897000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      3307000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst    300815745                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   2108993418                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   2418013163                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         4962                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         2520                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst       369741                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       232662                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       609885                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       286363                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       286363                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        24017                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        24017                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        11154                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        11154                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       157849                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       157849                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         4962                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         2520                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst       369741                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       390511                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total       767734                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         4962                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         2520                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst       369741                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       390511                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total       767734                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.045345                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.057937                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.023511                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.207855                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.094155                       # miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_miss_rate::writebacks     0.000007                       # miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_miss_rate::total     0.000007                       # miss rate for Writeback accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.766332                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.766332                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.925498                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.925498                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.152678                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.152678                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.045345                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.057937                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.023511                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.185552                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.106188                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.045345                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.057937                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.023511                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.185552                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.106188                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21764.444444                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22650.684932                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 34604.365006                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25917.766811                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27208.187308                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15661.674980                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15661.674980                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19764.230941                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19764.230941                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       528000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       528000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 35502.498548                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35502.498548                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21764.444444                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22650.684932                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34604.365006                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29105.622661                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 29660.138892                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21764.444444                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22650.684932                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34604.365006                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29105.622661                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 29660.138892                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         1020                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              31                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    32.903226                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       141584                       # number of writebacks
system.cpu0.l2cache.writebacks::total          141584                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst         1192                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data          751                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total         1943                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data          493                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total          493                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst         1192                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1244                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         2436                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst         1192                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1244                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         2436                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          225                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          146                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst         7501                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        47609                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        55481                       # number of ReadReq MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::writebacks            2                       # number of Writeback MSHR misses
system.cpu0.l2cache.Writeback_mshr_misses::total            2                       # number of Writeback MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       252027                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       252027                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        18405                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        18405                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        10323                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        10323                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        23607                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        23607                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          225                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          146                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst         7501                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data        71216                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total        79088                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          225                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          146                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst         7501                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data        71216                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       252027                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       331115                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3322000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2285000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst    227161754                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data    910924475                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1143693229                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  10450561115                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  10450561115                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    330354697                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    330354697                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    150011322                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    150011322                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       888000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       888000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data    642746273                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total    642746273                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3322000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2285000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst    227161754                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   1553670748                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   1786439502                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3322000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2285000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst    227161754                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   1553670748                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  10450561115                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  12237000617                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    478295250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 176453658508                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 176931953758                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   1575154999                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   1575154999                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    478295250                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 178028813507                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 178507108757                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.045345                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057937                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.020287                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.204627                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.090970                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks     0.000007                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total     0.000007                       # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.766332                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.766332                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.925498                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.925498                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.149554                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.149554                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.045345                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057937                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.020287                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.182366                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.103015                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.045345                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057937                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.020287                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.182366                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.431289                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30284.195974                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20614.142301                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17949.182124                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       444000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       444000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 27226.935782                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27226.935782                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30284.195974                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21816.315828                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22587.996940                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           355829                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          496.967445                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11721464                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           356159                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            32.910762                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        767187000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.967445                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970640                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.970640                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          330                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          330                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.644531                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         24668842                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        24668842                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5548461                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5548461                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5771889                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5771889                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        62661                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        62661                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       153118                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       153118                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       152372                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       152372                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     11320350                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        11320350                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     11383011                       # number of overall hits
system.cpu0.dcache.overall_hits::total       11383011                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       178532                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       178532                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       183693                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       183693                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        66756                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total        66756                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10498                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        10498                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        11173                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        11173                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       362225                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        362225                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       428981                       # number of overall misses
system.cpu0.dcache.overall_misses::total       428981                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2139066005                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   2139066005                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   2832298001                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   2832298001                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    176126000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    176126000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    261398841                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    261398841                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1128000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1128000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   4971364006                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   4971364006                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   4971364006                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   4971364006                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5726993                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      5726993                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5955582                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5955582                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       129417                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       129417                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       163616                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       163616                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       163545                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       163545                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11682575                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11682575                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11811992                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11811992                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031174                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031174                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.030844                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.030844                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.515821                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.515821                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064162                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064162                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.068318                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.068318                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.031006                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.031006                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036317                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.036317                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11981.415124                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11981.415124                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15418.649600                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15418.649600                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16777.100400                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16777.100400                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23395.582297                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13724.519307                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13724.519307                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11588.774342                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       286365                       # number of writebacks
system.cpu0.dcache.writebacks::total           286365                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         3418                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total         3418                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         2438                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total         2438                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data         5856                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total         5856                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data         5856                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total         5856                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       175114                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       175114                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       181255                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       181255                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        47050                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        47050                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        10498                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total        10498                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        11156                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        11156                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       356369                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       356369                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       403419                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       403419                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1737360745                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1737360745                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   2335118999                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2335118999                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    699675494                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    699675494                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    155125000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    155125000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    237977159                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    237977159                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1080000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1080000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   4072479744                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   4072479744                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   4772155238                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   4772155238                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1669232496                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1669232496                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030577                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030577                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.030434                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.030434                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.363553                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.363553                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064162                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064162                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.068214                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.068214                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030504                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.030504                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.034153                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.034153                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data  9921.312659                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total  9921.312659                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       1907557                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1767698                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        12543                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        12543                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       286363                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       331583                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        53089                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        23925                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp        60027                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           17                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           39                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       171374                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       163301                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side       753056                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      3449820                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side         6852                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        13348                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          4223076                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     23690016                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     48159078                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        19848                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total          71879022                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     631972                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      1656253                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.339000                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.473370                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           1094784     66.10%     66.10% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            561469     33.90%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       1656253                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1405252745                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy     72604500                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy    563408502                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1726182117                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      4332000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy      8386000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     6599972                       # DTB read hits
system.cpu1.dtb.read_misses                      3720                       # DTB read misses
system.cpu1.dtb.write_hits                    5539858                       # DTB write hits
system.cpu1.dtb.write_misses                     1581                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1672                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   123                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 6603692                       # DTB read accesses
system.cpu1.dtb.write_accesses                5541439                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         12139830                       # DTB hits
system.cpu1.dtb.misses                           5301                       # DTB misses
system.cpu1.dtb.accesses                     12145131                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    32728613                       # ITB inst hits
system.cpu1.itb.inst_misses                      2200                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1176                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                32730813                       # ITB inst accesses
system.cpu1.itb.hits                         32728613                       # DTB hits
system.cpu1.itb.misses                           2200                       # DTB misses
system.cpu1.itb.accesses                     32730813                       # DTB accesses
system.cpu1.numCycles                      5350361558                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   32086754                       # Number of instructions committed
system.cpu1.committedOps                     37934299                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             33961237                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  4436                       # Number of float alu accesses
system.cpu1.num_func_calls                     973285                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3888456                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    33961237                       # number of integer instructions
system.cpu1.num_fp_insts                         4436                       # number of float instructions
system.cpu1.num_int_register_reads           60527961                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          22681940                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                3022                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1416                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           134686779                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           15567897                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     12531559                       # number of memory refs
system.cpu1.num_load_insts                    6744563                       # Number of load instructions
system.cpu1.num_store_insts                   5786996                       # Number of store instructions
system.cpu1.num_idle_cycles              5182201093.372063                       # Number of idle cycles
system.cpu1.num_busy_cycles              168160464.627937                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.031430                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.968570                       # Percentage of idle cycles
system.cpu1.Branches                          5094014                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                12501      0.03%      0.03% # Class of executed instruction
system.cpu1.op_class::IntAlu                 25826807     67.22%     67.25% # Class of executed instruction
system.cpu1.op_class::IntMult                   50699      0.13%     67.38% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc               745      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.38% # Class of executed instruction
system.cpu1.op_class::MemRead                 6744563     17.55%     84.94% # Class of executed instruction
system.cpu1.op_class::MemWrite                5786996     15.06%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  38422311                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   40934                       # number of quiesce instructions executed
system.cpu1.icache.tags.replacements           375227                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.528279                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           32352870                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           375739                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            86.104636                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      79843888000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.528279                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973688                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973688                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         65832957                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        65832957                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     32352870                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       32352870                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     32352870                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        32352870                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     32352870                       # number of overall hits
system.cpu1.icache.overall_hits::total       32352870                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       375739                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       375739                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       375739                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        375739                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       375739                       # number of overall misses
system.cpu1.icache.overall_misses::total       375739                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   3159151510                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   3159151510                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   3159151510                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   3159151510                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   3159151510                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   3159151510                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     32728609                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     32728609                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     32728609                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     32728609                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     32728609                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     32728609                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011480                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011480                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011480                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011480                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011480                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011480                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8407.834987                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8407.834987                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8407.834987                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8407.834987                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8407.834987                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8407.834987                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       375739                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       375739                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       375739                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       375739                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       375739                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       375739                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2595414990                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   2595414990                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2595414990                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   2595414990                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2595414990                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   2595414990                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8511750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8511750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8511750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8511750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011480                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011480                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011480                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011480                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011480                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011480                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  6907.494271                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  6907.494271                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  6907.494271                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  6907.494271                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  6907.494271                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  6907.494271                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified      3539349                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       109722                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache      3291325                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher          217                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit           15                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued       138070                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page       329563                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements          122650                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15477.303394                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            769651                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs          138796                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            5.545196                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    2606454315500                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  5482.269126                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    12.040765                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.187836                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   603.787912                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2723.851785                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6655.165971                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.334611                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000735                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000011                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036852                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.166251                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.406199                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.944660                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         7087                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         9051                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           22                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           39                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          481                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4215                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         2330                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1744                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5747                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1414                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.432556                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.552429                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        16022455                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       16022455                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         6174                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2268                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       369218                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       169436                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        547096                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       225255                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       225255                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1340                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1340                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          885                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          885                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        86607                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        86607                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         6174                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2268                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       369218                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       256043                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         633703                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         6174                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2268                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       369218                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       256043                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        633703                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          268                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          169                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst         6377                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        56923                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        63737                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        20417                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        20417                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        12784                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        12784                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        23524                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        23524                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          268                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          169                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         6377                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        80447                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total        87261                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          268                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          169                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         6377                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        80447                       # number of overall misses
system.cpu1.l2cache.overall_misses::total        87261                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      5694000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      3369000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    191106990                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1462989443                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1663159433                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    341145571                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    341145571                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    259918262                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    259918262                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data       478999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total       478999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data    892976093                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total    892976093                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      5694000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      3369000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    191106990                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2355965536                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   2556135526                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      5694000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      3369000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    191106990                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2355965536                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   2556135526                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         6442                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2437                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       375595                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       226359                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       610833                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       225255                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       225255                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        21757                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        21757                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        13669                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        13669                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data       110131                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total       110131                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         6442                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2437                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       375595                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       336490                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       720964                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         6442                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2437                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       375595                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       336490                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       720964                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.041602                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.069348                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.016978                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.251472                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.104344                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.938411                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.938411                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.935255                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.935255                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.213600                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.213600                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.041602                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.069348                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.016978                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.239077                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.121034                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.041602                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.069348                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.016978                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.239077                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.121034                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21246.268657                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19934.911243                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29968.165281                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 25701.200622                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26094.096569                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16708.898026                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16708.898026                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20331.528630                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20331.528630                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 239499.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 239499.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37960.214802                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37960.214802                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21246.268657                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19934.911243                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29968.165281                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29285.934044                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29292.989148                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21246.268657                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19934.911243                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29968.165281                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29285.934044                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29292.989148                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          579                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              19                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    30.473684                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        66455                       # number of writebacks
system.cpu1.l2cache.writebacks::total           66455                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst          767                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data           80                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          847                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1344                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         1344                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst          767                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1424                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total         2191                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst          767                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1424                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total         2191                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          268                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          169                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst         5610                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        56843                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        62890                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       138069                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       138069                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        20417                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        20417                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        12784                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        12784                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        22180                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        22180                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          268                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          169                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         5610                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        79023                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total        85070                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          268                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          169                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         5610                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        79023                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       138069                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       223139                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      3817500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      2186000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    137414260                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data   1062900207                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1206317967                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   7048181570                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   7048181570                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    332046976                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    332046976                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    180785968                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    180785968                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       373999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       373999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data    591403879                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total    591403879                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      3817500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      2186000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    137414260                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   1654304086                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   1797721846                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      3817500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      2186000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    137414260                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   1654304086                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   7048181570                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   8845903416                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7648750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data  12231230753                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total  12238879503                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data  28539732155                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total  28539732155                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7648750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data  40770962908                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total  40778611658                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.041602                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.069348                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.014936                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.251119                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.102958                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.938411                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.938411                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.935255                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.935255                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.201397                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.201397                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.041602                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.069348                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014936                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.234845                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.117995                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.041602                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.069348                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014936                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.234845                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.309501                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 18698.875974                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 19181.395564                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20934.463207                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21132.265734                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           313601                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          474.302028                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           10949850                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           314113                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            34.859589                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      76456711000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.302028                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.926371                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.926371                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         22948274                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        22948274                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      6183420                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        6183420                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4558750                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4558750                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        19290                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        19290                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        77402                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        77402                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        75753                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        75753                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     10742170                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        10742170                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     10761460                       # number of overall hits
system.cpu1.dcache.overall_hits::total       10761460                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       187243                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       187243                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       134937                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       134937                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        43327                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        43327                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        12089                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        12089                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        13673                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        13673                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       322180                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        322180                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       365507                       # number of overall misses
system.cpu1.dcache.overall_misses::total       365507                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2299329756                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   2299329756                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2509975628                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2509975628                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    218034000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    218034000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    317344970                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    317344970                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       524000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total       524000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4809305384                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4809305384                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4809305384                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4809305384                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      6370663                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      6370663                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4693687                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4693687                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        62617                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        62617                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        89491                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        89491                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89426                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        89426                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     11064350                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     11064350                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     11126967                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     11126967                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.029391                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.029391                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028749                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.028749                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.691937                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.691937                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.135086                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.135086                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.152897                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.152897                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029119                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.029119                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032849                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.032849                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       225255                       # number of writebacks
system.cpu1.dcache.writebacks::total           225255                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          794                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          794                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data         3242                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total         3242                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data         4036                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total         4036                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data         4036                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total         4036                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       186449                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       186449                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       131695                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       131695                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        27821                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        27821                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12089                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12089                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        13671                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        13671                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       318144                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       318144                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       345965                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       345965                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1916001744                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1916001744                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2027549872                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2027549872                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    596503999                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    596503999                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    193851000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    193851000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    289002030                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    289002030                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       494000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       494000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3943551616                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3943551616                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4540055615                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4540055615                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  12848996742                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  12848996742                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  34213847345                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  34213847345                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data  47062844087                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total  47062844087                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029267                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029267                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028058                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028058                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.444304                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.444304                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.135086                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.135086                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.152875                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.152875                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028754                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028754                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031092                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.031092                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq        957719                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       715905                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq       756547                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp       756547                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       225255                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       189199                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        53977                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        23970                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        50977                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           26                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           39                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq       119927                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp       111476                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side       751552                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side      2675268                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6827                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        16819                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          3450466                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     24038516                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     40612602                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         9748                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        25768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          64686634                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     549743                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1492746                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.338347                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.473147                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5            987680     66.17%     66.17% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            505066     33.83%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1492746                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1514414783                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     42402999                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    563804260                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    984220768                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      4390000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy     10377250                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1782387791115                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------