path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.871820                       # Number of seconds simulated
sim_ticks                                2871819744000                       # Number of ticks simulated
final_tick                               2871819744000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 357244                       # Simulator instruction rate (inst/s)
host_op_rate                                   432116                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7805602288                       # Simulator tick rate (ticks/s)
host_mem_usage                                 614840                       # Number of bytes of host memory used
host_seconds                                   367.92                       # Real time elapsed on the host
sim_insts                                   131436334                       # Number of instructions simulated
sim_ops                                     158983282                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1155428                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1268388                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8606976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           151764                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           551380                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       345088                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12080624                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1155428                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       151764                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1307192                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8516928                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8534492                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26507                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20338                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134484                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2526                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              8636                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5392                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                197908                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          133077                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               137468                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              402333                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              441667                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      2997046                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               52846                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              191997                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       120164                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4206609                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         402333                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          52846                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             455179                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2965690                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6102                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2971806                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2965690                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             402333                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             447769                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      2997046                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              52846                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             192011                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       120164                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7178416                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        197908                       # Number of read requests accepted
system.physmem.writeReqs                       137468                       # Number of write requests accepted
system.physmem.readBursts                      197908                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     137468                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12655744                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10368                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8547392                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12080624                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8534492                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      162                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          64406                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11744                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11857                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11924                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11590                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20227                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11881                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12481                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12857                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12335                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12711                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11891                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11251                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11484                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11698                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10879                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10936                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8367                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8665                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8799                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8189                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7964                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8309                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8959                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8936                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8719                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9048                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8437                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8181                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8223                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7876                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7572                       # Per bank write bursts
system.physmem.perBankWrBursts::15               7309                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          22                       # Number of times write queue was full causing retry
system.physmem.totGap                    2871819304000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  188148                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 133077                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    139055                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     15611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8666                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6945                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5399                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4517                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3779                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3330                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        87                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7805                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8948                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10581                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9640                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8066                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6906                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       79                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        87485                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      242.362371                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     136.946957                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     304.393854                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46305     52.93%     52.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17523     20.03%     72.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6069      6.94%     79.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3389      3.87%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2483      2.84%     86.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1521      1.74%     88.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          858      0.98%     89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          952      1.09%     90.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8385      9.58%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          87485                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6517                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        30.342949                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      586.244331                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6515     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6517                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6517                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.493018                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.920871                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.293044                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5326     81.72%     81.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             466      7.15%     88.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              68      1.04%     89.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             161      2.47%     92.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              25      0.38%     92.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             129      1.98%     94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              31      0.48%     95.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              20      0.31%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              32      0.49%     96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              18      0.28%     96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.14%     96.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.11%     96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             150      2.30%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.09%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.11%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              24      0.37%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               5      0.08%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.06%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.05%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             3      0.05%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             3      0.05%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             9      0.14%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6517                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4471540489                       # Total ticks spent queuing
system.physmem.totMemAccLat                8179277989                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    988730000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       22612.55                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  41362.55                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.41                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.21                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.95                       # Average write queue length when enqueuing
system.physmem.readRowHits                     164996                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     78817                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.01                       # Row buffer hit rate for writes
system.physmem.avgGap                      8562983.95                       # Average gap between requests
system.physmem.pageHitRate                      73.59                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  341636400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  186408750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 815575800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                441858240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187573201920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            85932696690                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1647711485250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1923002863050                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.611581                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2740967841659                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95896320000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     34954258341                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  319750200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  174466875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 726835200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                423565200                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187573201920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85000293540                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1648529382750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1922747495685                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.522659                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2742335596201                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95896320000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     33587665799                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     8797                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                8797                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1607                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7190                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         8797                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           8797    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         8797                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         7279                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6527.254746                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767         7242     99.49%     99.49% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535           32      0.44%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839            3      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         7279                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1809726500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1809726500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5719     78.57%     78.57% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1560     21.43%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         7279                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8797                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8797                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7279                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7279                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        16076                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    25745693                       # DTB read hits
system.cpu0.dtb.read_misses                      7581                       # DTB read misses
system.cpu0.dtb.write_hits                   19246585                       # DTB write hits
system.cpu0.dtb.write_misses                     1216                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3751                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1856                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      321                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                25753274                       # DTB read accesses
system.cpu0.dtb.write_accesses               19247801                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         44992278                       # DTB hits
system.cpu0.dtb.misses                           8797                       # DTB misses
system.cpu0.dtb.accesses                     45001075                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3674                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3674                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          320                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3354                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3674                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3674    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3674                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6255.531301                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-16383         2268     88.04%     88.04% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-32767          277     10.75%     98.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-49151           28      1.09%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-180223            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2576                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1809154500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1809154500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2256     87.58%     87.58% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          320     12.42%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2576                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3674                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2576                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2576                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6250                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   121573780                       # ITB inst hits
system.cpu0.itb.inst_misses                      3674                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2371                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               121577454                       # ITB inst accesses
system.cpu0.itb.hits                        121573780                       # DTB hits
system.cpu0.itb.misses                           3674                       # DTB misses
system.cpu0.itb.accesses                    121577454                       # DTB accesses
system.cpu0.numCycles                      5743639488                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1907                       # number of quiesce instructions executed
system.cpu0.committedInsts                  117757184                       # Number of instructions committed
system.cpu0.committedOps                    142314769                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            125928094                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                 11483                       # Number of float alu accesses
system.cpu0.num_func_calls                   12772213                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     16007583                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   125928094                       # number of integer instructions
system.cpu0.num_fp_insts                        11483                       # number of float instructions
system.cpu0.num_int_register_reads          231704258                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          87445622                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                8771                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2716                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           515435615                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           53492348                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     46148278                       # number of memory refs
system.cpu0.num_load_insts                   26004695                       # Number of load instructions
system.cpu0.num_store_insts                  20143583                       # Number of store instructions
system.cpu0.num_idle_cycles              5456012961.442100                       # Number of idle cycles
system.cpu0.num_busy_cycles              287626526.557900                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.050077                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.949923                       # Percentage of idle cycles
system.cpu0.Branches                         29545337                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2315      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 99836654     68.33%     68.33% # Class of executed instruction
system.cpu0.op_class::IntMult                  112117      0.08%     68.41% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8321      0.01%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.41% # Class of executed instruction
system.cpu0.op_class::MemRead                26004695     17.80%     86.21% # Class of executed instruction
system.cpu0.op_class::MemWrite               20143583     13.79%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 146107685                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           732170                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          488.694805                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           44080957                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           732682                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            60.163832                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1836359000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   488.694805                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.954482                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.954482                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         90660887                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        90660887                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     24440244                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       24440244                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     18493380                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18493380                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       326498                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       326498                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374202                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       374202                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371573                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       371573                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     42933624                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        42933624                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     43260122                       # number of overall hits
system.cpu0.dcache.overall_hits::total       43260122                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       418073                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       418073                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       337261                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       337261                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133156                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       133156                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22252                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22252                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19918                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        19918                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       755334                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        755334                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       888490                       # number of overall misses
system.cpu0.dcache.overall_misses::total       888490                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5661692500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5661692500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6946372000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   6946372000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    344716000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    344716000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    507189500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    507189500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1629000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1629000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  12608064500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  12608064500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  12608064500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  12608064500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     24858317                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     24858317                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     18830641                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     18830641                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       459654                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       459654                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396454                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       396454                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391491                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       391491                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     43688958                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     43688958                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     44148612                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     44148612                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016818                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.016818                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017910                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017910                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.289687                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.289687                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056128                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056128                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050877                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050877                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017289                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.017289                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020125                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.020125                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13542.353847                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13542.353847                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20596.428286                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20596.428286                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15491.461442                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15491.461442                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25463.876895                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25463.876895                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       732170                       # number of writebacks
system.cpu0.dcache.writebacks::total           732170                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25278                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25278                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15552                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15552                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25279                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25279                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25279                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25279                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       392795                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       392795                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337260                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       337260                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106103                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       106103                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6700                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6700                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19918                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        19918                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       730055                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       730055                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       836158                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       836158                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31819                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31819                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60318                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60318                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4839458000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4839458000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6609064500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6609064500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1736821000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1736821000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104360500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104360500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    487321500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    487321500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1579000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1579000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11448522500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  11448522500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13185343500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  13185343500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6629856000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6629856000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5400865000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5400865000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12030721000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12030721000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015801                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015801                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017910                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017910                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230832                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230832                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016900                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016900                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050877                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050877                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016710                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016710                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018940                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018940                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199454.905667                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199454.905667                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1146899                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.321434                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          120426360                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1147411                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs           104.954859                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      14862010000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321434                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998675                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998675                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        244294980                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       244294980                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    120426360                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      120426360                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    120426360                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       120426360                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    120426360                       # number of overall hits
system.cpu0.icache.overall_hits::total      120426360                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1147420                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1147420                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1147420                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1147420                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1147420                       # number of overall misses
system.cpu0.icache.overall_misses::total      1147420                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12257879000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  12257879000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  12257879000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  12257879000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  12257879000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  12257879000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    121573780                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    121573780                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    121573780                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    121573780                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    121573780                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    121573780                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009438                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.009438                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009438                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.009438                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009438                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.009438                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10682.992278                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10682.992278                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1146899                       # number of writebacks
system.cpu0.icache.writebacks::total          1146899                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1147420                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1147420                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1147420                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1147420                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1147420                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1147420                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11684169000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11684169000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11684169000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11684169000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11684169000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11684169000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1253876500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1253876500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009438                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009438                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009438                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009438                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009438                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009438                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10182.992278                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10182.992278                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10182.992278                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10182.992278                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10182.992278                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10182.992278                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1935560                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1935650                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit           78                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       245750                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          273082                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16075.027062                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           3061877                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          289178                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           10.588209                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 14584.410184                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.385544                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.137322                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1488.094013                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.890162                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000146                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.090826                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.981142                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1066                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15022                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          271                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          320                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          458                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3316                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7592                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3838                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.065063                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.916870                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        62794753                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       62794753                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10867                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4767                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         15634                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       501313                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       501313                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1348863                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1348863                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       238469                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       238469                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1100555                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1100555                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       411293                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       411293                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10867                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4767                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1100555                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       649762                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1765951                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        10867                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4767                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1100555                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       649762                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1765951                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          177                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           76                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          253                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55141                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        55141                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19907                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        19907                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           11                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total           11                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43650                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        43650                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        46865                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        46865                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94305                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total        94305                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          177                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker           76                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        46865                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       137955                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       185073                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          177                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker           76                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        46865                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       137955                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       185073                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4896500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2045000                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total      6941500                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    165758000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    165758000                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     42773000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     42773000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1499992                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1499992                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2791235000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   2791235000                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3308401000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3308401000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3237666000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3237666000                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4896500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2045000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3308401000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   6028901000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   9344243500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4896500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2045000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3308401000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   6028901000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   9344243500                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        11044                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4843                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        15887                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       501313                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       501313                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1348863                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1348863                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55141                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        55141                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19907                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19907                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           11                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           11                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       282119                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       282119                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1147420                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1147420                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       505598                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       505598                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        11044                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4843                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1147420                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       787717                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1951024                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        11044                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4843                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1147420                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       787717                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1951024                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.016027                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.015693                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.015925                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154722                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154722                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040844                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040844                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186522                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186522                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.016027                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.015693                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040844                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.175133                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.094859                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.016027                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.015693                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040844                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.175133                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.094859                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27663.841808                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26907.894737                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27436.758893                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3006.075334                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3006.075334                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2148.641181                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2148.641181                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 136362.909091                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 136362.909091                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63945.819015                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63945.819015                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 70594.281447                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 70594.281447                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34331.859392                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34331.859392                       # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27663.841808                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26907.894737                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 70594.281447                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43701.939038                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 50489.501440                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27663.841808                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26907.894737                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 70594.281447                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43701.939038                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 50489.501440                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       231742                       # number of writebacks
system.cpu0.l2cache.writebacks::total          231742                       # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1776                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1776                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           53                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           53                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1829                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1829                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1829                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1829                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          177                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           76                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total          253                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       265136                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       265136                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55141                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55141                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19907                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19907                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           11                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           11                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41874                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        41874                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46865                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46865                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94252                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94252                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          177                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           76                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        46865                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136126                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       183244                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          177                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           76                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46865                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136126                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       265136                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       448380                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31819                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40841                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60318                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69340                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3834500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1589000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5423500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20369501795                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20369501795                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1428543500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1428543500                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    338252500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    338252500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1199992                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1199992                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2362760500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2362760500                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3027211000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3027211000                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2665459000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2665459000                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3834500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1589000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3027211000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5028219500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   8060854000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3834500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1589000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3027211000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5028219500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20369501795                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  28430355795                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6374890500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7561102000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5187001000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5187001000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11561891500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12748103000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.016027                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015693                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.015925                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148427                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148427                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040844                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040844                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186417                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.186417                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.016027                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015693                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040844                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.172811                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093922                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.016027                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015693                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040844                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.172811                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229818                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.snoop_filter.tot_requests      3903345                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1968246                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        28892                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       321222                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       317069                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4153                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq         63874                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1765403                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       733576                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1348863                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict       190188                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       312390                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        85764                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42077                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112758                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           84                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       301102                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       297729                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1147420                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       574776                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq         3316                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3438002                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2673168                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11871                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27031                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          6150072                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    145478520                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    101119646                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        19372                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        44176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         246661714                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     988213                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      2981714                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.123543                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.333265                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           2617497     87.78%     87.78% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            360064     12.08%     99.86% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              4153      0.14%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2981714                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    3884130992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115184885                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1730152000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1265237983                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      7028000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     15993487                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     2355                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                2355                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          481                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1874                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         2355                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           2355    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         2355                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1709                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  5695.537695                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         1565     91.57%     91.57% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767          135      7.90%     99.47% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-49151            5      0.29%     99.77% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.18%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1709                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1207257828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1207257828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1207257828                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1228     71.85%     71.85% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          481     28.15%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1709                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2355                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2355                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1709                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1709                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         4064                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     3323284                       # DTB read hits
system.cpu1.dtb.read_misses                      1962                       # DTB read misses
system.cpu1.dtb.write_hits                    2909831                       # DTB write hits
system.cpu1.dtb.write_misses                      393                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1652                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   231                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      124                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 3325246                       # DTB read accesses
system.cpu1.dtb.write_accesses                2910224                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          6233115                       # DTB hits
system.cpu1.dtb.misses                           2355                       # DTB misses
system.cpu1.dtb.accesses                      6235470                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1376                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1376                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          134                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1242                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1376                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1376    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1376                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          819                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5169.477869                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          116     14.16%     14.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287          583     71.18%     85.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383           72      8.79%     94.14% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            8      0.98%     95.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.12%     95.24% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           22      2.69%     97.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767            7      0.85%     98.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     98.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.61%     99.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.63% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247            3      0.37%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          819                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples  -1208095828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1208095828    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1208095828                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          685     83.64%     83.64% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          134     16.36%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          819                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1376                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1376                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          819                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          819                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2195                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    13877832                       # ITB inst hits
system.cpu1.itb.inst_misses                      1376                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     883                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                13879208                       # ITB inst accesses
system.cpu1.itb.hits                         13877832                       # DTB hits
system.cpu1.itb.misses                           1376                       # DTB misses
system.cpu1.itb.accesses                     13879208                       # DTB accesses
system.cpu1.numCycles                      5742698802                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2717                       # number of quiesce instructions executed
system.cpu1.committedInsts                   13679150                       # Number of instructions committed
system.cpu1.committedOps                     16668513                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             15113644                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
system.cpu1.num_func_calls                     913162                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      1492467                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    15113644                       # number of integer instructions
system.cpu1.num_fp_insts                            0                       # number of float instructions
system.cpu1.num_int_register_reads           27463830                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          10666857                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            61159895                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            5174219                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      6447631                       # number of memory refs
system.cpu1.num_load_insts                    3428751                       # Number of load instructions
system.cpu1.num_store_insts                   3018880                       # Number of store instructions
system.cpu1.num_idle_cycles              5696160545.959164                       # Number of idle cycles
system.cpu1.num_busy_cycles              46538256.040836                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.008104                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.991896                       # Percentage of idle cycles
system.cpu1.Branches                          2456488                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   24      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 10511910     61.88%     61.88% # Class of executed instruction
system.cpu1.op_class::IntMult                   24272      0.14%     62.03% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.03% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3188      0.02%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.04% # Class of executed instruction
system.cpu1.op_class::MemRead                 3428751     20.18%     82.23% # Class of executed instruction
system.cpu1.op_class::MemWrite                3018880     17.77%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  16987025                       # Class of executed instruction
system.cpu1.dcache.tags.replacements           147592                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          468.392474                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs            6004450                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           147942                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            40.586514                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     106294932000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   468.392474                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.914829                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.914829                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          318                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.683594                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         12646180                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        12646180                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      3055213                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        3055213                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      2743263                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       2743263                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41902                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        41902                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69872                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        69872                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61606                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        61606                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data      5798476                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         5798476                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data      5840378                       # number of overall hits
system.cpu1.dcache.overall_hits::total        5840378                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       112221                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       112221                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        79294                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        79294                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24421                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        24421                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16601                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        16601                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23085                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23085                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       191515                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        191515                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       215936                       # number of overall misses
system.cpu1.dcache.overall_misses::total       215936                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1751790500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1751790500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2724343500                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2724343500                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    320772500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    320772500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    629240500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    629240500                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3762500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3762500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4476134000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4476134000                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4476134000                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4476134000                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      3167434                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      3167434                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      2822557                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      2822557                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66323                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        66323                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86473                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        86473                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84691                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        84691                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data      5989991                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      5989991                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data      6056314                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      6056314                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035430                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035430                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028093                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.028093                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.368213                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.368213                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.191979                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.191979                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.272579                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.272579                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031973                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031973                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035655                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035655                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15610.184368                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15610.184368                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34357.498676                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34357.498676                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19322.480573                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19322.480573                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27257.548191                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27257.548191                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       147592                       # number of writebacks
system.cpu1.dcache.writebacks::total           147592                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          221                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          221                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11676                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11676                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          221                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          221                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          221                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       112000                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       112000                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79294                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        79294                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23950                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        23950                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4925                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4925                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23085                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23085                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       191294                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       191294                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       215244                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       215244                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3081                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5504                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5504                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1626671000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1626671000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2645049500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2645049500                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    437326000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    437326000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90573500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90573500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    606189500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    606189500                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3728500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3728500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4271720500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   4271720500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4709046500                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4709046500                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    439448500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    439448500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    303112500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    303112500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    742561000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    742561000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035360                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035360                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028093                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028093                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.361112                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.361112                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056954                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056954                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.272579                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.272579                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031936                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.031936                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035540                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.035540                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22330.655954                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22330.655954                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21877.713200                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21877.713200                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142631.775398                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142631.775398                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125098.018985                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125098.018985                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134912.972384                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134912.972384                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           463636                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.311121                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           13413679                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           464148                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            28.899573                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     106195496500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.311121                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973264                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973264                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         28219802                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        28219802                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     13413679                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       13413679                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     13413679                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        13413679                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     13413679                       # number of overall hits
system.cpu1.icache.overall_hits::total       13413679                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       464148                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       464148                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       464148                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        464148                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       464148                       # number of overall misses
system.cpu1.icache.overall_misses::total       464148                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4215419500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4215419500                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4215419500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4215419500                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4215419500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4215419500                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     13877827                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     13877827                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     13877827                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     13877827                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     13877827                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     13877827                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033445                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.033445                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033445                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.033445                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033445                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.033445                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9082.058955                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  9082.058955                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9082.058955                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  9082.058955                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9082.058955                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  9082.058955                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.writebacks::writebacks       463636                       # number of writebacks
system.cpu1.icache.writebacks::total           463636                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       464148                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       464148                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       464148                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       464148                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       464148                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       464148                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3983345500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3983345500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3983345500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3983345500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3983345500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3983345500                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     23546500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     23546500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033445                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033445                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033445                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.033445                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033445                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.033445                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8582.058955                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8582.058955                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8582.058955                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  8582.058955                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8582.058955                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  8582.058955                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       118070                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       118078                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        50218                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           30957                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       14956.632857                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1041724                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           46098                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           22.598030                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14500.509333                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     1.321768                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.084166                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   452.717591                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.885041                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000081                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027632                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.912880                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          931                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           37                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14173                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           38                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          891                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1648                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12129                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.056824                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002258                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.865051                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        21133576                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       21133576                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2455                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1470                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          3925                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks        91545                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total        91545                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       509576                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       509576                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18096                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        18096                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       455478                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       455478                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        77072                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        77072                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2455                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1470                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       455478                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data        95168                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         554571                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2455                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1470                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       455478                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data        95168                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        554571                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          345                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          297                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          642                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28981                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28981                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23084                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        23084                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32217                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        32217                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst         8670                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total         8670                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        63803                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        63803                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          345                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          297                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst         8670                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data        96020                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       105332                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          345                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          297                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst         8670                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data        96020                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       105332                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      7035000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5940500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total     12975500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     66105500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total     66105500                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     54747500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     54747500                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3677500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3677500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1649546500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1649546500                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    528187000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total    528187000                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1437865000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1437865000                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      7035000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5940500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    528187000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   3087411500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3628574000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      7035000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5940500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    528187000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   3087411500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3628574000                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         2800                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1767                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         4567                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks        91545                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total        91545                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       509576                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       509576                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28981                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        28981                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23084                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23084                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50313                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        50313                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       464148                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       464148                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       140875                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       140875                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         2800                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1767                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       464148                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       191188                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       659903                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         2800                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1767                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       464148                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       191188                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       659903                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.123214                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.168081                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.140574                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.640332                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.640332                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018679                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018679                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.452905                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.452905                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.123214                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.168081                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018679                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.502228                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.159617                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.123214                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.168081                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018679                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.502228                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.159617                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20391.304348                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20001.683502                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20211.059190                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2280.994445                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2280.994445                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2371.664356                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2371.664356                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3677500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3677500                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51201.120526                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51201.120526                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60921.222607                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60921.222607                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22536.009279                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22536.009279                       # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20391.304348                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20001.683502                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60921.222607                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32153.837742                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34448.923404                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20391.304348                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20001.683502                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60921.222607                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32153.837742                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34448.923404                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        25761                       # number of writebacks
system.cpu1.l2cache.writebacks::total           25761                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           70                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           70                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           70                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           70                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           70                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          345                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          297                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total          642                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20837                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        20837                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28981                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28981                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23084                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23084                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32147                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        32147                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst         8670                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8670                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63803                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        63803                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          345                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          297                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         8670                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data        95950                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       105262                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          345                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          297                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         8670                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data        95950                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        20837                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       126099                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3258                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2423                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5504                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5681                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4965000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4158500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9123500                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    915724625                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    915724625                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    582445000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    582445000                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    432971000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    432971000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3473500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3473500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1449025500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1449025500                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    476167000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    476167000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1055047000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1055047000                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4965000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4158500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    476167000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2504072500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2989363000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4965000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4158500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    476167000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2504072500                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    915724625                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3905087625                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    414452000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    436671000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    284931500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    284931500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    699383500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    721602500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.123214                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.168081                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.140574                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.638940                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.638940                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018679                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018679                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.452905                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452905                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.123214                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.168081                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018679                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.501862                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159511                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.123214                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.168081                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018679                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.501862                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191087                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14211.059190                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43947.047320                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20097.477658                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.477658                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18756.324727                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      3473500                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      3473500                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.snoop_filter.tot_requests      1323663                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       668360                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10107                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       169443                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       166760                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2683                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         10105                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       652363                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2423                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2423                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       118404                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       509576                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict        86260                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        25020                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        70278                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40907                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        84739                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           84                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        57602                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        55059                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       464148                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       215012                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq           32                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1383984                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       718041                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4385                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7029                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2113439                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     58847556                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24276952                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7068                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          83142776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     355785                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples       998697                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.187513                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.397146                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0            814111     81.52%     81.52% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            181903     18.21%     99.73% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              2683      0.27%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total        998697                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy    1278018500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     79432929                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    696399000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    317143500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      2618000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      4229000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31021                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31021                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             48741500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                32500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                93000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               609500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               23500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               48500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2500                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6155500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              165000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32044000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              119500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186329030                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               37500                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36461                       # number of replacements
system.iocache.tags.tagsinuse               14.380003                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36477                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         290757542000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.380003                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.898750                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.898750                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          255                       # number of overall misses
system.iocache.overall_misses::total              255                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     32882376                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     32882376                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4738851654                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4738851654                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     32882376                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     32882376                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     32882376                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     32882376                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128950.494118                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128950.494118                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128950.494118                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128950.494118                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128950.494118                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           818                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   99                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.262626                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36206                       # number of writebacks
system.iocache.writebacks::total                36206                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     20132376                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     20132376                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2927651654                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2927651654                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     20132376                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     20132376                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     20132376                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     20132376                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 78950.494118                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 78950.494118                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   123906                       # number of replacements
system.l2c.tags.tagsinuse                62994.829806                       # Cycle average of tags in use
system.l2c.tags.total_refs                     421817                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   187980                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.243946                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   13459.681359                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.946988                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.042686                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7381.464495                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2783.395152                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954481                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1451.828957                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      405.858901                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1734.111238                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.205378                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.112632                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042471                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.545876                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.022153                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.006193                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.026460                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.961225                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        31889                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        32181                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          315                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         5132                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        26438                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          384                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         2392                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29385                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.486588                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.491043                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5837673                       # Number of tag accesses
system.l2c.tags.data_accesses                 5837673                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       257503                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          257503                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           32214                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1943                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               34157                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          2130                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           884                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total              3014                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             4062                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1324                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5386                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           98                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           71                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        29368                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        46989                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        47574                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           22                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           20                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst         6299                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data         4989                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3377                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           138807                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker            98                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            71                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               29368                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               51051                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        47574                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            22                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            20                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst                6299                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data                6313                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         3377                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  144193                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           98                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           71                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              29368                       # number of overall hits
system.l2c.overall_hits::cpu0.data              51051                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        47574                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           22                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           20                       # number of overall hits
system.l2c.overall_hits::cpu1.inst               6299                       # number of overall hits
system.l2c.overall_hits::cpu1.data               6313                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         3377                       # number of overall hits
system.l2c.overall_hits::total                 144193                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9379                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2248                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11627                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          589                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1277                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1866                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11187                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           7836                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19023                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        17497                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         8847                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       134641                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2371                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data          788                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher         5392                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         169546                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17497                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20034                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       134641                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2371                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              8624                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5392                       # number of demand (read+write) misses
system.l2c.demand_misses::total                188569                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17497                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20034                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       134641                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2371                       # number of overall misses
system.l2c.overall_misses::cpu1.data             8624                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5392                       # number of overall misses
system.l2c.overall_misses::total               188569                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data     29891000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      5943500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     35834500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      4589000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      1770500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      6359500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   1626887000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1026108000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2652995000                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker       948500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker       272000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   2300069500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data   1205085500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  19535280293                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker       132500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst    317997500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    116823500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher    839508015                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  24316117308                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       948500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       272000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2300069500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   2831972500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  19535280293                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       132500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    317997500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1142931500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    839508015                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     26969112308                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       948500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       272000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2300069500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   2831972500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19535280293                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       132500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    317997500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1142931500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    839508015                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    26969112308                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks       257503                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       257503                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        41593                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4191                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45784                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         2719                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         2161                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          4880                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15249                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data         9160                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            24409                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          105                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           73                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        46865                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        55836                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       182215                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           23                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           20                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst         8670                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data         5777                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8769                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       308353                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker          105                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           73                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           46865                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           71085                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       182215                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           23                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           20                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst            8670                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           14937                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8769                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              332762                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker          105                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           73                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          46865                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          71085                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       182215                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           23                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           20                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst           8670                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          14937                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8769                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             332762                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.225495                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.536387                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.253953                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.216624                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590930                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.382377                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.733622                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.855459                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.779344                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.066667                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.373349                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.158446                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.043478                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.273472                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.136403                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.549844                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.066667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.373349                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.281832                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.043478                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.273472                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.577358                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.566678                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.066667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.373349                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.281832                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.043478                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.273472                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.577358                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.566678                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3187.013541                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2643.905694                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  3082.007397                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7791.171477                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1386.452623                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  3408.092176                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145426.566550                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130947.932619                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 139462.492772                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       135500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       136000                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131455.078013                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136214.027354                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       132500                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134119.569802                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 148253.172589                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 143418.997251                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 131455.078013                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 141358.315863                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 134119.569802                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 132529.162801                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 143019.861738                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       135500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 131455.078013                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 141358.315863                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 134119.569802                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 132529.162801                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 143019.861738                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               96871                       # number of writebacks
system.l2c.writebacks::total                    96871                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           15                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 15                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         2791                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         2791                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         9379                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2248                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11627                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          589                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1277                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1866                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11187                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         7836                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19023                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        17492                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         8847                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       134641                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst         2361                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data          788                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher         5392                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       169531                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17492                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20034                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134641                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2361                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         8624                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5392                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           188554                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17492                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20034                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134641                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2361                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         8624                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5392                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          188554                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        31819                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         3078                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        44096                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        30922                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        60318                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         5501                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        75018                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    706950000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    168753500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    875703500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     45541000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     97962500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    143503500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   1515017000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    947748000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   2462765000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker       878500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker       252000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   2124790500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   1116615500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  18188870293                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst    293429500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    108943500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher    785588015                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  22619490308                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       878500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       252000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2124790500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   2631632500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  18188870293                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    293429500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1056691500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    785588015                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  25082255308                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       878500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       252000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2124790500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   2631632500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18188870293                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    293429500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1056691500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    785588015                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  25082255308                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5802133000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    358998500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7203979000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4702508000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    243698500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4946206500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10504641000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    602697000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12150185500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.225495                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.536387                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.253953                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.216624                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590930                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.382377                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.733622                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.855459                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.779344                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.066667                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.373242                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158446                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.043478                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.272318                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.136403                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.549795                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.066667                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.373242                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.281832                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.043478                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.272318                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.577358                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.566633                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.066667                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.373242                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.281832                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.043478                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.272318                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.577358                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.566633                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       125500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 133024.254633                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 133024.254633                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               44096                       # Transaction distribution
system.membus.trans_dist::ReadResp             213882                       # Transaction distribution
system.membus.trans_dist::WriteReq              30922                       # Transaction distribution
system.membus.trans_dist::WriteResp             30922                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       133077                       # Transaction distribution
system.membus.trans_dist::CleanEvict            14603                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            73616                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          39905                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13581                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            8                       # Transaction distribution
system.membus.trans_dist::ReadExReq             39514                       # Transaction distribution
system.membus.trans_dist::ReadExResp            18935                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        169786                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13766                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664049                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       785783                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108937                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108937                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 894720                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27532                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18296972                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18487386                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20805530                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           121102                       # Total snoops (count)
system.membus.snoop_fanout::samples            582015                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  582015    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              582015                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88274000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11368000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           966740692                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1134075509                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64085297                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       961177                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       518872                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       139554                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          20662                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        19793                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          869                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              44099                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            468456                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30922                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30922                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       390602                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           84323                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          107685                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         42919                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         150604                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           84                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           84                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            50476                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           50476                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       424372                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1224412                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       249093                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1473505                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34296330                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3743120                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               38039450                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          438983                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           897187                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.337621                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.474943                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 595147     66.33%     66.33% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 301171     33.57%     99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    869      0.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             897187                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          864296758                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           360622                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         647366860                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         201908331                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------