path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.194312                       # Number of seconds simulated
sim_ticks                                1194312178000                       # Number of ticks simulated
final_tick                               1194312178000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 475403                       # Simulator instruction rate (inst/s)
host_op_rate                                   567868                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9241250441                       # Simulator tick rate (ticks/s)
host_mem_usage                                 438040                       # Number of bytes of host memory used
host_seconds                                   129.24                       # Real time elapsed on the host
sim_insts                                    61439698                       # Number of instructions simulated
sim_ops                                      73389630                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           393932                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4710012                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           323460                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4796088                       # Number of bytes read from this memory
system.physmem.bytes_read::total             62128516                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       393932                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       323460                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          717392                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4097216                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7124560                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             12383                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             73653                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              5145                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             74957                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               6654210                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           64019                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               820855                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        43459753                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              329840                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3943703                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              270834                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             4015774                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52020332                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         329840                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         270834                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             600674                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3430607                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data              14234                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data            2520567                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5965408                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3430607                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       43459753                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             329840                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3957937                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             270834                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            6536341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               57985740                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       6654210                       # Number of read requests accepted
system.physmem.writeReqs                       820855                       # Number of write requests accepted
system.physmem.readBursts                     6654210                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     820855                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                425838464                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     30976                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7136448                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  62128516                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7124560                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      484                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  709321                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          12079                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              415236                       # Per bank write bursts
system.physmem.perBankRdBursts::1              415218                       # Per bank write bursts
system.physmem.perBankRdBursts::2              415240                       # Per bank write bursts
system.physmem.perBankRdBursts::3              415658                       # Per bank write bursts
system.physmem.perBankRdBursts::4              422402                       # Per bank write bursts
system.physmem.perBankRdBursts::5              415506                       # Per bank write bursts
system.physmem.perBankRdBursts::6              415779                       # Per bank write bursts
system.physmem.perBankRdBursts::7              415682                       # Per bank write bursts
system.physmem.perBankRdBursts::8              416047                       # Per bank write bursts
system.physmem.perBankRdBursts::9              415577                       # Per bank write bursts
system.physmem.perBankRdBursts::10             415398                       # Per bank write bursts
system.physmem.perBankRdBursts::11             414862                       # Per bank write bursts
system.physmem.perBankRdBursts::12             415007                       # Per bank write bursts
system.physmem.perBankRdBursts::13             415552                       # Per bank write bursts
system.physmem.perBankRdBursts::14             415496                       # Per bank write bursts
system.physmem.perBankRdBursts::15             415066                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6763                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6728                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6819                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7055                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7301                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7028                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7316                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7231                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7485                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7107                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7000                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6549                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6696                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6902                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6960                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6567                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    1194307723500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    6799                       # Read request sizes (log2)
system.physmem.readPktSize::3                 6488089                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  159322                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  64019                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    572550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    410650                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    412558                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    460055                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                    417389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                    445707                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   1151151                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                   1116358                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                   1442650                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     62467                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    48974                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    44870                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    43130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     8689                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     8270                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     8147                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3903                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6491                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6488                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       473292                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      914.815615                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     785.169464                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     288.643252                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          25022      5.29%      5.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        21566      4.56%      9.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5869      1.24%     11.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2391      0.51%     11.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2344      0.50%     12.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1629      0.34%     12.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4093      0.86%     13.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          899      0.19%     13.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       409479     86.52%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         473292                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6481                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean      1026.648974                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev    26505.494009                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-65535          6473     99.88%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143            3      0.05%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6481                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6481                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.205215                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.176618                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.984217                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2581     39.82%     39.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 15      0.23%     40.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               3862     59.59%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 20      0.31%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  3      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6481                       # Writes before turning the bus around for reads
system.physmem.totQLat                   170730095750                       # Total ticks spent queuing
system.physmem.totMemAccLat              295487458250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  33268630000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25659.32                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44409.32                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         356.56                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           5.98                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       52.02                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        5.97                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.83                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.79                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         4.36                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.98                       # Average write queue length when enqueuing
system.physmem.readRowHits                    6199598                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     92343                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   93.17                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  82.79                       # Row buffer hit rate for writes
system.physmem.avgGap                       159772.22                       # Average gap between requests
system.physmem.pageHitRate                      93.00                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     945808643750                       # Time in different power states
system.physmem.memoryStateTime::REF       39880620000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      208620525000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               57                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           57                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     60005732                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq             7703348                       # Transaction distribution
system.membus.trans_dist::ReadResp            7703348                       # Transaction distribution
system.membus.trans_dist::WriteReq             767581                       # Transaction distribution
system.membus.trans_dist::WriteResp            767581                       # Transaction distribution
system.membus.trans_dist::Writeback             64019                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            31325                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          17234                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           12079                       # Transaction distribution
system.membus.trans_dist::ReadExReq            137481                       # Transaction distribution
system.membus.trans_dist::ReadExResp           137066                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382642                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          906                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1971036                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4364934                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               17341062                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389989                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1812                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17348564                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total     19761065                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            71665577                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               71665577                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1224785500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             9231500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy              778500                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy          9212282000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         5079172023                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
system.membus.respLayer2.occupancy        16050388750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    69203                       # number of replacements
system.l2c.tags.tagsinuse                52959.316379                       # Cycle average of tags in use
system.l2c.tags.total_refs                    1672724                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   134375                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    12.448179                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   40136.915421                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000411                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001544                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3716.167205                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4233.542603                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.741623                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001622                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2809.362324                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2060.583626                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.612441                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.056704                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.064599                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000042                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.042867                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.031442                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.808095                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1911                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8176                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55031                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 17204185                       # Number of tag accesses
system.l2c.tags.data_accesses                17204185                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         3944                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         1786                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             419390                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             205855                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5333                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         1846                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             464270                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             143434                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1245858                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          570720                       # number of Writeback hits
system.l2c.Writeback_hits::total               570720                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            1291                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             523                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                1814                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           214                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            97                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               311                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            56339                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            52717                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109056                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          3944                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          1786                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              419390                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              262194                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5333                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          1846                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              464270                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              196151                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1354914                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         3944                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         1786                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             419390                       # number of overall hits
system.l2c.overall_hits::cpu0.data             262194                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5333                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         1846                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             464270                       # number of overall hits
system.l2c.overall_hits::cpu1.data             196151                       # number of overall hits
system.l2c.overall_hits::total                1354914                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             5741                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             7844                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             5048                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data             3616                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                22257                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          4858                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3744                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              8602                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          567                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          472                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1039                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          67076                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72428                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             139504                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              5741                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             74920                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              5048                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             76044                       # number of demand (read+write) misses
system.l2c.demand_misses::total                161761                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             5741                       # number of overall misses
system.l2c.overall_misses::cpu0.data            74920                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             5048                       # number of overall misses
system.l2c.overall_misses::cpu1.data            76044                       # number of overall misses
system.l2c.overall_misses::total               161761                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        32000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    405931250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    580562999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       320500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    360408000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data    277006500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1624485749                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     12826446                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     12064984                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     24891430                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1764424                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2465394                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      4229818                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4470263914                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5223424391                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9693688305                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker        32000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    405931250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   5050826913                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       320500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    360408000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   5500430891                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     11318174054                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker        32000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    405931250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   5050826913                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       320500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    360408000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   5500430891                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    11318174054                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         3945                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         1788                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         425131                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         213699                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5337                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         1847                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         469318                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         147050                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1268115                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       570720                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           570720                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         6149                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         4267                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           10416                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          781                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data          569                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1350                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       123415                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       125145                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           248560                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         3945                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         1788                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          425131                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          337114                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5337                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         1847                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          469318                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          272195                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1516675                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         3945                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         1788                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         425131                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         337114                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5337                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         1847                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         469318                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         272195                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1516675                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000253                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001119                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.013504                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.036706                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000749                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000541                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.010756                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.024590                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.017551                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.790047                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.877431                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.825845                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.725992                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.829525                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.769630                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.543500                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.578753                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.561249                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000253                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.001119                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.013504                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.222239                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000749                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.010756                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.279373                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.106655                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000253                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.001119                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.013504                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.222239                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000749                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.010756                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.279373                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.106655                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        32000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70707.411601                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 74013.640872                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        80125                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71396.196513                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76605.779867                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 72987.633059                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2640.272952                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3222.485043                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  2893.679377                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3111.858907                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5223.292373                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4071.047161                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66644.759884                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72118.854462                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69486.812600                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 70707.411601                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 67416.269527                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        80125                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 71396.196513                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 72332.214126                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69968.497067                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 70707.411601                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 67416.269527                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        80125                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 71396.196513                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 72332.214126                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69968.497067                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               64019                       # number of writebacks
system.l2c.writebacks::total                    64019                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         5740                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         7844                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         5048                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data         3616                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           22256                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         4858                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         3744                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         8602                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          567                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          472                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1039                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        67076                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72428                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        139504                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         5740                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        74920                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         5048                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        76044                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           161760                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         5740                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        74920                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         5048                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        76044                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          161760                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    333147000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    482688999                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       270000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    296491000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data    231948000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1344752499                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     48613352                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     37517733                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     86131085                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5678567                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4724471                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     10403038                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3605327074                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4301754105                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   7907081179                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    333147000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4088016073                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       270000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    296491000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   4533702105                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   9251833678                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    333147000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4088016073                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       270000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    296491000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   4533702105                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   9251833678                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    350592250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12457114749                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5367250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154289145498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167102219747                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1046762999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15721978412                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  16768741411                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    350592250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13503877748                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5367250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170011123910                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183870961158                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000253                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001119                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013502                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036706                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000749                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000541                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010756                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024590                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.017550                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.790047                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.877431                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.825845                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.725992                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.829525                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.769630                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.543500                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.578753                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.561249                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000253                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001119                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013502                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.222239                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000749                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000541                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010756                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.279373                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.106654                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000253                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001119                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013502                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.222239                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000749                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000541                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010756                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.279373                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.106654                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58039.547038                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61536.078404                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        67500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58734.350238                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64144.911504                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 60422.020983                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.865377                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.913857                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.109347                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.548604                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53749.881836                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59393.523292                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56679.960281                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58039.547038                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54565.083729                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        67500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58734.350238                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59619.458537                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57194.817495                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58039.547038                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        67500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57194.817495                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.toL2Bus.throughput                   119643708                       # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq            2534658                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2534658                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq            767581                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp           767581                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           570720                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           30701                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         17545                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          48246                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           260694                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          260694                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       864108                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1226294                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6184                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12819                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       939372                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4600756                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6173                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15243                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7670949                       # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27234976                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41362613                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         7152                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15780                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30036788                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39599456                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7388                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        21348                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total          138285501                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus             138285501                       # Total data (bytes)
system.toL2Bus.snoop_data_through_bus         4606436                       # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy         4757764712                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1924888432                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1752701680                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy           4396499                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy           8876994                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy        2115350205                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy        2925844707                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
system.toL2Bus.respLayer8.occupancy           4326000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer9.occupancy           9906999                       # Layer occupancy (ticks)
system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
system.iobus.throughput                      45460895                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq              7671423                       # Transaction distribution
system.iobus.trans_dist::ReadResp             7671423                       # Transaction distribution
system.iobus.trans_dist::WriteReq                7962                       # Transaction distribution
system.iobus.trans_dist::WriteResp               7962                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8040                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          740                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          496                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382642                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                15358770                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40317                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16080                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1480                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2389989                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total             54294501                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                54294501                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21416000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              4026000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               376000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               298000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.1                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374680000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         16364250250                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                     6063582                       # DTB read hits
system.cpu0.dtb.read_misses                      3748                       # DTB read misses
system.cpu0.dtb.write_hits                    5648980                       # DTB write hits
system.cpu0.dtb.write_misses                      807                       # DTB write misses
system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    1709                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   140                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                 6067330                       # DTB read accesses
system.cpu0.dtb.write_accesses                5649787                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         11712562                       # DTB hits
system.cpu0.dtb.misses                           4555                       # DTB misses
system.cpu0.dtb.accesses                     11717117                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                    29557926                       # ITB inst hits
system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    1181                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                29560131                       # ITB inst accesses
system.cpu0.itb.hits                         29557926                       # DTB hits
system.cpu0.itb.misses                           2205                       # DTB misses
system.cpu0.itb.accesses                     29560131                       # DTB accesses
system.cpu0.numCycles                      2388624356                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   28859743                       # Number of instructions committed
system.cpu0.committedOps                     34624628                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             30439288                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
system.cpu0.num_func_calls                    1241573                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      4174263                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    30439288                       # number of integer instructions
system.cpu0.num_fp_insts                         3860                       # number of float instructions
system.cpu0.num_int_register_reads           53589242                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          19764786                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           123695766                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           15045730                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     12225186                       # number of memory refs
system.cpu0.num_load_insts                    6245915                       # Number of load instructions
system.cpu0.num_store_insts                   5979271                       # Number of store instructions
system.cpu0.num_idle_cycles              2246427873.598119                       # Number of idle cycles
system.cpu0.num_busy_cycles              142196482.401881                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.059531                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.940469                       # Percentage of idle cycles
system.cpu0.Branches                          5599312                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                14563      0.04%      0.04% # Class of executed instruction
system.cpu0.op_class::IntAlu                 22957352     65.14%     65.18% # Class of executed instruction
system.cpu0.op_class::IntMult                   43755      0.12%     65.31% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc               692      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     65.31% # Class of executed instruction
system.cpu0.op_class::MemRead                 6245915     17.72%     83.03% # Class of executed instruction
system.cpu0.op_class::MemWrite                5979271     16.97%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  35241548                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   47055                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements           425168                       # number of replacements
system.cpu0.icache.tags.tagsinuse          509.375466                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           29132228                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs           425680                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            68.436920                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      75988011000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.375466                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994874                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.994874                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          269                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses         29983590                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses        29983590                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     29132228                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       29132228                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     29132228                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        29132228                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     29132228                       # number of overall hits
system.cpu0.icache.overall_hits::total       29132228                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       425681                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       425681                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       425681                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        425681                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       425681                       # number of overall misses
system.cpu0.icache.overall_misses::total       425681                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5899766682                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total   5899766682                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst   5899766682                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total   5899766682                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst   5899766682                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total   5899766682                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     29557909                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     29557909                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     29557909                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     29557909                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     29557909                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     29557909                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014402                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014402                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014402                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014402                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014402                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014402                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13859.595993                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13859.595993                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425681                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       425681                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       425681                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       425681                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       425681                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       425681                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5046160318                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   5046160318                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5046160318                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   5046160318                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5046160318                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   5046160318                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442165750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    442165750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442165750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    442165750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014402                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014402                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014402                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014402                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014402                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014402                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11854.323585                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11854.323585                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11854.323585                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11854.323585                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11854.323585                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements           329792                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          452.041842                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           11239100                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           330304                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            34.026533                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        671364250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   452.041842                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.882894                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.882894                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         46848154                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        46848154                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data      5514035                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        5514035                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      5340154                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       5340154                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data        64966                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total        64966                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       148024                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       148024                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149636                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       149636                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     10854189                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10854189                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     10919155                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10919155                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       179189                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       179189                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       145422                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       145422                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        62829                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total        62829                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9439                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         9439                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7485                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         7485                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       324611                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        324611                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       387440                       # number of overall misses
system.cpu0.dcache.overall_misses::total       387440                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2350643732                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   2350643732                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5817567140                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   5817567140                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     94706749                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total     94706749                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44450567                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total     44450567                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8168210872                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   8168210872                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8168210872                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   8168210872                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data      5693224                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      5693224                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      5485576                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5485576                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       127795                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       127795                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157463                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       157463                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157121                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       157121                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     11178800                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     11178800                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     11306595                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     11306595                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031474                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031474                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026510                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.026510                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.491639                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.491639                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059944                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059944                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047638                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047638                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029038                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.029038                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034267                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.034267                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13118.236789                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13118.236789                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40004.725145                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 40004.725145                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5938.619506                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5938.619506                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       305747                       # number of writebacks
system.cpu0.dcache.writebacks::total           305747                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          276                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          276                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         4042                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total         4042                       # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data         4318                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total         4318                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data         4318                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total         4318                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       178913                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       178913                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141380                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       141380                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        48508                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        48508                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9439                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9439                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7483                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total         7483                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       320293                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       320293                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       368801                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       368801                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   1988652518                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   1988652518                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5320324110                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5320324110                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    853626758                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    853626758                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     75777251                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     75777251                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29483433                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29483433                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7308976628                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   7308976628                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8162603386                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   8162603386                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13564535750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13564535750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1170801000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1170801000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14735336750                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14735336750                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031426                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031426                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025773                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025773                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.379577                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.379577                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059944                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059944                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047626                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047626                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028652                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028652                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032618                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032618                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8028.101600                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8028.101600                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3940.055192                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3940.055192                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     7408792                       # DTB read hits
system.cpu1.dtb.read_misses                      3640                       # DTB read misses
system.cpu1.dtb.write_hits                    5825509                       # DTB write hits
system.cpu1.dtb.write_misses                     1435                       # DTB write misses
system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1866                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 7412432                       # DTB read accesses
system.cpu1.dtb.write_accesses                5826944                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         13234301                       # DTB hits
system.cpu1.dtb.misses                           5075                       # DTB misses
system.cpu1.dtb.accesses                     13239376                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                    33190882                       # ITB inst hits
system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1276                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                33193053                       # ITB inst accesses
system.cpu1.itb.hits                         33190882                       # DTB hits
system.cpu1.itb.misses                           2171                       # DTB misses
system.cpu1.itb.accesses                     33193053                       # DTB accesses
system.cpu1.numCycles                      2387219429                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   32579955                       # Number of instructions committed
system.cpu1.committedOps                     38765002                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             35167643                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
system.cpu1.num_func_calls                     962341                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      3529676                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    35167643                       # number of integer instructions
system.cpu1.num_fp_insts                         6793                       # number of float instructions
system.cpu1.num_int_register_reads           64976079                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          23977665                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           139669414                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           14465628                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     13620676                       # number of memory refs
system.cpu1.num_load_insts                    7578910                       # Number of load instructions
system.cpu1.num_store_insts                   6041766                       # Number of store instructions
system.cpu1.num_idle_cycles              1873842319.884373                       # Number of idle cycles
system.cpu1.num_busy_cycles              513377109.115627                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.215052                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.784948                       # Percentage of idle cycles
system.cpu1.Branches                          4944984                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                14265      0.04%      0.04% # Class of executed instruction
system.cpu1.op_class::IntAlu                 25564023     65.13%     65.17% # Class of executed instruction
system.cpu1.op_class::IntMult                   50133      0.13%     65.29% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     65.29% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              1482      0.00%     65.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     65.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     65.30% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     65.30% # Class of executed instruction
system.cpu1.op_class::MemRead                 7578910     19.31%     84.61% # Class of executed instruction
system.cpu1.op_class::MemWrite                6041766     15.39%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  39250579                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   44258                       # number of quiesce instructions executed
system.cpu1.icache.tags.replacements           469324                       # number of replacements
system.cpu1.icache.tags.tagsinuse          478.642267                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           32721042                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           469836                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            69.643539                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      93149552500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.642267                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934848                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.934848                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          456                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         33660714                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        33660714                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     32721042                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       32721042                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     32721042                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        32721042                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     32721042                       # number of overall hits
system.cpu1.icache.overall_hits::total       32721042                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       469836                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       469836                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       469836                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        469836                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       469836                       # number of overall misses
system.cpu1.icache.overall_misses::total       469836                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6435695955                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   6435695955                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   6435695955                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   6435695955                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   6435695955                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   6435695955                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     33190878                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     33190878                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     33190878                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     33190878                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     33190878                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     33190878                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014156                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.014156                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014156                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.014156                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014156                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.014156                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13697.749757                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13697.749757                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       469836                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       469836                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       469836                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       469836                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       469836                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       469836                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5494111045                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   5494111045                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5494111045                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   5494111045                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5494111045                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   5494111045                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6835750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6835750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6835750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      6835750                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014156                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014156                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014156                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.014156                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014156                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.014156                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11693.678315                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11693.678315                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11693.678315                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11693.678315                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11693.678315                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11693.678315                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements           292234                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          471.923930                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           11040887                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           292603                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            37.733335                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle      84705826250                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.923930                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.921726                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.921726                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          369                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          356                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.720703                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         45818347                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        45818347                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      6006097                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        6006097                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      4823101                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       4823101                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        22483                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        22483                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81936                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        81936                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82707                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        82707                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     10829198                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        10829198                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     10851681                       # number of overall hits
system.cpu1.dcache.overall_hits::total       10851681                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       144053                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       144053                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data       152082                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       152082                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        41875                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        41875                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11222                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        11222                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10064                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        10064                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       296135                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        296135                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       338010                       # number of overall misses
system.cpu1.dcache.overall_misses::total       338010                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1718496498                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1718496498                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6437170330                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   6437170330                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     96291249                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total     96291249                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52005971                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total     52005971                       # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   8155666828                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   8155666828                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   8155666828                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   8155666828                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      6150150                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      6150150                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      4975183                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      4975183                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        64358                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        64358                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        93158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92771                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        92771                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     11125333                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     11125333                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     11189691                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     11189691                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023423                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.023423                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030568                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.030568                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.650657                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.650657                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120462                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120462                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108482                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108482                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026618                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.026618                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.030207                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.030207                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8580.578239                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8580.578239                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5167.524940                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5167.524940                       # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs           57                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs           57                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       264973                       # number of writebacks
system.cpu1.dcache.writebacks::total           264973                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          379                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          379                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data         2067                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total         2067                       # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data         2446                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total         2446                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data         2446                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total         2446                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       143674                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       143674                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150015                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total       150015                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        26855                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        26855                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11222                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11222                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10062                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        10062                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       293689                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       293689                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       320544                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       320544                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1427169251                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1427169251                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6022199670                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6022199670                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    445093004                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    445093004                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73834751                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     73834751                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31881029                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31881029                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7449368921                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   7449368921                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7894461925                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   7894461925                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25187299088                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25187299088                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023361                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023361                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030153                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030153                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.417275                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.417275                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.120462                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120462                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108461                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108461                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026398                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026398                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.028646                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.028646                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  9933.385658                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  9933.385658                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6579.464534                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6579.464534                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3168.458458                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3168.458458                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
system.iocache.tags.data_accesses                   0                       # Number of data accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 745112259250                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------