path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.868319                       # Number of seconds simulated
sim_ticks                                2868318696500                       # Number of ticks simulated
final_tick                               2868318696500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 534652                       # Simulator instruction rate (inst/s)
host_op_rate                                   646675                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            11631340017                       # Simulator tick rate (ticks/s)
host_mem_usage                                 586476                       # Number of bytes of host memory used
host_seconds                                   246.60                       # Real time elapsed on the host
sim_insts                                   131846562                       # Number of instructions simulated
sim_ops                                     159471778                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1173796                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          1283584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher      8628800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           156308                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data           605472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher       378048                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12227608                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1173796                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       156308                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1330104                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8654400                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8672144                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             26794                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             20582                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       134825                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2597                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data              9484                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher         5907                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                200214                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          135225                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               139661                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              409228                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              447504                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher      3008313                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               54495                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              211090                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       131801                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4262988                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         409228                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          54495                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             463723                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3017238                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6172                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3023424                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3017238                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             409228                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             453676                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher      3008313                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              54495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             211103                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       131801                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7286412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        200214                       # Number of read requests accepted
system.physmem.writeReqs                       175885                       # Number of write requests accepted
system.physmem.readBursts                      200214                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     175885                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12804096                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9600                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10892544                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12227608                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               10990480                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      150                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    5671                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          13850                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12188                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12046                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12591                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12330                       # Per bank write bursts
system.physmem.perBankRdBursts::4               20750                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12582                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12043                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12246                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12442                       # Per bank write bursts
system.physmem.perBankRdBursts::9               12402                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11722                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11146                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11467                       # Per bank write bursts
system.physmem.perBankRdBursts::13              11916                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10852                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11341                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10835                       # Per bank write bursts
system.physmem.perBankWrBursts::1               11264                       # Per bank write bursts
system.physmem.perBankWrBursts::2               11493                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10899                       # Per bank write bursts
system.physmem.perBankWrBursts::4               10487                       # Per bank write bursts
system.physmem.perBankWrBursts::5               11152                       # Per bank write bursts
system.physmem.perBankWrBursts::6               11024                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10595                       # Per bank write bursts
system.physmem.perBankWrBursts::8               10782                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10958                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10716                       # Per bank write bursts
system.physmem.perBankWrBursts::11              10408                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10444                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9906                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9416                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9817                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    2868318254500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9742                       # Read request sizes (log2)
system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  190444                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4436                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 171449                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    138850                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     16077                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     10399                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9072                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5697                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4782                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4036                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       52                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     8259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     9096                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    10239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    11796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    11771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    12530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    11837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    11533                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    10810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      533                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        90415                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      262.086778                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     144.561031                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.181928                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          46335     51.25%     51.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17813     19.70%     70.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6067      6.71%     77.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3600      3.98%     81.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2534      2.80%     84.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1568      1.73%     86.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1031      1.14%     87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          985      1.09%     88.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10482     11.59%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          90415                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7120                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.098736                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      516.724228                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7117     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7120                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7120                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.903933                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.122109                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       22.073987                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5764     80.96%     80.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             237      3.33%     84.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              43      0.60%     84.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             234      3.29%     88.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             121      1.70%     89.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              62      0.87%     90.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              31      0.44%     91.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              36      0.51%     91.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             117      1.64%     93.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              18      0.25%     93.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              25      0.35%     93.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              16      0.22%     94.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              40      0.56%     94.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              10      0.14%     94.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              17      0.24%     95.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              28      0.39%     95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              58      0.81%     96.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              14      0.20%     96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               7      0.10%     96.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               6      0.08%     96.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              88      1.24%     97.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.06%     97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            12      0.17%     98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     98.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            15      0.21%     98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             6      0.08%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            14      0.20%     98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             9      0.13%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            35      0.49%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             6      0.08%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             8      0.11%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.03%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.04%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             8      0.11%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.01%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             4      0.06%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             3      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             3      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7120                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4855930250                       # Total ticks spent queuing
system.physmem.totMemAccLat                8607130250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1000320000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       24271.88                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  43021.88                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           4.46                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.80                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        4.26                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.69                       # Average write queue length when enqueuing
system.physmem.readRowHits                     167229                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    112615                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.59                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  66.16                       # Row buffer hit rate for writes
system.physmem.avgGap                      7626497.96                       # Average gap between requests
system.physmem.pageHitRate                      75.58                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  354707640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  193540875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 832845000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                568613520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           187344349920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            84727272375                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1646666587500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1920687916830                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.622475                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2739235632500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     95779320000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     33303656000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  328829760                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  179421000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 727646400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                534256560                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           187344349920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            83962556955                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1647337390500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1920414451095                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.527135                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2740355751000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     95779320000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     32179536500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     7749                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7749                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1459                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         6290                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         7749                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7749    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7749                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         6355                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean  8363.375452                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean  7097.000757                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  5454.838397                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         6203     97.61%     97.61% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767          142      2.23%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151            6      0.09%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            3      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::180224-196607            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         6355                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    987959000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      987959000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    987959000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         4935     77.66%     77.66% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1420     22.34%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6355                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7749                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7749                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6355                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6355                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        14104                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    19044092                       # DTB read hits
system.cpu0.dtb.read_misses                      6608                       # DTB read misses
system.cpu0.dtb.write_hits                   15688894                       # DTB write hits
system.cpu0.dtb.write_misses                     1141                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3442                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1734                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                19050700                       # DTB read accesses
system.cpu0.dtb.write_accesses               15690035                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         34732986                       # DTB hits
system.cpu0.dtb.misses                           7749                       # DTB misses
system.cpu0.dtb.accesses                     34740735                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3348                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3348                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          298                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3050                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3348    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3348                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean  8781.732419                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean  7396.194245                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  5559.104899                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191         1469     62.99%     62.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383          817     35.03%     98.03% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575            4      0.17%     98.20% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           39      1.67%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151            1      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::106496-114687            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2332                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    987617000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      987617000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    987617000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2034     87.22%     87.22% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          298     12.78%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2332                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3348                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2332                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5680                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    91510827                       # ITB inst hits
system.cpu0.itb.inst_misses                      3348                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2150                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                91514175                       # ITB inst accesses
system.cpu0.itb.hits                         91510827                       # DTB hits
system.cpu0.itb.misses                           3348                       # DTB misses
system.cpu0.itb.accesses                     91514175                       # DTB accesses
system.cpu0.numCycles                      5736637393                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   89363678                       # Number of instructions committed
system.cpu0.committedOps                    107297883                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             94350928                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9820                       # Number of float alu accesses
system.cpu0.num_func_calls                    6606472                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     12627044                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    94350928                       # number of integer instructions
system.cpu0.num_fp_insts                         9820                       # number of float instructions
system.cpu0.num_int_register_reads          169124164                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          64348180                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7560                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           385798415                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           43074064                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     35866705                       # number of memory refs
system.cpu0.num_load_insts                   19295047                       # Number of load instructions
system.cpu0.num_store_insts                  16571658                       # Number of store instructions
system.cpu0.num_idle_cycles              5512519658.266078                       # Number of idle cycles
system.cpu0.num_busy_cycles              224117734.733922                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.039068                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.960932                       # Percentage of idle cycles
system.cpu0.Branches                         19970568                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 73557669     67.15%     67.15% # Class of executed instruction
system.cpu0.op_class::IntMult                  108302      0.10%     67.25% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8177      0.01%     67.26% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.26% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.26% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.26% # Class of executed instruction
system.cpu0.op_class::MemRead                19295047     17.61%     84.87% # Class of executed instruction
system.cpu0.op_class::MemWrite               16571658     15.13%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 109543126                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1879                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           690539                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          487.185772                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           33864824                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           691051                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            49.004812                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1015908000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   487.185772                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.951535                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.951535                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         70103571                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        70103571                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     17785791                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       17785791                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     14958877                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      14958877                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       318525                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       318525                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       364927                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       364927                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       361705                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       361705                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     32744668                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        32744668                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     33063193                       # number of overall hits
system.cpu0.dcache.overall_hits::total       33063193                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       394905                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       394905                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       324481                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       324481                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       127732                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       127732                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21710                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        21710                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20007                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        20007                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       719386                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        719386                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       847118                       # number of overall misses
system.cpu0.dcache.overall_misses::total       847118                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   4990872752                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   4990872752                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4944330313                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total   4944330313                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    327573000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    327573000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    444426745                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total    444426745                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1572500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1572500                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   9935203065                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total   9935203065                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   9935203065                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total   9935203065                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     18180696                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     18180696                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     15283358                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     15283358                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446257                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       446257                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386637                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386637                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381712                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381712                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     33464054                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     33464054                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     33910311                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     33910311                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.021721                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.021721                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.021231                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.021231                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.286230                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.286230                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056151                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056151                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052414                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052414                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.021497                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.021497                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.024981                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.024981                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       504116                       # number of writebacks
system.cpu0.dcache.writebacks::total           504116                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25128                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        25128                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15248                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15248                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        25128                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        25128                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        25128                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        25128                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       369777                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       369777                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       324481                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       324481                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       100470                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       100470                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6462                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6462                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20007                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total        20007                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       694258                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       694258                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       794728                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       794728                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3859056498                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3859056498                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4283066685                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4283066685                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1502769500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1502769500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     90797250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     90797250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    403751255                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    403751255                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1480500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1480500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8142123183                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total   8142123183                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9644892683                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total   9644892683                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   5991645999                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5991645999                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   4628507500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4628507500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  10620153499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10620153499                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.020339                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.020339                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.021231                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021231                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.225139                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.225139                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016713                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016713                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052414                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052414                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.020746                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.020746                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.023436                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.023436                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1099798                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.479276                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           90410508                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1100310                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            82.168214                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      13323414750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.479276                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998983                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.998983                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        184121973                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       184121973                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     90410508                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       90410508                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     90410508                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        90410508                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     90410508                       # number of overall hits
system.cpu0.icache.overall_hits::total       90410508                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1100319                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1100319                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1100319                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1100319                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1100319                       # number of overall misses
system.cpu0.icache.overall_misses::total      1100319                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10739818993                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  10739818993                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  10739818993                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  10739818993                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  10739818993                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  10739818993                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     91510827                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     91510827                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     91510827                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     91510827                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     91510827                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     91510827                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012024                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.012024                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012024                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.012024                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012024                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.012024                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  9760.641226                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  9760.641226                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  9760.641226                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  9760.641226                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  9760.641226                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  9760.641226                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1100319                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1100319                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      1100319                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1100319                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      1100319                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1100319                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9082830507                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total   9082830507                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9082830507                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total   9082830507                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9082830507                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total   9082830507                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    719096500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    719096500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    719096500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    719096500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.012024                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012024                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.012024                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.012024                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.012024                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.012024                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  8254.724773                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  8254.724773                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  8254.724773                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  8254.724773                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  8254.724773                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  8254.724773                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued      1853283                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      1853292                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage       238164                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          268426                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16093.899190                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           1968322                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          284663                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            6.914569                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  7921.036071                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.357121                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.109776                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4473.771805                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  1953.197848                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1743.426570                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.483462                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000144                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.273057                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.119214                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.106410                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.982294                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1127                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15106                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          288                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          418                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          412                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3213                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7809                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3908                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.068787                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000244                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.921997                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        39654154                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       39654154                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7774                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3610                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1053168                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data       381762                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       1446314                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks       504114                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total       504114                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        28406                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        28406                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data         1700                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total         1700                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       227802                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       227802                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7774                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3610                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1053168                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       609564                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1674116                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7774                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3610                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1053168                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       609564                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1674116                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          215                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          122                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst        47151                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data        94947                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total       142435                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26586                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26586                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18299                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18299                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data        41687                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total        41687                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          215                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          122                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        47151                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       136634                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       184122                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          215                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          122                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        47151                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       136634                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       184122                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4899750                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2713500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   2213649997                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data   2684439955                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   4905703202                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    458226521                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    458226521                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    356750783                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    356750783                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1434495                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1434495                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   1789174823                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   1789174823                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4899750                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2713500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   2213649997                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data   4473614778                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total   6694878025                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4899750                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2713500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   2213649997                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data   4473614778                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total   6694878025                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7989                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3732                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1100319                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data       476709                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      1588749                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks       504114                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total       504114                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        54992                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        54992                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19999                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        19999                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269489                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269489                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7989                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3732                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1100319                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       746198                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1858238                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7989                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3732                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1100319                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       746198                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1858238                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.026912                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.032690                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.042852                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.199172                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.089652                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.483452                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.483452                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.914996                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.914996                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154689                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154689                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.026912                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.032690                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042852                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.183107                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.099084                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.026912                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.032690                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042852                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.183107                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.099084                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22789.534884                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22241.803279                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46948.102840                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28273.036062                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34441.697630                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17235.632325                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17235.632325                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19495.643642                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19495.643642                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 179311.875000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 179311.875000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 42919.251157                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 42919.251157                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22789.534884                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22241.803279                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46948.102840                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 32741.592708                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 36361.097669                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22789.534884                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22241.803279                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46948.102840                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 32741.592708                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 36361.097669                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       196247                       # number of writebacks
system.cpu0.l2cache.writebacks::total          196247                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data           32                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total           32                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1210                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         1210                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1242                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total         1242                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1242                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total         1242                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          215                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          122                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst        47151                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data        94915                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total       142403                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       246323                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       246323                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        26586                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total        26586                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        18299                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        18299                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        40477                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total        40477                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          215                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          122                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        47151                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data       135392                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total       182880                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          215                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          122                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        47151                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data       135392                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       246323                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total       429203                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3394250                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1859500                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   1877090003                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data   2013208709                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   3895552462                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  13906201830                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  13906201830                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data    448274629                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total    448274629                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    246009723                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    246009723                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1112495                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1112495                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   1381066645                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   1381066645                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3394250                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1859500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   1877090003                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   3394275354                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total   5276619107                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3394250                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1859500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   1877090003                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   3394275354                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  13906201830                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total  19182820937                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    647209500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5743013251                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6390222751                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   4419325000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   4419325000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    647209500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  10162338251                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10809547751                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.026912                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.032690                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.042852                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.199105                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.089632                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.483452                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.483452                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.914996                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.914996                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.150199                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.150199                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.026912                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.032690                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042852                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.181442                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.098416                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.026912                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.032690                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042852                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.181442                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.230973                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq       1737767                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1686227                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        27891                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        27891                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback       504114                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq       316054                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        89164                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42476                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       112407                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           43                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           81                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       298764                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       285064                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2218682                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2366147                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        10130                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        22028                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          4616987                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     70456504                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     84324454                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        14928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        31956                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         154827842                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     648932                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      2984532                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.180419                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.384536                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5           2446067     81.96%     81.96% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6            538465     18.04%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       2984532                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy    1775358935                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    115165999                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   1664866493                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   1209535062                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy      6398000                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy     14039749                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     3332                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3332                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          642                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         2690                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         3332                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3332    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3332                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         2562                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean  8324.355972                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean  7260.502547                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  4990.324891                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         2067     80.68%     80.68% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383          375     14.64%     95.32% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575           62      2.42%     97.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767           50      1.95%     99.69% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959            4      0.16%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151            3      0.12%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         2562                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1455144968                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1455144968    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1455144968                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1928     75.25%     75.25% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          634     24.75%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2562                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3332                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3332                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2562                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2562                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5894                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    10115566                       # DTB read hits
system.cpu1.dtb.read_misses                      2828                       # DTB read misses
system.cpu1.dtb.write_hits                    6544640                       # DTB write hits
system.cpu1.dtb.write_misses                      504                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2029                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   346                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                10118394                       # DTB read accesses
system.cpu1.dtb.write_accesses                6545144                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         16660206                       # DTB hits
system.cpu1.dtb.misses                           3332                       # DTB misses
system.cpu1.dtb.accesses                     16663538                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1746                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1746                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          168                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1578                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1746    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1746                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean  8955.736224                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean  7685.889357                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  5645.921496                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095          191     17.25%     17.25% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191          643     58.08%     75.34% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383          217     19.60%     94.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479            1      0.09%     95.03% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575            3      0.27%     95.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671           27      2.44%     97.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767           19      1.72%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959            3      0.27%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.27%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         1107                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1454651968                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1454651968    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1454651968                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          939     84.82%     84.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          168     15.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1107                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1746                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1107                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2853                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    44359905                       # ITB inst hits
system.cpu1.itb.inst_misses                      1746                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1148                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                44361651                       # ITB inst accesses
system.cpu1.itb.hits                         44359905                       # DTB hits
system.cpu1.itb.misses                           1746                       # DTB misses
system.cpu1.itb.accesses                     44361651                       # DTB accesses
system.cpu1.numCycles                      5735725430                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   42482884                       # Number of instructions committed
system.cpu1.committedOps                     52173895                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             47161467                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1857                       # Number of float alu accesses
system.cpu1.num_func_calls                    7121857                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      4915281                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    47161467                       # number of integer instructions
system.cpu1.num_fp_insts                         1857                       # number of float instructions
system.cpu1.num_int_register_reads           90906541                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          34070734                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1341                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           192636366                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           15749934                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     16924073                       # number of memory refs
system.cpu1.num_load_insts                   10229886                       # Number of load instructions
system.cpu1.num_store_insts                   6694187                       # Number of store instructions
system.cpu1.num_idle_cycles              5637554126.704413                       # Number of idle cycles
system.cpu1.num_busy_cycles              98171303.295587                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.017116                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.982884                       # Percentage of idle cycles
system.cpu1.Branches                         12116511                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 37117349     68.64%     68.64% # Class of executed instruction
system.cpu1.op_class::IntMult                   29132      0.05%     68.70% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3361      0.01%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.70% # Class of executed instruction
system.cpu1.op_class::MemRead                10229886     18.92%     87.62% # Class of executed instruction
system.cpu1.op_class::MemWrite                6694187     12.38%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  54073981                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2789                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements           191058                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          472.360308                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           16390617                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           191421                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            85.626013                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     104654883500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.360308                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.922579                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.922579                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          363                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          312                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.708984                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         33541448                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        33541448                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data      9797337                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        9797337                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      6353174                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       6353174                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        49731                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        49731                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        79655                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        79655                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        71640                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        71640                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     16150511                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        16150511                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     16200242                       # number of overall hits
system.cpu1.dcache.overall_hits::total       16200242                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       137366                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       137366                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        93147                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        93147                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30426                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30426                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17223                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total        17223                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23379                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        23379                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       230513                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        230513                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       260939                       # number of overall misses
system.cpu1.dcache.overall_misses::total       260939                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1997360003                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total   1997360003                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2352005341                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total   2352005341                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    320800000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total    320800000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    539390293                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total    539390293                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1691000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1691000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data   4349365344                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total   4349365344                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data   4349365344                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total   4349365344                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data      9934703                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      9934703                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      6446321                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      6446321                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80157                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        80157                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96878                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96878                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        95019                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        95019                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     16381024                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     16381024                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     16461181                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     16461181                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.013827                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.013827                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.014450                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.014450                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.379580                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.379580                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.177780                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.177780                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.246046                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.246046                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.014072                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.014072                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.015852                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.015852                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks       118649                       # number of writebacks
system.cpu1.dcache.writebacks::total           118649                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          239                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total          239                       # number of ReadReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12076                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12076                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data          239                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total          239                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data          239                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total          239                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       137127                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total       137127                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        93147                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total        93147                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        29658                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total        29658                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         5147                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total         5147                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23379                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total        23379                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data       230274                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total       230274                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data       259932                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total       259932                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1715737747                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1715737747                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2159697659                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2159697659                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    467259500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    467259500                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     82226250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     82226250                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    491497707                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    491497707                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1621000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1621000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3875435406                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total   3875435406                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4342694906                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total   4342694906                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    525084500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    525084500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    379956000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    379956000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    905040500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total    905040500                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013803                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.013803                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014450                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.014450                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.369999                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.369999                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.053129                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.053129                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.246046                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.246046                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.014057                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.014057                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.015791                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.015791                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements           526723                       # number of replacements
system.cpu1.icache.tags.tagsinuse          498.608741                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           43832665                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           527235                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            83.136865                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      84507534000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.608741                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973845                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.973845                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          387                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses         89247035                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses        89247035                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     43832665                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       43832665                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     43832665                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        43832665                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     43832665                       # number of overall hits
system.cpu1.icache.overall_hits::total       43832665                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       527235                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       527235                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       527235                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        527235                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       527235                       # number of overall misses
system.cpu1.icache.overall_misses::total       527235                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4617960760                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total   4617960760                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst   4617960760                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total   4617960760                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst   4617960760                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total   4617960760                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst     44359900                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     44359900                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     44359900                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     44359900                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     44359900                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     44359900                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011885                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011885                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011885                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011885                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011885                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011885                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8758.828151                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8758.828151                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8758.828151                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8758.828151                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8758.828151                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8758.828151                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       527235                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total       527235                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst       527235                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total       527235                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst       527235                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total       527235                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3826248740                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total   3826248740                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3826248740                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total   3826248740                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3826248740                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total   3826248740                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13994500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     13994500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     13994500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total     13994500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011885                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011885                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011885                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011885                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011885                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011885                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7257.197910                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7257.197910                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7257.197910                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7257.197910                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7257.197910                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7257.197910                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued       199846                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified       199846                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage        59474                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           47689                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15083.724459                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs            731618                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           62301                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           11.743279                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  8757.920968                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     3.140482                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.100736                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3269.623984                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2111.182929                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   939.755359                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.534541                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000192                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000128                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.199562                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.128856                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.057358                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.920637                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1198                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        13391                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           29                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         1169                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          282                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1514                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        11595                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.073120                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001404                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.817322                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        15244499                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       15244499                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3091                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1729                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst       513133                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data       102720                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        620673                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks       118649                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total       118649                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data         1485                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total         1485                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data          867                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total          867                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        28139                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        28139                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3091                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1729                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       513133                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       130859                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         648812                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3091                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1729                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       513133                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       130859                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        648812                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          321                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          276                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst        14102                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data        69212                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        83911                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28339                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28339                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22509                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22509                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        35184                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        35184                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          321                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          276                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        14102                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       104396                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       119095                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          321                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          276                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        14102                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       104396                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       119095                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      6369000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5421000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst    483830740                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data   1476489366                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1972110106                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    522569379                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    522569379                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    435248439                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    435248439                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1586000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1586000                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1289152696                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   1289152696                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      6369000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5421000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst    483830740                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data   2765642062                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total   3261262802                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      6369000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5421000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst    483830740                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data   2765642062                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total   3261262802                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3412                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2005                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       527235                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data       171932                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       704584                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks       118649                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total       118649                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29824                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        29824                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23376                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        23376                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63323                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        63323                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3412                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2005                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       527235                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       235255                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       767907                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3412                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2005                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       527235                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       235255                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       767907                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.094080                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.137656                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.026747                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.402554                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.119093                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.950208                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.950208                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.962911                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.962911                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.555627                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.555627                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.094080                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.137656                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026747                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.443757                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.155090                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.094080                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.137656                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026747                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.443757                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.155090                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19841.121495                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19641.304348                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34309.370302                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21332.852193                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23502.402617                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18439.937154                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18439.937154                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19336.640411                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19336.640411                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 528666.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528666.666667                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36640.310823                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36640.310823                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19841.121495                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19641.304348                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34309.370302                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26491.839362                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 27383.708821                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19841.121495                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19641.304348                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34309.370302                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26491.839362                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 27383.708821                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks        31472                       # number of writebacks
system.cpu1.l2cache.writebacks::total           31472                       # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           76                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total           76                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data           76                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total           76                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data           76                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total           76                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          321                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          276                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst        14102                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data        69212                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        83911                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        24018                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total        24018                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28339                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28339                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        22509                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        22509                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        35108                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total        35108                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          321                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          276                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        14102                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data       104320                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total       119019                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          321                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          276                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        14102                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data       104320                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        24018                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total       143037                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4122000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3489000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst    384250260                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data    991800372                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total   1383661632                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    814752860                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    814752860                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    402368047                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    402368047                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    306023777                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    306023777                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1341000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1341000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1031661014                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1031661014                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4122000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3489000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    384250260                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2023461386                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total   2415322646                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4122000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3489000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    384250260                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2023461386                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    814752860                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total   3230075506                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12590000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    494236499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    506826499                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    356773500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    356773500                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12590000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    851009999                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    863599999                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.094080                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.137656                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.026747                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.402554                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.119093                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.950208                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.950208                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.962911                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.962911                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.554427                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.554427                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.094080                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.137656                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026747                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.443434                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.154991                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.094080                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.137656                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026747                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.443434                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.186269                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       447000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       447000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq       1051189                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       750269                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         3091                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         3091                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback       118649                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq        33325                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        74679                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41637                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        85827                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           49                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           81                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        85544                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        68027                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1054824                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       784590                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         5329                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         9434                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          1854177                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     33743748                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25394480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         8020                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        13648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          59159896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     572639                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1437265                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.343414                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.474848                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5            943688     65.66%     65.66% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6            493577     34.34%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1437265                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy     595732734                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy     80038500                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy    791497760                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy    388635637                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy      3324000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy      6022000                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                31024                       # Transaction distribution
system.iobus.trans_dist::ReadResp               31024                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59440                       # Transaction distribution
system.iobus.trans_dist::WriteResp              23216                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56656                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107970                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180928                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162850                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484122                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             40136000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                90000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347109131                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            84754000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36846525                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36445                       # number of replacements
system.iocache.tags.tagsinuse               14.387294                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36461                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         287959539000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.387294                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.899206                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.899206                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
system.iocache.tags.data_accesses              328311                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          255                       # number of overall misses
system.iocache.overall_misses::total              255                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     31782377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     31782377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9599974229                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9599974229                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     31782377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     31782377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     31782377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     31782377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124636.772549                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124636.772549                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124636.772549                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124636.772549                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124636.772549                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         55555                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7160                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.759078                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     18521377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     18521377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7716276279                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7716276279                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     18521377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     18521377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     18521377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     18521377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72632.850980                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72632.850980                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   130735                       # number of replacements
system.l2c.tags.tagsinuse                63966.604731                       # Cycle average of tags in use
system.l2c.tags.total_refs                     343053                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   195063                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.758678                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   12083.139597                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.938906                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     1.007553                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     6678.027236                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2760.487108                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.955640                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1552.248405                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      535.801693                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1990.692549                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.184374                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000060                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.101899                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.042122                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.585332                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.023685                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.008176                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.030376                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.976053                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32989                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        31331                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          170                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4524                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        28295                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          254                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         1895                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        29170                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.503372                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.000122                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.478073                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  4931105                       # Number of tag accesses
system.l2c.tags.data_accesses                 4931105                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker           82                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker           63                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst              29372                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data              45566                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher        45492                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker           34                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker           41                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst              11667                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data               8537                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher         5785                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 146639                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          227719                       # number of Writeback hits
system.l2c.Writeback_hits::total               227719                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            2362                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             770                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3132                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data           164                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data           164                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               328                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data             3862                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             1497                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                 5359                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker            82                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            63                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               29372                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               49428                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher        45492                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            34                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            41                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               11667                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               10034                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher         5785                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  151998                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           82                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           63                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              29372                       # number of overall hits
system.l2c.overall_hits::cpu0.data              49428                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher        45492                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           34                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           41                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              11667                       # number of overall hits
system.l2c.overall_hits::cpu1.data              10034                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher         5785                       # number of overall hits
system.l2c.overall_hits::total                 151998                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            17779                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data             8894                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       134996                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             2435                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data              924                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher         5907                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               170945                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          8889                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          2898                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             11787                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          758                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1209                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1967                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          11387                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data           8562                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              19949                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             17779                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             20281                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       134996                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2435                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data              9486                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher         5907                       # number of demand (read+write) misses
system.l2c.demand_misses::total                190894                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            17779                       # number of overall misses
system.l2c.overall_misses::cpu0.data            20281                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       134996                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2435                       # number of overall misses
system.l2c.overall_misses::cpu1.data             9486                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher         5907                       # number of overall misses
system.l2c.overall_misses::total               190894                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       494750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   1299838245                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data    708631748                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  13069199153                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        75000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    182647247                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data     78676500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher    680911899                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    16020624042                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      5423319                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      2108409                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      7531728                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       679977                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       605974                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total      1285951                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data    888864663                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data    627516972                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1516381635                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       494750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1299838245                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   1597496411                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  13069199153                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        75000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    182647247                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data    706193472                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher    680911899                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     17537005677                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       494750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1299838245                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   1597496411                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  13069199153                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        75000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    182647247                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data    706193472                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher    680911899                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    17537005677                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker           89                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker           65                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst          47151                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data          54460                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher       180488                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker           35                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker           41                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst          14102                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data           9461                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher        11692                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             317584                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       227719                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           227719                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11251                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3668                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           14919                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          922                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1373                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2295                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        15249                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        10059                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            25308                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker           89                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           65                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           47151                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data           69709                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       180488                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           35                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           41                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           14102                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           19520                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher        11692                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              342892                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker           89                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           65                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          47151                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data          69709                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       180488                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           35                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           41                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          14102                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          19520                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher        11692                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             342892                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.078652                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.377065                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.163313                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.747950                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.028571                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.172671                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.097664                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.505217                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.538267                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.790063                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.790076                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.790066                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.822126                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.880554                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.857081                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.746737                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.851178                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.788249                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.078652                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.377065                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.290938                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.747950                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.028571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.172671                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.485963                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.505217                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.556718                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.078652                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.377065                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.290938                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.747950                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.028571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.172671                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.485963                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.505217                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.556718                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        75000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75009.136345                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 85147.727273                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 93718.003112                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   610.115761                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   727.539337                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   638.986002                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   897.067282                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   501.219189                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total   653.762583                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78059.599807                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73290.933427                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76012.914682                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70678.571429                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73110.874909                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 78768.128347                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        75000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75009.136345                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74445.864643                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 91867.767855                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70678.571429                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73110.874909                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78768.128347                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        75000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75009.136345                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74445.864643                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 91867.767855                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               99035                       # number of writebacks
system.l2c.writebacks::total                    99035                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu1.inst             3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 4                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  4                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 4                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        17779                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data         8894                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       134996                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         2432                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data          923                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher         5907                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          170941                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         8889                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         2898                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        11787                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          758                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1209                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1967                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        11387                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data         8562                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         19949                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        17779                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        20281                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       134996                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         2432                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data         9485                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher         5907                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           190890                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        17779                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        20281                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       134996                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         2432                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data         9485                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher         5907                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          190890                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       408750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   1075716745                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data    597785248                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  11388842153                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    151904497                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data     67178000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher    608475899                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  13890498792                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     90106352                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     29086385                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    119192737                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7710755                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     12095707                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     19806462                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data    746306335                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    519227026                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1265533361                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       408750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   1075716745                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   1344091583                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  11388842153                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    151904497                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data    586405026                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher    608475899                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  15156032153                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       408750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   1075716745                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   1344091583                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  11388842153                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    151904497                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data    586405026                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    608475899                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  15156032153                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    476665000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5183212748                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      9260500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    424539000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6093677248                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   3944737000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    304049000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4248786000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    476665000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9127949748                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      9260500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    728588000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10342463248                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.078652                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.030769                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.377065                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.163313                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.747950                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.028571                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.172458                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.097558                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.505217                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.538254                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.790063                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.790076                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.790066                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.822126                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.880554                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.857081                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.746737                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.851178                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.788249                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.078652                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.030769                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.377065                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.290938                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.747950                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.028571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.172458                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.485912                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.505217                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.556706                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.078652                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.030769                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.377065                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.290938                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.747950                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.028571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.172458                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.485912                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.505217                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.556706                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 79396.679517                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 79396.679517                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              215303                       # Transaction distribution
system.membus.trans_dist::ReadResp             215303                       # Transaction distribution
system.membus.trans_dist::WriteReq              30982                       # Transaction distribution
system.membus.trans_dist::WriteResp             30982                       # Transaction distribution
system.membus.trans_dist::Writeback            135225                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            76008                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40410                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           13867                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            5                       # Transaction distribution
system.membus.trans_dist::ReadExReq             40350                       # Transaction distribution
system.membus.trans_dist::ReadExResp            19836                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107970                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13762                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       659440                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       781206                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 890114                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162850                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27524                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18582632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18773074                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23408530                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           123675                       # Total snoops (count)
system.membus.snoop_fanout::samples            499419                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  499419    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              499419                       # Request fanout histogram
system.membus.reqLayer0.occupancy            88165000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               18500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            11453500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1828859499                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1931425684                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38544475                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             482729                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            482714                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30982                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30982                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           227719                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq        36225                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           79027                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         40738                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         119765                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           81                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           81                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq            51496                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp           51496                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1065854                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       282098                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1347952                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     31837086                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4944756                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               36781842                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          286323                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           873908                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.041744                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.200003                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 837428     95.83%     95.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  36480      4.17%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             873908                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1446151615                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1080000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1735034184                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         618323353                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------