path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.615716                       # Number of seconds simulated
sim_ticks                                2615716222000                       # Number of ticks simulated
final_tick                               2615716222000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 250038                       # Simulator instruction rate (inst/s)
host_op_rate                                   318184                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            10864403710                       # Simulator tick rate (ticks/s)
host_mem_usage                                 394540                       # Number of bytes of host memory used
host_seconds                                   240.76                       # Real time elapsed on the host
sim_insts                                    60199078                       # Number of instructions simulated
sim_ops                                      76605946                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            704928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9093712                       # Number of bytes read from this memory
system.physmem.bytes_read::total            132482480                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       704928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          704928                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3710144                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6726216                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              17217                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142123                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15494771                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           57971                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               811989                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46902409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               269497                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3476567                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50648644                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          269497                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             269497                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1418405                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1153058                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2571462                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1418405                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46902409                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              269497                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4629625                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53220107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15494771                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       811989                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                    15494771                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     811989                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                    991665344                       # Total number of bytes read from memory
system.physmem.bytesWritten                  51967296                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd              132482480                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6726216                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                     1656                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               4515                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                968108                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                967905                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                967771                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                967944                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                974355                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                968114                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                967591                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                967671                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                968519                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                968300                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10               967957                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11               967810                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12               967935                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13               967629                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14               967816                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15               967690                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  6734                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  6600                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  6526                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  6493                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  6702                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  6993                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  6729                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6823                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7180                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  6976                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 6694                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 6614                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 6691                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 6338                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 6636                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 6497                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    2615711849000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                    6652                       # Categorize read packet sizes
system.physmem.readPktSize::3                15335424                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  152695                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                 754018                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  57971                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                   1137574                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    984079                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1018155                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3783404                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2827794                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2821787                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2781992                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     18262                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     15752                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     29208                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    42299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    28515                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1054                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1034                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                     1015                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       48                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        38068                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    26227.310287                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    2428.378300                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   31656.989485                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-127          5540     14.55%     14.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-191         3323      8.73%     23.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-255         2175      5.71%     29.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-319         1668      4.38%     33.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-383         1160      3.05%     36.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-447         1060      2.78%     39.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-511          828      2.18%     41.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-575          781      2.05%     43.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-639          514      1.35%     44.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-703          493      1.30%     46.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-767          417      1.10%     47.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-831          450      1.18%     48.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-895          283      0.74%     49.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-959          279      0.73%     49.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-1023          185      0.49%     50.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1087          195      0.51%     50.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1151          134      0.35%     51.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1215          139      0.37%     51.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1279          114      0.30%     51.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1343           94      0.25%     52.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1407           76      0.20%     52.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1471          150      0.39%     52.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1535          792      2.08%     54.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1599          203      0.53%     55.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1663          136      0.36%     55.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1727          113      0.30%     55.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1791           91      0.24%     56.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1855           85      0.22%     56.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1919           60      0.16%     56.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1983           34      0.09%     56.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2047           44      0.12%     56.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2111           48      0.13%     56.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2175           31      0.08%     56.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2239           35      0.09%     57.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2303           24      0.06%     57.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2367           25      0.07%     57.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2431           18      0.05%     57.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2495           18      0.05%     57.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2559           21      0.06%     57.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2623           13      0.03%     57.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2687            5      0.01%     57.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2751           11      0.03%     57.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2815            8      0.02%     57.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2879           15      0.04%     57.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2943           17      0.04%     57.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-3007            7      0.02%     57.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3071            7      0.02%     57.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3135           18      0.05%     57.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3199            8      0.02%     57.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3263            8      0.02%     57.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3327           10      0.03%     57.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3391           16      0.04%     57.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3455            6      0.02%     57.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3519           11      0.03%     57.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3583            6      0.02%     57.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3647            5      0.01%     57.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3711            5      0.01%     57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3775            7      0.02%     57.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3839            6      0.02%     57.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3903            6      0.02%     57.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3967            6      0.02%     57.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-4031            9      0.02%     57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4095            9      0.02%     57.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4159           42      0.11%     58.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4223            2      0.01%     58.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4287            4      0.01%     58.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4351            4      0.01%     58.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4415            8      0.02%     58.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4479            6      0.02%     58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4543            4      0.01%     58.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4607            5      0.01%     58.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4671            5      0.01%     58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4735            6      0.02%     58.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4799            2      0.01%     58.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4863            1      0.00%     58.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4927            6      0.02%     58.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4991            1      0.00%     58.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5055            3      0.01%     58.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5119            2      0.01%     58.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5183           10      0.03%     58.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5247            1      0.00%     58.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5311            2      0.01%     58.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5375            5      0.01%     58.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5439            5      0.01%     58.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5503            2      0.01%     58.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5567            3      0.01%     58.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5631            3      0.01%     58.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5759            2      0.01%     58.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5823            3      0.01%     58.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5951            1      0.00%     58.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-6015            2      0.01%     58.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6143            2      0.01%     58.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6207            2      0.01%     58.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6335            2      0.01%     58.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6399            1      0.00%     58.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6527            4      0.01%     58.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6591            1      0.00%     58.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6655            1      0.00%     58.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6719            1      0.00%     58.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6783            6      0.02%     58.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6847           16      0.04%     58.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6911            4      0.01%     58.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7039            4      0.01%     58.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7103            4      0.01%     58.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7167            1      0.00%     58.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7231            4      0.01%     58.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7295            2      0.01%     58.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7423            2      0.01%     58.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7487            3      0.01%     58.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7551            2      0.01%     58.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7615            3      0.01%     58.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7679            4      0.01%     58.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7743            5      0.01%     58.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7807            2      0.01%     58.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7871            1      0.00%     58.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7935            6      0.02%     58.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7999            7      0.02%     58.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8063            6      0.02%     58.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8127            8      0.02%     58.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8191            8      0.02%     58.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8255          328      0.86%     59.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8319            1      0.00%     59.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8511           24      0.06%     59.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8575          141      0.37%     59.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8639          169      0.44%     60.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8767            1      0.00%     60.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8831            1      0.00%     60.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8895            2      0.01%     60.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-9023            3      0.01%     60.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9279            3      0.01%     60.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9535            1      0.00%     60.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10303            4      0.01%     60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11583            1      0.00%     60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11967            1      0.00%     60.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12095            2      0.01%     60.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12991            1      0.00%     60.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13119            4      0.01%     60.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13247            1      0.00%     60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13375            1      0.00%     60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13887            1      0.00%     60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-14015            1      0.00%     60.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14399            4      0.01%     60.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14655            1      0.00%     60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-15039            1      0.00%     60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15935            1      0.00%     60.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16191            2      0.01%     60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16447            1      0.00%     60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16703            1      0.00%     60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17215            1      0.00%     60.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17471            3      0.01%     60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17727            1      0.00%     60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18239            2      0.01%     60.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18495            5      0.01%     60.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18624-18687            1      0.00%     60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19263            1      0.00%     60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19391            1      0.00%     60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19519            3      0.01%     60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20287            1      0.00%     60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20415            1      0.00%     60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20543            1      0.00%     60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21823            1      0.00%     60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22079            2      0.01%     60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22144-22207            1      0.00%     60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22335            1      0.00%     60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22847            1      0.00%     60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23103            1      0.00%     60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23168-23231            1      0.00%     60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23359            1      0.00%     60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23615            4      0.01%     60.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24127            1      0.00%     60.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24192-24255            1      0.00%     60.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24383            3      0.01%     60.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24639            1      0.00%     60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24895            1      0.00%     60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25151            1      0.00%     60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25407            1      0.00%     60.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25663            1      0.00%     60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25791            1      0.00%     60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26687            1      0.00%     60.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26943            2      0.01%     60.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27455            2      0.01%     60.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27711            4      0.01%     60.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28223            2      0.01%     60.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28479            1      0.00%     60.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28735            2      0.01%     60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28863            1      0.00%     60.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29247            3      0.01%     60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29503            1      0.00%     60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29759            3      0.01%     60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-30015            1      0.00%     60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30271            1      0.00%     60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30336-30399            1      0.00%     60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30783            1      0.00%     60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-31039            1      0.00%     60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31167            1      0.00%     60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31168-31231            1      0.00%     60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31295            2      0.01%     60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31423            1      0.00%     60.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31551            2      0.01%     60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31680-31743            1      0.00%     60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31807            6      0.02%     60.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32063            1      0.00%     60.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32319            1      0.00%     60.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33087           16      0.04%     60.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33152-33215           19      0.05%     60.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33343           23      0.06%     60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33599            1      0.00%     60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34879            1      0.00%     60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35903            1      0.00%     60.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36415            2      0.01%     60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36927            1      0.00%     60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37951            1      0.00%     60.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40255            1      0.00%     60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41279            2      0.01%     60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41791            1      0.00%     60.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42047            1      0.00%     60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43327            1      0.00%     60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46143            1      0.00%     60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46399            1      0.00%     60.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46528-46591            1      0.00%     60.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47167            3      0.01%     60.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47935            1      0.00%     60.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48191            1      0.00%     60.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48447            1      0.00%     60.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48959            1      0.00%     60.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49664-49727            1      0.00%     60.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51263            2      0.01%     60.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52287            2      0.01%     60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56320-56383            1      0.00%     60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56576-56639            1      0.00%     60.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57344-57407            1      0.00%     60.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57600-57663            1      0.00%     60.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58368-58431            2      0.01%     60.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60416-60479            1      0.00%     60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60672-60735            1      0.00%     60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61184-61247            1      0.00%     60.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61696-61759            1      0.00%     60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63488-63551            1      0.00%     60.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65024-65087          190      0.50%     61.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65088-65151            6      0.02%     61.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65216-65279            6      0.02%     61.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65343            1      0.00%     61.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65472-65535            1      0.00%     61.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65599        14664     38.52%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::67392-67455            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::69760-69823            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::71744-71807            2      0.01%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73984-74047            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          38068                       # Bytes accessed per row activation
system.physmem.totQLat                   296768605750                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat              390592239500                       # Sum of mem lat for all requests
system.physmem.totBusLat                  77465575000                       # Total cycles spent in databus access
system.physmem.totBankLat                 16358058750                       # Total cycles spent in bank access
system.physmem.avgQLat                       19154.87                       # Average queueing delay per request
system.physmem.avgBankLat                     1055.83                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  25210.70                       # Average memory access latency
system.physmem.avgRdBW                         379.12                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          19.87                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  50.65                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   2.57                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           3.12                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.15                       # Average read queue length over time
system.physmem.avgWrQLen                        13.76                       # Average write queue length over time
system.physmem.readRowHits                   15468398                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     93875                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.84                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  11.56                       # Row buffer hit rate for writes
system.physmem.avgGap                       160406.60                       # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54136917                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16546596                       # Transaction distribution
system.membus.trans_dist::ReadResp           16546596                       # Transaction distribution
system.membus.trans_dist::WriteReq             763368                       # Transaction distribution
system.membus.trans_dist::WriteResp            763368                       # Transaction distribution
system.membus.trans_dist::Writeback             57971                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4515                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4515                       # Transaction distribution
system.membus.trans_dist::ReadExReq            132250                       # Transaction distribution
system.membus.trans_dist::ReadExResp           132250                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382988                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893731                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280581                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34951429                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390393                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16525304                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18923421                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           141606813                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              141606813                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1206151000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3613000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17904160000                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4944878700                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        34615555500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.throughput                      47816267                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16518752                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16518752                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8166                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8166                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7946                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          534                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382988                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30670848                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                33053836                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15892                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390393                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            125073785                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               125073785                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3978000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               534000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               527000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15335424000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374822000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         42038784500                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     14996146                       # DTB read hits
system.cpu.dtb.read_misses                       7341                       # DTB read misses
system.cpu.dtb.write_hits                    11230467                       # DTB write hits
system.cpu.dtb.write_misses                      2217                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3506                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    197                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 15003487                       # DTB read accesses
system.cpu.dtb.write_accesses                11232684                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          26226613                       # DTB hits
system.cpu.dtb.misses                            9558                       # DTB misses
system.cpu.dtb.accesses                      26236171                       # DTB accesses
system.cpu.itb.inst_hits                     61492923                       # ITB inst hits
system.cpu.itb.inst_misses                       4471                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 61497394                       # ITB inst accesses
system.cpu.itb.hits                          61492923                       # DTB hits
system.cpu.itb.misses                            4471                       # DTB misses
system.cpu.itb.accesses                      61497394                       # DTB accesses
system.cpu.numCycles                       5231432444                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    60199078                       # Number of instructions committed
system.cpu.committedOps                      76605946                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              68872726                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
system.cpu.num_func_calls                     2140465                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7948429                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     68872726                       # number of integer instructions
system.cpu.num_fp_insts                         10269                       # number of float instructions
system.cpu.num_int_register_reads           394779183                       # number of times the integer registers were read
system.cpu.num_int_register_writes           74182470                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
system.cpu.num_mem_refs                      27394080                       # number of memory refs
system.cpu.num_load_insts                    15660200                       # Number of load instructions
system.cpu.num_store_insts                   11733880                       # Number of store instructions
system.cpu.num_idle_cycles               4581975478.612248                       # Number of idle cycles
system.cpu.num_busy_cycles               649456965.387752                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.124145                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.875855                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83018                       # number of quiesce instructions executed
system.cpu.icache.tags.replacements            856273                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.884220                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            60636138                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            856785                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             70.771708                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       19799760250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.884220                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997821                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997821                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     60636138                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        60636138                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      60636138                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         60636138                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     60636138                       # number of overall hits
system.cpu.icache.overall_hits::total        60636138                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       856785                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        856785                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       856785                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         856785                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       856785                       # number of overall misses
system.cpu.icache.overall_misses::total        856785                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11770019500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11770019500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11770019500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11770019500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11770019500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11770019500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     61492923                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     61492923                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     61492923                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     61492923                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     61492923                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     61492923                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013933                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013933                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013933                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013933                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013933                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013933                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13737.424792                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13737.424792                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856785                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       856785                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       856785                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       856785                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       856785                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       856785                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10051263500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  10051263500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10051263500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  10051263500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10051263500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  10051263500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    414413750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    414413750                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    414413750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    414413750                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013933                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013933                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013933                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.371931                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.371931                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.371931                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.371931                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.371931                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.371931                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            62587                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        50733.810806                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1683077                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           127973                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            13.151813                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     2564904211000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37696.862224                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884576                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000692                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  6998.396772                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6034.666541                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.575208                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106787                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.092082                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.774137                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8720                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3535                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       844543                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       370162                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1226960                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       595785                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       595785                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       113425                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       113425                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         8720                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3535                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       844543                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       483587                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1340385                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         8720                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3535                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       844543                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       483587                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1340385                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        10601                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         9837                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        20445                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2872                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2872                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133893                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133893                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        10601                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143730                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154338                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        10601                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143730                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154338                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       390500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       122500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    747407000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    696870750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1444790750                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       470980                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       470980                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8609068107                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8609068107                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       390500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    747407000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9305938857                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10053858857                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       390500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       122500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    747407000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9305938857                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10053858857                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8725                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3537                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       855144                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       379999                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1247405                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       595785                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       595785                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2898                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2898                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       247318                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       247318                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8725                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3537                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       855144                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       627317                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1494723                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8725                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3537                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       855144                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       627317                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1494723                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000573                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000565                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012397                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025887                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016390                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991028                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991028                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541380                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541380                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000573                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000565                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012397                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.229119                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.103255                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000573                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000565                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012397                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.229119                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.103255                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        78100                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        61250                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70503.443071                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70841.796279                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70667.192468                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   163.990251                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   163.990251                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64298.119446                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64298.119446                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        78100                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        61250                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70503.443071                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64745.974097                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 65141.824159                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        78100                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        61250                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70503.443071                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64745.974097                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 65141.824159                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        57971                       # number of writebacks
system.cpu.l2cache.writebacks::total            57971                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10601                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9837                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        20445                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2872                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2872                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133893                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133893                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10601                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143730                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154338                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10601                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143730                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154338                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       326500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        97500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    613945500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    572634250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1187003750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     28725872                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     28725872                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6933351393                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6933351393                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       326500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        97500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    613945500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7505985643                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8120355143                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       326500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        97500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    613945500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7505985643                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8120355143                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    322980250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657157250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166980137500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16702542535                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16702542535                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    322980250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359699785                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183682680035                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000573                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012397                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025887                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016390                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991028                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991028                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541380                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541380                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000573                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012397                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229119                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.103255                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000573                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000565                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012397                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229119                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.103255                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        65300                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57913.923215                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58212.285250                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58058.388359                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.044568                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.044568                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51782.777240                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51782.777240                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        65300                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        48750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57913.923215                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52222.818083                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52614.101148                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        65300                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        48750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            626805                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.881003                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            23655596                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            627317                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             37.709158                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         640871250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.881003                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999768                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999768                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13195774                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13195774                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      9972821                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        9972821                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       236302                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       236302                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247801                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247801                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      23168595                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         23168595                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     23168595                       # number of overall hits
system.cpu.dcache.overall_hits::total        23168595                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       368499                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        368499                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       250216                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       250216                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        11500                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        11500                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       618715                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         618715                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       618715                       # number of overall misses
system.cpu.dcache.overall_misses::total        618715                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5384538000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5384538000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10623511265                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10623511265                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    158750500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    158750500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  16008049265                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  16008049265                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  16008049265                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  16008049265                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13564273                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13564273                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10223037                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10223037                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247802                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       247802                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247801                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247801                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     23787310                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     23787310                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     23787310                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     23787310                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027167                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.027167                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024476                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.024476                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046408                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046408                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.026010                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.026010                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.026010                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.026010                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25873.058298                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25873.058298                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       595785                       # number of writebacks
system.cpu.dcache.writebacks::total            595785                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368499                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       368499                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250216                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       250216                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11500                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        11500                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       618715                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       618715                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       618715                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       618715                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4642816500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4642816500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10058410735                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10058410735                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135673500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135673500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14701227235                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  14701227235                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14701227235                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  14701227235                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26234094465                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26234094465                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027167                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027167                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024476                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024476                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046408                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046408                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026010                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.026010                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026010                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.026010                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput                53011951                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2455175                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2455175                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763368                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763368                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       595785                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2898                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2898                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       247318                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       247318                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725171                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5751163                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12463                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27463                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7516260                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54755700                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83692841                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14148                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34900                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      138497589                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         138497589                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       166632                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3009741500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1296026750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2542955300                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       8926500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      18739250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1460469685500                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------