path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.594328                       # Number of seconds simulated
sim_ticks                                2594327510000                       # Number of ticks simulated
final_tick                               2594327510000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 600896                       # Simulator instruction rate (inst/s)
host_op_rate                                   764626                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            25897323777                       # Simulator tick rate (ticks/s)
host_mem_usage                                 390576                       # Number of bytes of host memory used
host_seconds                                   100.18                       # Real time elapsed on the host
sim_insts                                    60196191                       # Number of instructions simulated
sim_ops                                      76598245                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            704288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9067216                       # Number of bytes read from this memory
system.physmem.bytes_read::total            132455344                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       704288                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          704288                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3695616                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6711688                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              17207                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141709                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15494347                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           57744                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               811762                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47289092                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            123                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               271472                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3495016                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                51055753                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          271472                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             271472                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1424499                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1162564                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2587063                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1424499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47289092                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              271472                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4657580                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53642816                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         62159                       # number of replacements
system.l2c.tagsinuse                     51417.185894                       # Cycle average of tags in use
system.l2c.total_refs                         1682923                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        127542                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         13.195049                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                  2544924960000                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        38023.288706                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker        3.884784                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.000558                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           7004.395748                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           6385.616098                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.580189                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000059                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.106879                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.097437                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.784564                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker          8754                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker          3544                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst              843519                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              370124                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1225941                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          596001                       # number of Writeback hits
system.l2c.Writeback_hits::total               596001                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            114391                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               114391                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker           8754                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker           3544                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst               843519                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data               484515                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1340332                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker          8754                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker          3544                       # number of overall hits
system.l2c.overall_hits::cpu.inst              843519                       # number of overall hits
system.l2c.overall_hits::cpu.data              484515                       # number of overall hits
system.l2c.overall_hits::total                1340332                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             10591                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             10247                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                20845                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           2879                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2879                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          133059                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             133059                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              10591                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             143306                       # number of demand (read+write) misses
system.l2c.demand_misses::total                153904                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu.inst             10591                       # number of overall misses
system.l2c.overall_misses::cpu.data            143306                       # number of overall misses
system.l2c.overall_misses::total               153904                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker       260500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker       104000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst    552260500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data    533540500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1086165500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data      1040000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1040000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   6923957000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6923957000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker       260500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker       104000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst    552260500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   7457497500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      8010122500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker       260500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker       104000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst    552260500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   7457497500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     8010122500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker         8759                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker         3546                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst          854110                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data          380371                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1246786                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       596001                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           596001                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         2905                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2905                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        247450                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247450                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker         8759                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker         3546                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst           854110                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data           627821                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1494236                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker         8759                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker         3546                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst          854110                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data          627821                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1494236                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000564                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.012400                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.026939                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016719                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.991050                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991050                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.537721                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.537721                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.000564                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.012400                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.228259                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.102998                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.000564                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.012400                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.228259                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.102998                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52100                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.320650                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52067.971113                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52106.764212                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data   361.236540                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   361.236540                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52036.743099                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52036.743099                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52144.320650                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52038.976037                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52046.226869                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52144.320650                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52038.976037                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52046.226869                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               57744                       # number of writebacks
system.l2c.writebacks::total                    57744                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        10591                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        10247                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           20845                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         2879                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2879                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       133059                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        133059                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         10591                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        143306                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           153904                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        10591                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       143306                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          153904                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       200000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        80000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    425162000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data    410573000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    836015000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    115365000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    115365000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5327229000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5327229000                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       200000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    425162000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   5737802000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6163244000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       200000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker        80000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    425162000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   5737802000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6163244000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst    264840000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131435179000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131700019000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31197392500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total  31197392500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.inst    264840000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 162632571500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 162897411500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026939                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016719                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991050                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991050                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.537721                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.537721                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.228259                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.102998                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.228259                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.102998                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40046.028693                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40046.028693                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     14995137                       # DTB read hits
system.cpu.dtb.read_misses                       7357                       # DTB read misses
system.cpu.dtb.write_hits                    11229787                       # DTB write hits
system.cpu.dtb.write_misses                      2205                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3485                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    182                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 15002494                       # DTB read accesses
system.cpu.dtb.write_accesses                11231992                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          26224924                       # DTB hits
system.cpu.dtb.misses                            9562                       # DTB misses
system.cpu.dtb.accesses                      26234486                       # DTB accesses
system.cpu.itb.inst_hits                     61490084                       # ITB inst hits
system.cpu.itb.inst_misses                       4471                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 61494555                       # ITB inst accesses
system.cpu.itb.hits                          61490084                       # DTB hits
system.cpu.itb.misses                            4471                       # DTB misses
system.cpu.itb.accesses                      61494555                       # DTB accesses
system.cpu.numCycles                       5188655020                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    60196191                       # Number of instructions committed
system.cpu.committedOps                      76598245                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              68865648                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
system.cpu.num_func_calls                     2139540                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7910583                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     68865648                       # number of integer instructions
system.cpu.num_fp_insts                         10269                       # number of float instructions
system.cpu.num_int_register_reads           394743471                       # number of times the integer registers were read
system.cpu.num_int_register_writes           74177139                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
system.cpu.num_mem_refs                      27392126                       # number of memory refs
system.cpu.num_load_insts                    15659006                       # Number of load instructions
system.cpu.num_store_insts                   11733120                       # Number of store instructions
system.cpu.num_idle_cycles               4570211154.554238                       # Number of idle cycles
system.cpu.num_busy_cycles               618443865.445762                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.119192                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.880808                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    82989                       # number of quiesce instructions executed
system.cpu.icache.replacements                 855220                       # number of replacements
system.cpu.icache.tagsinuse                510.929118                       # Cycle average of tags in use
system.cpu.icache.total_refs                 60634352                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 855732                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  70.856707                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            18856022000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.929118                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.997908                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.997908                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     60634352                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        60634352                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      60634352                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         60634352                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     60634352                       # number of overall hits
system.cpu.icache.overall_hits::total        60634352                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       855732                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        855732                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       855732                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         855732                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       855732                       # number of overall misses
system.cpu.icache.overall_misses::total        855732                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  12556184500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  12556184500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  12556184500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  12556184500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  12556184500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  12556184500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     61490084                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     61490084                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     61490084                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     61490084                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     61490084                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     61490084                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013917                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013917                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013917                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013917                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013917                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013917                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14673.033730                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14673.033730                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       855732                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       855732                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       855732                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       855732                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       855732                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       855732                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9987081500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9987081500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9987081500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9987081500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9987081500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9987081500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    350913000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    350913000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    350913000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    350913000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013917                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013917                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013917                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 627309                       # number of replacements
system.cpu.dcache.tagsinuse                511.875626                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 23653426                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 627821                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  37.675430                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              661351000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.875626                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999757                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999757                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13194612                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13194612                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      9972158                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        9972158                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       236094                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       236094                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247657                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247657                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      23166770                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         23166770                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     23166770                       # number of overall hits
system.cpu.dcache.overall_hits::total        23166770                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       368807                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        368807                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       250355                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       250355                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        11564                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        11564                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       619162                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         619162                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       619162                       # number of overall misses
system.cpu.dcache.overall_misses::total        619162                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5738700500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5738700500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9229453000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9229453000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    171857500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    171857500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  14968153500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  14968153500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  14968153500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  14968153500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13563419                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13563419                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222513                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222513                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247658                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       247658                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247657                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247657                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     23785932                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     23785932                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     23785932                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     23785932                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027191                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.027191                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024491                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.024491                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046693                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046693                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.026031                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.026031                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.026031                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.026031                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24174.858115                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24174.858115                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       596001                       # number of writebacks
system.cpu.dcache.writebacks::total            596001                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368807                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       368807                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250355                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       250355                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11564                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        11564                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       619162                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       619162                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       619162                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       619162                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4631124500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4631124500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8478310000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8478310000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    137164000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    137164000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13109434500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  13109434500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13109434500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  13109434500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40357680500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40357680500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027191                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027191                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024491                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024491                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046693                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046693                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026031                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.026031                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026031                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.026031                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1342178832750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------