path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.909587                       # Number of seconds simulated
sim_ticks                                2909586837500                       # Number of ticks simulated
final_tick                               2909586837500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 929184                       # Simulator instruction rate (inst/s)
host_op_rate                                  1120306                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            24040663881                       # Simulator tick rate (ticks/s)
host_mem_usage                                 581600                       # Number of bytes of host memory used
host_seconds                                   121.03                       # Real time elapsed on the host
sim_insts                                   112457033                       # Number of instructions simulated
sim_ops                                     135588117                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1186532                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8901860                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10089928                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1186532                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1186532                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7512000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7529524                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26993                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             139611                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166628                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117375                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121756                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               407801                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3059493                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3467822                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          407801                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             407801                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2581810                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6023                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2587833                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2581810                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              407801                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3065516                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6055654                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166628                       # Number of read requests accepted
system.physmem.writeReqs                       121756                       # Number of write requests accepted
system.physmem.readBursts                      166628                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     121756                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10657408                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7542016                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10089928                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7529524                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10077                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10695                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10660                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18797                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9664                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9666                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10487                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9973                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9232                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8679                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9822                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10379                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9723                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8282                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8171                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7489                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7661                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6695                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7533                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7264                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    2909586480500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  157056                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117375                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    165639                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       614                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1976                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5904                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6035                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6789                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        58742                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      309.818528                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.858167                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.750191                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21399     36.43%     36.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14737     25.09%     61.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6061     10.32%     71.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3228      5.50%     77.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2535      4.32%     81.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1458      2.48%     84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1057      1.80%     85.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1079      1.84%     87.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7188     12.24%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          58742                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5615                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.654497                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      597.763680                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5614     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5615                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5615                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.987355                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.791633                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       15.100649                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4949     88.14%     88.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              78      1.39%     89.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              32      0.57%     90.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              46      0.82%     90.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              24      0.43%     91.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              20      0.36%     91.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              46      0.82%     92.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               4      0.07%     92.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             153      2.72%     95.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              11      0.20%     95.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               7      0.12%     95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              13      0.23%     95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              63      1.12%     96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.09%     97.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.09%     97.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              26      0.46%     97.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             103      1.83%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.04%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.02%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.04%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             8      0.14%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.12%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             4      0.07%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5615                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1624802000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4747089500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    832610000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9757.28                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28507.28                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.59                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
system.physmem.readRowHits                     136095                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89528                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.73                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.96                       # Row buffer hit rate for writes
system.physmem.avgGap                     10089278.46                       # Average gap between requests
system.physmem.pageHitRate                      79.34                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  230829480                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  125948625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 702195000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                392895360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           190039717920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            90325761075                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1666515907500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1948333254960                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.626580                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2772215900000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     97157320000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     40208512500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  213260040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  116362125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 596668800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                370733760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           190039717920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            88049301345                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1668512802000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1947898845990                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.477277                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2775567504000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     97157320000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     36861865500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                      9546                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                 9546                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1255                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8291                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples         9546                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0            9546    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total         9546                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7382                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  8541.710442                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767         7377     99.93%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7382                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples   1638910500                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      1638910500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total   1638910500                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6174     83.64%     83.64% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1208     16.36%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7382                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9546                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9546                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7382                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7382                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        16928                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24520655                       # DTB read hits
system.cpu.dtb.read_misses                       8124                       # DTB read misses
system.cpu.dtb.write_hits                    19606816                       # DTB write hits
system.cpu.dtb.write_misses                      1422                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4272                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1650                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24528779                       # DTB read accesses
system.cpu.dtb.write_accesses                19608238                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44127471                       # DTB hits
system.cpu.dtb.misses                            9546                       # DTB misses
system.cpu.dtb.accesses                      44137017                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      4763                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 4763                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          310                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         4453                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         4763                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            4763    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         4763                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3108                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12722.007722                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7865.701982                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383         2410     77.54%     77.54% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767          696     22.39%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3108                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   1638383000                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      1638383000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   1638383000                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2798     90.03%     90.03% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.97%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3108                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4763                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         4763                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3108                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3108                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         7871                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    115554258                       # ITB inst hits
system.cpu.itb.inst_misses                       4763                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                115559021                       # ITB inst accesses
system.cpu.itb.hits                         115554258                       # DTB hits
system.cpu.itb.misses                            4763                       # DTB misses
system.cpu.itb.accesses                     115559021                       # DTB accesses
system.cpu.numCycles                       5819173675                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.committedInsts                   112457033                       # Number of instructions committed
system.cpu.committedOps                     135588117                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             119893391                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
system.cpu.num_func_calls                     9892146                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     15230571                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    119893391                       # number of integer instructions
system.cpu.num_fp_insts                         11161                       # number of float instructions
system.cpu.num_int_register_reads           218063465                       # number of times the integer registers were read
system.cpu.num_int_register_writes           82646448                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            489743456                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            51893999                       # number of times the CC registers were written
system.cpu.num_mem_refs                      45407924                       # number of memory refs
system.cpu.num_load_insts                    24843119                       # Number of load instructions
system.cpu.num_store_insts                   20564805                       # Number of store instructions
system.cpu.num_idle_cycles               5379054575.844151                       # Number of idle cycles
system.cpu.num_busy_cycles               440119099.155849                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.075633                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.924367                       # Percentage of idle cycles
system.cpu.Branches                          25916787                       # Number of branches fetched
system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                  93175095     67.17%     67.18% # Class of executed instruction
system.cpu.op_class::IntMult                   114406      0.08%     67.26% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc               8453      0.01%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::MemRead                 24843119     17.91%     85.17% # Class of executed instruction
system.cpu.op_class::MemWrite                20564805     14.83%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  138708215                       # Class of executed instruction
system.cpu.dcache.tags.replacements            819223                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.702328                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            43236235                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            819735                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             52.744161                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1736147500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.702328                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999419                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999419                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         177112671                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        177112671                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23112983                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23112983                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18824226                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18824226                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       392786                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        392786                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443250                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443250                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460223                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460223                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41937209                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41937209                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42329995                       # number of overall hits
system.cpu.dcache.overall_hits::total        42329995                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       399912                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        399912                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       298709                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       298709                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       118381                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       118381                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22756                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22756                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data       698621                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         698621                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       817002                       # number of overall misses
system.cpu.dcache.overall_misses::total        817002                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   6488404500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   6488404500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  19100944000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  19100944000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    293896000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    293896000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  25589348500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  25589348500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  25589348500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  25589348500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23512895                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23512895                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19122935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19122935                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       511167                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       511167                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466006                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466006                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460225                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460225                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42635830                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42635830                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     43146997                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     43146997                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017008                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.017008                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015620                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015620                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231590                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.231590                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048832                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048832                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.016386                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.018935                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.018935                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36628.370032                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31321.035322                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          100                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                20                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       683846                       # number of writebacks
system.cpu.dcache.writebacks::total            683846                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          929                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          929                       # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14246                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14246                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          929                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          929                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          929                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          929                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       398983                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       398983                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298709                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298709                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116322                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       116322                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8510                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8510                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       697692                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       697692                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       814014                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       814014                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6058749500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6058749500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18802235000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  18802235000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1616519000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1616519000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115353500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115353500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24860984500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  24860984500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26477503500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26477503500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6278149500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6278149500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089976500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089976500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11368126000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11368126000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016969                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016969                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015620                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015620                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227562                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227562                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018262                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018262                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016364                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016364                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018866                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.018866                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13896.932652                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32527.086143                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32527.086143                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.402274                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.402274                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184492.968212                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184492.968212                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193575.799888                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193575.799888                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1695721                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.436852                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           113858019                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1696233                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             67.124044                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       29070355500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.436852                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996947                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         117250497                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        117250497                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    113858019                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113858019                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113858019                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113858019                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113858019                       # number of overall hits
system.cpu.icache.overall_hits::total       113858019                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1696239                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1696239                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1696239                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1696239                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1696239                       # number of overall misses
system.cpu.icache.overall_misses::total       1696239                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  24272134000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  24272134000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  24272134000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  24272134000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  24272134000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  24272134000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    115554258                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    115554258                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    115554258                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    115554258                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    115554258                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    115554258                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014679                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014679                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014679                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014679                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014679                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014679                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14309.383289                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14309.383289                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks      1695721                       # number of writebacks
system.cpu.icache.writebacks::total           1695721                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1696239                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1696239                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1696239                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1696239                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1696239                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1696239                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22575895000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  22575895000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22575895000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  22575895000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22575895000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  22575895000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1142541000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1142541000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1142541000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   1142541000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014679                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014679                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014679                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014679                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014679                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014679                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.383289                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.383289                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.383289                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.383289                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.383289                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.383289                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            87565                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64865.223598                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4544536                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           152800                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            29.741728                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50196.713333                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.799338                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012649                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  9701.721355                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4962.976923                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.765941                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000058                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.148037                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.075729                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989765                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65230                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6851                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56199                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995331                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         40512344                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        40512344                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7807                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4039                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          11846                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       683846                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       683846                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1664945                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1664945                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           23                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       167031                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       167031                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1678228                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1678228                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       511642                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       511642                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         7807                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4039                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1678228                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       678673                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2368747                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         7807                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4039                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1678228                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       678673                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2368747                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2742                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2742                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       128913                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       128913                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        17978                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        17978                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        12173                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        12173                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        17978                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141086                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        159073                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        17978                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141086                       # number of overall misses
system.cpu.l2cache.overall_misses::total       159073                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       957500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       266000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total      1223500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1793500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1793500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       159000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16382558000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16382558000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2351294500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2351294500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1615422500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1615422500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       957500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       266000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2351294500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  17997980500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  20350498500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       957500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       266000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2351294500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  17997980500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  20350498500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7814                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4041                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        11855                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       683846                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       683846                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1664945                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1664945                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2765                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2765                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295944                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295944                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1696206                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1696206                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       523815                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       523815                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7814                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4041                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1696206                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       819759                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2527820                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7814                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4041                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1696206                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       819759                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2527820                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000495                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.000759                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991682                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991682                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.435599                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.435599                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010599                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010599                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023239                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023239                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000495                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010599                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172107                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.062929                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000495                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010599                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172107                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.062929                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       133000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   654.084610                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   654.084610                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127082.280298                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127082.280298                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130787.323395                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130787.323395                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132705.372546                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132705.372546                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130787.323395                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127567.444679                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 127931.820611                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130787.323395                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127567.444679                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 127931.820611                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        81185                       # number of writebacks
system.cpu.l2cache.writebacks::total            81185                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2742                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2742                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       128913                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       128913                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17978                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17978                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12173                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12173                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        17978                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141086                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       159073                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        17978                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141086                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       159073                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       887500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       246000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1133500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    186544500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    186544500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       139000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15093428000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15093428000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2171514500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2171514500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1493692500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1493692500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       887500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       246000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2171514500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16587120500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  18759768500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       887500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       246000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2171514500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16587120500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  18759768500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888804000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6918570000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772572500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772572500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10661376500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11691142500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000759                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991682                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991682                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.435599                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.435599                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010599                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023239                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023239                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172107                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.062929                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172107                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.062929                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5052863                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536887                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38132                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          581                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq          67213                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2287480                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       801231                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1695721                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       141985                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2765                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2767                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295944                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295944                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1696239                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       524043                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5106210                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2581942                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13257                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        25651                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7727060                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217119416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96427485                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16164                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        31256                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          313594321                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      175889                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2774012                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.020868                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.142944                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2716123     97.91%     97.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              57889      2.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2774012                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4957617000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2553380500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1275954500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       9216000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      17837000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46336500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                97000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               644500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6279500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36469500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187058527                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36418                       # number of replacements
system.iocache.tags.tagsinuse                1.084082                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         313812610000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.084082                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067755                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067755                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328068                       # Number of tag accesses
system.iocache.tags.data_accesses              328068                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          228                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          228                       # number of demand (read+write) misses
system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          228                       # number of overall misses
system.iocache.overall_misses::total              228                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28180377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28180377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4549133150                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4549133150                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28180377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28180377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28180377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28180377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          228                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             228                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          228                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            228                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123598.144737                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123598.144737                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123598.144737                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          228                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16780377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16780377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736521626                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2736521626                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16780377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16780377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16780377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16780377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70548                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       117375                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6608                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            127158                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127158                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30388                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       434329                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       541921                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72885                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72885                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 614806                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15302332                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15465685                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17782805                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              492                       # Total snoops (count)
system.membus.snoop_fanout::samples            390011                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  390011    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              390011                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90460500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1730500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           823136860                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          943248500                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1186623                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------