path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.902862                       # Number of seconds simulated
sim_ticks                                2902861767000                       # Number of ticks simulated
final_tick                               2902861767000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 747193                       # Simulator instruction rate (inst/s)
host_op_rate                                   900893                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            19275657141                       # Simulator tick rate (ticks/s)
host_mem_usage                                 615228                       # Number of bytes of host memory used
host_seconds                                   150.60                       # Real time elapsed on the host
sim_insts                                   112525269                       # Number of instructions simulated
sim_ops                                     135672104                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1191332                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8985828                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10178696                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1191332                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1191332                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7576000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7593524                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              27068                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140923                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                168015                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118375                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122756                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               410399                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3095507                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3506435                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          410399                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             410399                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2609838                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6037                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2615875                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2609838                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              410399                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3101543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6122310                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        168015                       # Number of read requests accepted
system.physmem.writeReqs                       158980                       # Number of write requests accepted
system.physmem.readBursts                      168015                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     158980                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10745280                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7680                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9814400                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10178696                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9911860                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      120                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    5603                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4500                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9689                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9230                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10198                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10267                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18984                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10226                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10551                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10350                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9702                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9930                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9908                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8848                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9929                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10408                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9925                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9750                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9389                       # Per bank write bursts
system.physmem.perBankWrBursts::1                8975                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10251                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9953                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9418                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9499                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9770                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9764                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9682                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9836                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9791                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9091                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9681                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9852                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9372                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9026                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2902861390500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  158443                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 154599                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    167093                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       544                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       246                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     8734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     8985                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     9766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    10233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    10902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    10695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9893                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6660                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60962                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      337.252977                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     194.461800                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     352.629111                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21587     35.41%     35.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14795     24.27%     59.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5550      9.10%     68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3419      5.61%     74.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2349      3.85%     78.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1576      2.59%     80.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1011      1.66%     82.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1092      1.79%     84.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9583     15.72%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60962                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6214                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.016254                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      542.923852                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6212     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6214                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6214                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        24.678146                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.366342                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       23.738225                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5089     81.90%     81.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              32      0.51%     82.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              24      0.39%     82.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             212      3.41%     86.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             128      2.06%     88.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              65      1.05%     89.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              41      0.66%     89.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              30      0.48%     90.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             138      2.22%     92.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              16      0.26%     92.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              13      0.21%     93.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              16      0.26%     93.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              29      0.47%     93.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              17      0.27%     94.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              11      0.18%     94.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              29      0.47%     94.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              66      1.06%     95.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               8      0.13%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.05%     96.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              17      0.27%     96.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              91      1.46%     97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            15      0.24%     98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             8      0.13%     98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             6      0.10%     98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            11      0.18%     98.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     98.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            39      0.63%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             7      0.11%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.03%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.06%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             9      0.14%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.05%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             5      0.08%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.05%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             5      0.08%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.02%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             3      0.05%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             4      0.06%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6214                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1487834250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4635865500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    839475000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8861.69                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27611.69                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.70                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.38                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.51                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.41                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.07                       # Average write queue length when enqueuing
system.physmem.readRowHits                     138089                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    122193                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.67                       # Row buffer hit rate for writes
system.physmem.avgGap                      8877387.70                       # Average gap between requests
system.physmem.pageHitRate                      81.02                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  235320120                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  128398875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 698061000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                499083120                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           189600322080                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            86740865775                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1665624160500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1943526211470                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.522458                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2770750790000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     96932680000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35170942500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  225552600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  123069375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 611512200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                494624880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           189600322080                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85548905145                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1666669740000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1943273726280                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.435479                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2772511956000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     96932680000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     33417040500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                      9552                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                 9552                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1261                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8291                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples         9552                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0            9552    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total         9552                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7388                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean  9945.756632                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  7345.780525                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  7322.338006                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         5745     77.76%     77.76% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767         1639     22.18%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-81919            2      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::147456-163839            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7388                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    809108000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0       809108000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    809108000                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6174     83.57%     83.57% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1214     16.43%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7388                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9552                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9552                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7388                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7388                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        16940                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24537663                       # DTB read hits
system.cpu.dtb.read_misses                       8142                       # DTB read misses
system.cpu.dtb.write_hits                    19618927                       # DTB write hits
system.cpu.dtb.write_misses                      1410                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4273                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1664                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24545805                       # DTB read accesses
system.cpu.dtb.write_accesses                19620337                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44156590                       # DTB hits
system.cpu.dtb.misses                            9552                       # DTB misses
system.cpu.dtb.accesses                      44166142                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      4762                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 4762                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          309                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         4453                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         4762                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            4762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         4762                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3107                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean  9893.949147                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  7210.941913                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7351.443657                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1400     45.06%     45.06% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383         1004     32.31%     77.37% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          701     22.56%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::73728-81919            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3107                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples    808810000                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0       808810000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total    808810000                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2798     90.05%     90.05% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           309      9.95%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3107                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4762                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         4762                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    115624412                       # ITB inst hits
system.cpu.itb.inst_misses                       4762                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                115629174                       # ITB inst accesses
system.cpu.itb.hits                         115624412                       # DTB hits
system.cpu.itb.misses                            4762                       # DTB misses
system.cpu.itb.accesses                     115629174                       # DTB accesses
system.cpu.numCycles                       5805723534                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   112525269                       # Number of instructions committed
system.cpu.committedOps                     135672104                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             119969678                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  11290                       # Number of float alu accesses
system.cpu.num_func_calls                     9899985                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     15238216                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    119969678                       # number of integer instructions
system.cpu.num_fp_insts                         11290                       # number of float instructions
system.cpu.num_int_register_reads           218203287                       # number of times the integer registers were read
system.cpu.num_int_register_writes           82701548                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 8578                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            490054820                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            51921339                       # number of times the CC registers were written
system.cpu.num_mem_refs                      45438019                       # number of memory refs
system.cpu.num_load_insts                    24860597                       # Number of load instructions
system.cpu.num_store_insts                   20577422                       # Number of store instructions
system.cpu.num_idle_cycles               5386825418.146145                       # Number of idle cycles
system.cpu.num_busy_cycles               418898115.853856                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.072153                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.927847                       # Percentage of idle cycles
system.cpu.Branches                          25932360                       # Number of branches fetched
system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                  93231199     67.17%     67.17% # Class of executed instruction
system.cpu.op_class::IntMult                   114517      0.08%     67.26% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc               8515      0.01%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::MemRead                 24860597     17.91%     85.17% # Class of executed instruction
system.cpu.op_class::MemWrite                20577422     14.83%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  138794587                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3037                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements            823321                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.850573                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            43261398                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            823833                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             52.512339                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         876905250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.850573                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999708                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999708                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          368                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         177233078                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        177233078                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23126684                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23126684                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18835651                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18835651                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       392122                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        392122                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443636                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443636                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460570                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460570                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41962335                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41962335                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42354457                       # number of overall hits
system.cpu.dcache.overall_hits::total        42354457                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       402703                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        402703                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       299019                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       299019                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       119172                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       119172                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22743                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22743                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data       701722                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         701722                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       820894                       # number of overall misses
system.cpu.dcache.overall_misses::total        820894                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5916458250                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5916458250                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  11650381750                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  11650381750                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    280295250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    280295250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       150000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       150000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  17566840000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  17566840000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  17566840000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  17566840000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23529387                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23529387                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19134670                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19134670                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       511294                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       511294                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466379                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       466379                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460572                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460572                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42664057                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42664057                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     43175351                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     43175351                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017115                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.017115                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015627                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015627                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.233079                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.233079                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048765                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048765                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.016448                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.016448                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.019013                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.019013                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        75000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25033.902315                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21399.644778                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           78                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                34                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.294118                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       686487                       # number of writebacks
system.cpu.dcache.writebacks::total            686487                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          629                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          629                       # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14254                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14254                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          629                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          629                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          629                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          629                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       402074                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       402074                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299019                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       299019                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       117021                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       117021                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8489                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8489                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       701093                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       701093                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       818114                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       818114                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5098164750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   5098164750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10994871250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10994871250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1411142000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1411142000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    100012000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    100012000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       146000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16093036000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  16093036000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17504178000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  17504178000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5791398250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5791398250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4429682000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4429682000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10221080250                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  10221080250                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017088                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017088                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015627                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015627                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228872                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228872                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018202                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018202                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016433                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016433                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018949                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.018949                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        73000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1701491                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.782044                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           113922403                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1702003                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             66.934314                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       25181626250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.782044                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997621                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997621                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         117326421                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        117326421                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    113922403                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113922403                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113922403                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113922403                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113922403                       # number of overall hits
system.cpu.icache.overall_hits::total       113922403                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1702009                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1702009                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1702009                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1702009                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1702009                       # number of overall misses
system.cpu.icache.overall_misses::total       1702009                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  23268250500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  23268250500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  23268250500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  23268250500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  23268250500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  23268250500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    115624412                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    115624412                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    115624412                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    115624412                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    115624412                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    115624412                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014720                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014720                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014720                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014720                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014720                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014720                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13671.050212                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13671.050212                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13671.050212                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13671.050212                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13671.050212                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13671.050212                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1702009                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1702009                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1702009                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1702009                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1702009                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1702009                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19857660500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  19857660500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19857660500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  19857660500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19857660500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  19857660500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    597905000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    597905000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    597905000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    597905000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014720                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014720                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014720                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014720                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014720                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014720                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            88884                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64931.599128                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            2763158                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           154151                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            17.925009                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50668.289778                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.809348                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012227                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  9584.205539                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4675.282236                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.773137                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000058                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.146243                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.071339                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.990778                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65262                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2127                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6961                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56128                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995819                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         26260695                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        26260695                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6986                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3658                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1683931                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       515395                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2209970                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       686487                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       686487                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           23                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       166042                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       166042                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6986                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3658                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1683931                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       681437                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2376012                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6986                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3658                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1683931                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       681437                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2376012                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        18053                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        12189                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        30251                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2710                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2710                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       130244                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       130244                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        18053                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       142433                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        160495                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        18053                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       142433                       # number of overall misses
system.cpu.l2cache.overall_misses::total       160495                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       495250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       149500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1316295500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    927332750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2244273000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       444481                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       444481                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       144000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       144000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8974834460                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8974834460                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       495250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       149500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1316295500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9902167210                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11219107460                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       495250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       149500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1316295500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9902167210                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11219107460                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6993                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3660                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1701984                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       527584                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2240221                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       686487                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       686487                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2733                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2733                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296286                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296286                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6993                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3660                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1701984                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       823870                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2536507                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6993                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3660                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1701984                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       823870                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2536507                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001001                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000546                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010607                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.023103                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.013504                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991584                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991584                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.439589                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.439589                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001001                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000546                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010607                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172883                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063274                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001001                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000546                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010607                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172883                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063274                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        70750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74750                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72912.839971                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76079.477398                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74188.390466                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   164.015129                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   164.015129                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        72000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68907.853414                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68907.853414                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        70750                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72912.839971                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69521.580041                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69903.158728                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        70750                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74750                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72912.839971                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69521.580041                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69903.158728                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        82185                       # number of writebacks
system.cpu.l2cache.writebacks::total            82185                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        18053                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        12189                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        30251                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2710                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2710                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130244                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       130244                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        18053                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       142433                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       160495                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        18053                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       142433                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       160495                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       408750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1090271000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    775288750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1866093500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27282710                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27282710                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7345006540                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7345006540                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       408750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1090271000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8120295290                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9211100040                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       408750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1090271000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8120295290                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9211100040                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    474215000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5385925500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5860140500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4098165500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4098165500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    474215000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9484091000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9958306000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001001                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000546                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010607                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.023103                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.013504                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991584                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991584                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.439589                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.439589                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001001                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000546                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010607                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172883                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063274                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001001                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000546                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010607                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172883                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063274                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        2297061                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2297046                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27618                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27618                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       686487                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2733                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2735                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296286                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296286                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3422037                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2457460                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12875                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        24836                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           5917208                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    108963064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96860105                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27972                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          205865781                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       53107                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3278617                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.011120                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.104863                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            3242159     98.89%     98.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6              36458      1.11%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3278617                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     2355272500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       328500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2567431500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1312657000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       9215000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      17843250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30195                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30195                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59038                       # Transaction distribution
system.iobus.trans_dist::WriteResp              22814                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54242                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105550                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178466                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67959                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159197                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480301                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38529000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           347060139                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82736000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36804507                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.134613                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         298400039000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.134613                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.070913                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.070913                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28034377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28034377                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide   9587408255                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   9587408255                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28034377                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28034377                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28034377                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28034377                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 119805.029915                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 119805.029915                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 119805.029915                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 119805.029915                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         55358                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 7146                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.746711                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        36224                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     15865377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     15865377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   7703746269                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   7703746269                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     15865377                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     15865377                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     15865377                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     15865377                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 67800.756410                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67800.756410                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               70661                       # Transaction distribution
system.membus.trans_dist::ReadResp              70661                       # Transaction distribution
system.membus.trans_dist::WriteReq              27618                       # Transaction distribution
system.membus.trans_dist::WriteResp             27618                       # Transaction distribution
system.membus.trans_dist::Writeback            118375                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4500                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4502                       # Transaction distribution
system.membus.trans_dist::ReadExReq            128454                       # Transaction distribution
system.membus.trans_dist::ReadExResp           128454                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105550                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2122                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       436226                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       543908                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108887                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 652795                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159197                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15455100                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15618561                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      4635456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20254017                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              498                       # Total snoops (count)
system.membus.snoop_fanout::samples            318040                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  318040    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              318040                       # Request fanout histogram
system.membus.reqLayer0.occupancy            86773500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1758500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          1589750000                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer2.occupancy         1594947750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer3.occupancy           38337493                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------