path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.905318                       # Number of seconds simulated
sim_ticks                                2905317504500                       # Number of ticks simulated
final_tick                               2905317504500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 372777                       # Simulator instruction rate (inst/s)
host_op_rate                                   449455                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9630563349                       # Simulator tick rate (ticks/s)
host_mem_usage                                 568288                       # Number of bytes of host memory used
host_seconds                                   301.68                       # Real time elapsed on the host
sim_insts                                   112458065                       # Number of instructions simulated
sim_ops                                     135590016                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1186532                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8969508                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10157576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1186532                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1186532                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7562112                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7579636                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26993                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140668                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                167685                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118158                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               122539                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               408400                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3087273                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3496202                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          408400                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             408400                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2602852                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6032                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2608884                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2602852                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              408400                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3093305                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6105086                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        167685                       # Number of read requests accepted
system.physmem.writeReqs                       122539                       # Number of write requests accepted
system.physmem.readBursts                      167685                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     122539                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10724096                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7592512                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10157576                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7579636                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9872                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9614                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9963                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9595                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18744                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9936                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10635                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11205                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9589                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10033                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9283                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8863                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10202                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10190                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10325                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9515                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7135                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7022                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7742                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7365                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7465                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7289                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7716                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8300                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7184                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7439                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6836                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6804                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7947                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7681                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7752                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6956                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          62                       # Number of times write queue was full causing retry
system.physmem.totGap                    2905317142500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  158113                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 118158                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    166730                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       559                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       263                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2795                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5970                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7196                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7093                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      292                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      129                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        57710                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      317.389430                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     186.497805                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     335.903414                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          20578     35.66%     35.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14720     25.51%     61.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5637      9.77%     70.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3163      5.48%     76.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2413      4.18%     80.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1394      2.42%     83.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1275      2.21%     85.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          905      1.57%     86.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7625     13.21%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          57710                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5794                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.919917                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      588.859232                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5793     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5794                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5794                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.475147                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.526106                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.995822                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            5070     87.50%     87.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              36      0.62%     88.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              58      1.00%     89.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              41      0.71%     89.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             290      5.01%     94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              32      0.55%     95.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               5      0.09%     95.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.14%     95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               5      0.09%     95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               2      0.03%     95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.09%     95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             158      2.73%     98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               7      0.12%     98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.09%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               5      0.09%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               8      0.14%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               5      0.09%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.03%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.03%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             9      0.16%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             9      0.16%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             5      0.09%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             6      0.10%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             5      0.09%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.05%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5794                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4573778750                       # Total ticks spent queuing
system.physmem.totMemAccLat                7715603750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    837820000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       27295.71                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46045.71                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.69                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.61                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.50                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.61                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.46                       # Average write queue length when enqueuing
system.physmem.readRowHits                     138574                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89912                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.70                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.78                       # Row buffer hit rate for writes
system.physmem.avgGap                     10010602.65                       # Average gap between requests
system.physmem.pageHitRate                      79.83                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  209951700                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  111591975                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 639486960                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                313377480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           6673146480.000002                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4797272190                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              415271520                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       13955015310                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        9412509120                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       682622001540                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             719151899205                       # Total energy per rank (pJ)
system.physmem_0.averagePower              247.529538                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           2893187374000                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      780943500                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2837778000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   2838595786500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  24511740750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      7987774000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  30603481750                       # Time in different power states
system.physmem_1.actEnergy                  202104840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  107417475                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 556920000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                305886780                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           6671302560.000002                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             4519380090                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              410434080                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       13655969940                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        9525025920                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       682931246265                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             718886718750                       # Total energy per rank (pJ)
system.physmem_1.averagePower              247.438264                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           2894335381000                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      777927000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2837694000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   2839583336000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  24804588750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      7366436500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  29947522250                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                      9553                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                 9553                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1256                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8297                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples         9553                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0            9553    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total         9553                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7389                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 10013.804304                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean  8464.395211                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  6610.536044                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383         6588     89.16%     89.16% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767          796     10.77%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::81920-98303            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7389                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples   1003066500                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      1003066500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total   1003066500                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6180     83.64%     83.64% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1209     16.36%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7389                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9553                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9553                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7389                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7389                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        16942                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24519779                       # DTB read hits
system.cpu.dtb.read_misses                       8140                       # DTB read misses
system.cpu.dtb.write_hits                    19605270                       # DTB write hits
system.cpu.dtb.write_misses                      1413                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4209                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1622                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24527919                       # DTB read accesses
system.cpu.dtb.write_accesses                19606683                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44125049                       # DTB hits
system.cpu.dtb.misses                            9553                       # DTB misses
system.cpu.dtb.accesses                      44134602                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                      4763                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 4763                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          310                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         4453                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         4763                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            4763    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         4763                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3108                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 10180.341055                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean  8232.055098                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7311.468363                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191         1821     58.59%     58.59% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383          761     24.49%     83.08% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575          524     16.86%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::90112-98303            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::98304-106495            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3108                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   1002711000                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      1002711000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   1002711000                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2798     90.03%     90.03% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.97%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3108                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4763                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         4763                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3108                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3108                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         7871                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    115555925                       # ITB inst hits
system.cpu.itb.inst_misses                       4763                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2849                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                115560688                       # ITB inst accesses
system.cpu.itb.hits                         115555925                       # DTB hits
system.cpu.itb.misses                            4763                       # DTB misses
system.cpu.itb.accesses                     115560688                       # DTB accesses
system.cpu.numPwrStateTransitions                6064                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples          3032                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     887473047.745383                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    17466686250.192787                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         2968     97.89%     97.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10           58      1.91%     99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.03%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.03%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            1      0.03%     99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            3      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 499963437276                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total            3032                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    214499223736                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818280764                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       5810635009                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3032                       # number of quiesce instructions executed
system.cpu.committedInsts                   112458065                       # Number of instructions committed
system.cpu.committedOps                     135590016                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             119895072                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  11290                       # Number of float alu accesses
system.cpu.num_func_calls                     9894802                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     15230859                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    119895072                       # number of integer instructions
system.cpu.num_fp_insts                         11290                       # number of float instructions
system.cpu.num_int_register_reads           218056824                       # number of times the integer registers were read
system.cpu.num_int_register_writes           82647475                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 8578                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            489748178                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            51895154                       # number of times the CC registers were written
system.cpu.num_mem_refs                      45405351                       # number of memory refs
system.cpu.num_load_insts                    24842092                       # Number of load instructions
system.cpu.num_store_insts                   20563259                       # Number of store instructions
system.cpu.num_idle_cycles               5381636561.526148                       # Number of idle cycles
system.cpu.num_busy_cycles               428998447.473852                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.073830                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.926170                       # Percentage of idle cycles
system.cpu.Branches                          25919628                       # Number of branches fetched
system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                  93180053     67.18%     67.18% # Class of executed instruction
system.cpu.op_class::IntMult                   114520      0.08%     67.26% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatMisc                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc               8439      0.01%     67.27% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     67.27% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.27% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.27% # Class of executed instruction
system.cpu.op_class::MemRead                 24839384     17.91%     85.17% # Class of executed instruction
system.cpu.op_class::MemWrite                20554681     14.82%     99.99% # Class of executed instruction
system.cpu.op_class::FloatMemRead                2708      0.00%     99.99% # Class of executed instruction
system.cpu.op_class::FloatMemWrite               8578      0.01%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  138710700                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            821158                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.816175                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            43232098                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            821670                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             52.614916                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1078145500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.816175                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999641                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999641                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          356                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           96                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         177104923                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        177104923                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     23110979                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23110979                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18822589                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18822589                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       392473                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        392473                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443107                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443107                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460141                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460141                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41933568                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41933568                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42326041                       # number of overall hits
system.cpu.dcache.overall_hits::total        42326041                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       401142                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        401142                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       298882                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       298882                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       118684                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       118684                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22807                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22807                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data       700024                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         700024                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       818708                       # number of overall misses
system.cpu.dcache.overall_misses::total        818708                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   6437634500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   6437634500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14441729500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14441729500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    297474000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    297474000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       166000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       166000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  20879364000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  20879364000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  20879364000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  20879364000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23512121                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23512121                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19121471                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19121471                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       511157                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       511157                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465914                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465914                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460143                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460143                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42633592                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42633592                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     43144749                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     43144749                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017061                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.017061                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015631                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015631                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.232187                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.232187                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048951                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048951                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.016420                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.016420                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.018976                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.018976                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.268444                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.268444                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48319.167765                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48319.167765                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.100802                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.100802                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29826.640229                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29826.640229                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25502.821519                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25502.821519                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks       685618                       # number of writebacks
system.cpu.dcache.writebacks::total            685618                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          708                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          708                       # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14278                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14278                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          708                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          708                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          708                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          708                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       400434                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       400434                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298882                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298882                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116661                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       116661                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8529                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8529                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       699316                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       699316                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       815977                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       815977                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6011986000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6011986000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14142847500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  14142847500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1587073500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1587073500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    118989500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    118989500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       164000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       164000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20154833500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  20154833500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  21741907000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  21741907000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6284829000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6284829000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6284829000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6284829000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017031                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017031                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015631                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015631                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228229                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228229                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018306                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018306                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016403                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016403                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018913                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.018913                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15013.675162                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15013.675162                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47319.167765                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47319.167765                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13604.147916                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13604.147916                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.166608                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.166608                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28820.781306                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28820.781306                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26645.244903                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26645.244903                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           1700061                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.693087                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           113855346                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1700573                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             66.951166                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       26307743500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.693087                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997447                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997447                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          212                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         117256504                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        117256504                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    113855346                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113855346                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113855346                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113855346                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113855346                       # number of overall hits
system.cpu.icache.overall_hits::total       113855346                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1700579                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1700579                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1700579                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1700579                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1700579                       # number of overall misses
system.cpu.icache.overall_misses::total       1700579                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  24045189500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  24045189500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  24045189500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  24045189500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  24045189500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  24045189500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    115555925                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    115555925                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    115555925                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    115555925                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    115555925                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    115555925                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014717                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014717                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014717                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014717                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014717                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014717                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.413400                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14139.413400                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.413400                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14139.413400                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.413400                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14139.413400                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      1700061                       # number of writebacks
system.cpu.icache.writebacks::total           1700061                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1700579                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1700579                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1700579                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1700579                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1700579                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1700579                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22344610500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  22344610500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22344610500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  22344610500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22344610500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  22344610500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    745203000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    745203000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    745203000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    745203000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014717                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014717                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014717                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014717                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014717                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014717                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.413400                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.413400                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.413400                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.413400                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.413400                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.413400                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements            88597                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65011.992500                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4854150                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           154024                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            31.515543                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     147534324000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.050681                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.041157                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  9634.970202                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.930460                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000047                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.147018                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.844939                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.992004                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65422                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           76                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4349                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        60996                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998260                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         40276407                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        40276407                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         5063                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2684                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total           7747                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       685618                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       685618                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1667781                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1667781                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         2789                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         2789                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       167649                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       167649                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1682585                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1682585                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       513552                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       513552                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         5063                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2684                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1682585                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       681201                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2371533                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         5063                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2684                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1682585                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       681201                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2371533                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           18                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           18                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       128426                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       128426                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        17978                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        17978                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        12072                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        12072                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        17978                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       140498                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        158485                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        17978                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       140498                       # number of overall misses
system.cpu.l2cache.overall_misses::total       158485                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1154000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       180000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total      1334000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       525000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       525000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       161000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       161000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  11900828000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  11900828000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2066597500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2066597500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1519988500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1519988500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1154000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       180000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2066597500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13420816500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  15488748000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1154000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       180000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2066597500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13420816500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  15488748000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         5070                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2686                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         7756                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       685618                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       685618                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1667781                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1667781                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2807                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2807                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       296075                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       296075                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1700563                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1700563                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       525624                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       525624                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         5070                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2686                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1700563                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       821699                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2530018                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         5070                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2686                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1700563                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       821699                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2530018                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001381                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000745                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.001160                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.006413                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.006413                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.433762                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.433762                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010572                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010572                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.022967                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.022967                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001381                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000745                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010572                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.170985                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.062642                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001381                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000745                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010572                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.170985                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.062642                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        90000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92666.812016                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92666.812016                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114951.468461                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114951.468461                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125910.246852                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125910.246852                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        90000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114951.468461                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95523.185383                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97730.056472                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        90000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114951.468461                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95523.185383                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97730.056472                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        81968                       # number of writebacks
system.cpu.l2cache.writebacks::total            81968                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           18                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       128426                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       128426                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17978                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17978                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12072                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12072                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        17978                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       140498                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       158485                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        17978                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       140498                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       158485                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1084000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       160000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1244000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       345000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       345000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       141000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       141000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  10616568000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  10616568000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1886817500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1886817500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1399268500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1399268500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1084000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       160000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1886817500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12015836500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  13903898000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1084000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       160000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1886817500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12015836500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  13903898000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    632428000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5895484000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6527912000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    632428000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5895484000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   6527912000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001381                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000745                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001160                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.006413                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.006413                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.433762                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.433762                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010572                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010572                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.022967                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.022967                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001381                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000745                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010572                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170985                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.062642                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001381                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000745                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010572                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170985                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.062642                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        80000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82666.812016                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82666.812016                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104951.468461                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104951.468461                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115910.246852                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115910.246852                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        80000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104951.468461                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85523.185383                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87730.056472                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        80000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104951.468461                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85523.185383                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87730.056472                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests      5065624                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2543364                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        39292                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          222                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          222                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq          67226                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2293620                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       767586                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1700061                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       142169                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2807                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2809                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       296075                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       296075                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1700579                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       525821                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq         4351                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5119247                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2587819                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        11902                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        22920                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7741888                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    217676024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96663645                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        10744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        20280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          314370693                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      112662                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               5336440                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2713047                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.021691                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.145674                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2654197     97.83%     97.83% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              58850      2.17%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2713047                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4970034000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       347377                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2559890500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1278885500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       9216000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      17850000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30159                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30159                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72868                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72868                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178346                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2320912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2320912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480037                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46336000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                97000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                15500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               642500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6289000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36469500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187558131                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36692000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36400                       # number of replacements
system.iocache.tags.tagsinuse                1.079865                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36416                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         310617748000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.079865                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067492                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067492                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               327906                       # Number of tag accesses
system.iocache.tags.data_accesses              327906                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          210                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              210                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36434                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36434                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36434                       # number of overall misses
system.iocache.overall_misses::total            36434                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     34063377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     34063377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4369997754                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4369997754                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4404061131                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4404061131                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4404061131                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4404061131                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          210                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            210                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36434                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36434                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36434                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36434                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 162206.557143                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162206.557143                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120638.188880                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120638.188880                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120877.782593                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120877.782593                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120877.782593                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120877.782593                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           208                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    4                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs           52                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          210                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          210                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36434                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36434                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36434                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36434                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     23563377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     23563377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2556779983                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2556779983                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2580343360                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2580343360                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2580343360                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2580343360                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112206.557143                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112206.557143                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70582.486280                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70582.486280                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70822.401054                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70822.401054                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70822.401054                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70822.401054                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests        319998                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       129556                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          458                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70429                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       118158                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6839                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              128                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            128316                       # Transaction distribution
system.membus.trans_dist::ReadExResp           128316                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30269                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       433106                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       540698                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72849                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72849                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 613547                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15420092                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15583445                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17900565                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              474                       # Total snoops (count)
system.membus.snoopTraffic                      30208                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            262688                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.018375                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.134305                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  257861     98.16%     98.16% # Request fanout histogram
system.membus.snoop_fanout::1                    4827      1.84%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              262688                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90466500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1724500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           822811335                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          948647750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1085623                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905317504500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------