blob: 73585121bf47b865df6c93b90351a6d8d22f6710 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.603665 # Number of seconds simulated
sim_ticks 2603664815000 # Number of ticks simulated
final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 536000 # Simulator instruction rate (inst/s)
host_op_rate 682052 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23183028791 # Simulator tick rate (ticks/s)
host_mem_usage 404656 # Number of bytes of host memory used
host_seconds 112.31 # Real time elapsed on the host
sim_insts 60197643 # Number of instructions simulated
sim_ops 76600583 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15494089 # Total number of read requests seen
system.physmem.writeReqs 811479 # Total number of write requests seen
system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 991621696 # Total number of bytes read from memory
system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2603660455000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 152013 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 754018 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 57461 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests
system.physmem.totBusLat 77468765000 # Total cycles spent in databus access
system.physmem.totBankLat 17445216250 # Total cycles spent in bank access
system.physmem.avgQLat 22041.64 # Average queueing delay per request
system.physmem.avgBankLat 1125.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 28167.59 # Average memory access latency
system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.13 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
system.physmem.avgWrQLen 12.39 # Average write queue length over time
system.physmem.readRowHits 15418905 # Number of row buffer hits during reads
system.physmem.writeRowHits 794060 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
system.physmem.avgGap 159679.22 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14995667 # DTB read hits
system.cpu.dtb.read_misses 7332 # DTB read misses
system.cpu.dtb.write_hits 11230865 # DTB write hits
system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 15002999 # DTB read accesses
system.cpu.dtb.write_accesses 11233068 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26226532 # DTB hits
system.cpu.dtb.misses 9535 # DTB misses
system.cpu.dtb.accesses 26236067 # DTB accesses
system.cpu.itb.inst_hits 61491584 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 61496055 # ITB inst accesses
system.cpu.itb.hits 61491584 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61496055 # DTB accesses
system.cpu.numCycles 5207329630 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60197643 # Number of instructions committed
system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2139730 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls
system.cpu.num_int_insts 68868344 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read
system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27393912 # number of memory refs
system.cpu.num_load_insts 15659685 # Number of load instructions
system.cpu.num_store_insts 11734227 # Number of store instructions
system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles
system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles
system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.879355 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
system.cpu.icache.replacements 855486 # number of replacements
system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use
system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits
system.cpu.icache.overall_hits::total 60635586 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses
system.cpu.icache.overall_misses::total 855998 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855998 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 855998 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 855998 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 855998 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 855998 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 855998 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9857308000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9857308000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9857308000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9857308000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9857308000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9857308000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11515.573635 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11515.573635 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 61906 # number of replacements
system.cpu.l2cache.tagsinuse 50893.814517 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1682715 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 127287 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.219850 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2553152311000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 37867.919206 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 6996.279505 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6025.728892 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.577819 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.106755 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 843761 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 370335 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226345 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 596039 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 596039 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 114427 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 114427 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 843761 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 484762 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1340772 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 843761 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 484762 # number of overall hits
system.cpu.l2cache.overall_hits::total 1340772 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143041 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153648 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143041 # number of overall misses
system.cpu.l2cache.overall_misses::total 153648 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 562062000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534519000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1097047500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075862000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6075862000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 562062000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6610381000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 7172909500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 562062000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6610381000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 7172909500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854360 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380193 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1246810 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 596039 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 596039 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247610 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247610 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 854360 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627803 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494420 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 854360 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627803 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494420 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012406 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025929 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537874 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.537874 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012406 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.102814 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012406 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.102814 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53029.719785 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54221.850274 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53606.034693 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45620.402003 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45620.402003 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46684.040795 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46684.040795 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks
system.cpu.l2cache.writebacks::total 57461 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143041 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 153648 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143041 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 153648 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253760 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113756 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430665051 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411778800 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 842811367 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28850324 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28850324 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4437954325 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4437954325 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253760 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113756 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430665051 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4849733125 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5280765692 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253760 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113756 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430665051 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4849733125 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5280765692 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209122550 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688445815 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166897568365 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025929 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537874 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537874 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102814 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102814 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40632.611661 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41771.028606 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41183.062155 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10034.895304 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10034.895304 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33322.228250 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33322.228250 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 627291 # number of replacements
system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use
system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits
system.cpu.dcache.overall_hits::total 23168189 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses
system.cpu.dcache.overall_misses::total 619303 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks
system.cpu.dcache.writebacks::total 596039 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|