blob: 4a0324f9e8fcff99b2a80e8d5ac218b727d77def (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
|
---------- Begin Simulation Statistics ----------
sim_seconds 2.629150 # Number of seconds simulated
sim_ticks 2629149747000 # Number of ticks simulated
final_tick 2629149747000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 556259 # Simulator instruction rate (inst/s)
host_op_rate 707830 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 24290841486 # Simulator tick rate (ticks/s)
host_mem_usage 380276 # Number of bytes of host memory used
host_seconds 108.24 # Real time elapsed on the host
sim_insts 60207390 # Number of instructions simulated
sim_ops 76612873 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 705696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9115408 # Number of bytes read from this memory
system.physmem.bytes_read::total 134077744 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 705696 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705696 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3736256 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6752328 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17229 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142462 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15691729 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812397 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47261004 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 97 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 268412 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3467055 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50996618 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 268412 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 268412 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1421089 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1147166 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2568255 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1421089 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47261004 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 97 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 268412 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4614222 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53564873 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cpu.l2cache.replacements 62933 # number of replacements
system.cpu.l2cache.tagsinuse 51862.510726 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1683379 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 128318 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.118806 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2576532162000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 38450.903251 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.914018 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000670 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 7005.048584 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6403.644203 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.586714 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000044 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.106889 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.097712 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.791359 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8836 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 844195 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 370308 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226888 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 596416 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 596416 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 113846 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 113846 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8836 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 844195 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 484154 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1340734 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8836 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 844195 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 484154 # number of overall hits
system.cpu.l2cache.overall_hits::total 1340734 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10613 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 10261 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 20880 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2845 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2845 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133824 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133824 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 4 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10613 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 144085 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 154704 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 4 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10613 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 144085 # number of overall misses
system.cpu.l2cache.overall_misses::total 154704 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 208000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 104000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 553137500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534185000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1087634500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6961477000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6961477000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 208000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 104000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 553137500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7495662000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 8049111500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 208000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 104000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 553137500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7495662000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 8049111500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8840 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854808 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380569 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1247768 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 596416 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 596416 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2871 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2871 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247670 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247670 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8840 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 854808 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 628239 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1495438 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8840 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 854808 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 628239 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1495438 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000452 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012416 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016734 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990944 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990944 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540332 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.540332 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000452 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012416 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229347 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103451 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000452 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012416 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229347 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103451 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52118.863658 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52059.740766 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52089.774904 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 365.553603 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 365.553603 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52019.645206 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52019.645206 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52029.110430 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52118.863658 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52022.500607 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52029.110430 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 58379 # number of writebacks
system.cpu.l2cache.writebacks::total 58379 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10613 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10261 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 20880 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2845 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2845 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133824 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133824 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10613 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 144085 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 154704 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10613 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 144085 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154704 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 425775500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411049000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 837064500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114083000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114083000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5355569000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5355569000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 80000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425775500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5766618000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6192633500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 80000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425775500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5766618000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6192633500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167018677500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31852864000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31852864000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198606701500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198871541500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026962 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016734 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990944 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990944 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540332 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540332 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.103451 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000452 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012416 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229347 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.103451 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40089.295977 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40099.472759 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40019.495756 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.298313 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40022.334039 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40028.916512 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14998169 # DTB read hits
system.cpu.dtb.read_misses 7372 # DTB read misses
system.cpu.dtb.write_hits 11231565 # DTB write hits
system.cpu.dtb.write_misses 2270 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 15005541 # DTB read accesses
system.cpu.dtb.write_accesses 11233835 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26229734 # DTB hits
system.cpu.dtb.misses 9642 # DTB misses
system.cpu.dtb.accesses 26239376 # DTB accesses
system.cpu.itb.inst_hits 61501359 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 61505830 # ITB inst accesses
system.cpu.itb.hits 61501359 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61505830 # DTB accesses
system.cpu.numCycles 5258299494 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60207390 # Number of instructions committed
system.cpu.committedOps 76612873 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68878830 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2140176 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7948958 # number of instructions that are conditional controls
system.cpu.num_int_insts 68878830 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394820534 # number of times the integer registers were read
system.cpu.num_int_register_writes 74191435 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27397151 # number of memory refs
system.cpu.num_load_insts 15662227 # Number of load instructions
system.cpu.num_store_insts 11734924 # Number of store instructions
system.cpu.num_idle_cycles 4567780450.602262 # Number of idle cycles
system.cpu.num_busy_cycles 690519043.397737 # Number of busy cycles
system.cpu.not_idle_fraction 0.131320 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.868680 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83013 # number of quiesce instructions executed
system.cpu.icache.replacements 855930 # number of replacements
system.cpu.icache.tagsinuse 510.898307 # Cycle average of tags in use
system.cpu.icache.total_refs 60644917 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 856442 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.810302 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 19819985000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.898307 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.997848 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997848 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 60644917 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60644917 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60644917 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60644917 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60644917 # number of overall hits
system.cpu.icache.overall_hits::total 60644917 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856442 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856442 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856442 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856442 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856442 # number of overall misses
system.cpu.icache.overall_misses::total 856442 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12566277500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12566277500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12566277500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12566277500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12566277500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12566277500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61501359 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61501359 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61501359 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61501359 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61501359 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61501359 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14672.654424 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14672.654424 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856442 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 856442 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 856442 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 856442 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856442 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856442 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9995044500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9995044500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9995044500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9995044500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9995044500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9995044500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.427770 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.427770 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.427770 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.427770 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 627727 # number of replacements
system.cpu.dcache.tagsinuse 511.877273 # Cycle average of tags in use
system.cpu.dcache.total_refs 23657788 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 628239 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.657306 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 661351000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.877273 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999760 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999760 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13196825 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13196825 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9973191 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9973191 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236701 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236701 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 248200 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 248200 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23170016 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23170016 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23170016 # number of overall hits
system.cpu.dcache.overall_hits::total 23170016 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 369069 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 369069 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250541 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250541 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619610 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619610 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619610 # number of overall misses
system.cpu.dcache.overall_misses::total 619610 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5742174000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5742174000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9260838000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9260838000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170995500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 170995500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 15003012000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 15003012000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 15003012000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 15003012000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13565894 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13565894 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10223732 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10223732 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248201 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 248201 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 248200 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 248200 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23789626 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23789626 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23789626 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23789626 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027206 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027206 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024506 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024506 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026045 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026045 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026045 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026045 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15558.537834 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15558.537834 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36963.363282 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36963.363282 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14869.173913 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14869.173913 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24213.637611 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24213.637611 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24213.637611 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 596416 # number of writebacks
system.cpu.dcache.writebacks::total 596416 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 369069 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 369069 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250541 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250541 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 619610 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619610 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619610 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619610 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4633803000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4633803000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509109000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509109000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136482000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136482000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13142912000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13142912000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13142912000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13142912000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41013343500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41013343500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027206 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027206 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026045 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026045 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026045 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11868 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11868 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1358668189629 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|