path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.909596                       # Number of seconds simulated
sim_ticks                                2909596171500                       # Number of ticks simulated
final_tick                               2909596171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 322522                       # Simulator instruction rate (inst/s)
host_op_rate                                   388861                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             8344730622                       # Simulator tick rate (ticks/s)
host_mem_usage                                 560756                       # Number of bytes of host memory used
host_seconds                                   348.67                       # Real time elapsed on the host
sim_insts                                   112455206                       # Number of instructions simulated
sim_ops                                     135585876                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1186404                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8901796                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10089736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1186404                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1186404                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7511872                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7529396                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              26991                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             139610                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166625                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117373                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121754                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               407756                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3059461                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3467744                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          407756                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             407756                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2581758                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                6023                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2587780                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2581758                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              407756                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3065484                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6055525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166625                       # Number of read requests accepted
system.physmem.writeReqs                       121754                       # Number of write requests accepted
system.physmem.readBursts                      166625                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     121754                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10656448                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7541952                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10089736                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7529396                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          47113                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10077                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10695                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10661                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18797                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9659                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9663                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10485                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9973                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9232                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8679                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9817                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10379                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9722                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8282                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8171                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7489                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7659                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6695                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7534                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7264                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
system.physmem.totGap                    2909595814500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  157053                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117373                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    165628                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       256                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7774                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9310                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6775                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        58778                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      309.611351                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.749688                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.493771                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21450     36.49%     36.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14701     25.01%     61.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6086     10.35%     71.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3214      5.47%     77.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2550      4.34%     81.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1476      2.51%     84.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1054      1.79%     85.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1089      1.85%     87.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7158     12.18%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          58778                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5758                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.915596                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      590.311059                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5757     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5758                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5758                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.465960                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.711564                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.116644                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4961     86.16%     86.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              87      1.51%     87.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              33      0.57%     88.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             172      2.99%     91.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              23      0.40%     91.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             160      2.78%     94.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              50      0.87%     95.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.10%     95.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               7      0.12%     95.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              22      0.38%     95.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.03%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.10%     96.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             163      2.83%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               3      0.05%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              10      0.17%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              20      0.35%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            16      0.28%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5758                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1616458000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4738464250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    832535000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9708.05                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28458.05                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.59                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
system.physmem.readRowHits                     136072                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89499                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.72                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.93                       # Row buffer hit rate for writes
system.physmem.avgGap                     10089485.76                       # Average gap between requests
system.physmem.pageHitRate                      79.32                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  230958000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  126018750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 702124800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                392882400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           190040226480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            90366604425                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1666484751750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1948343566605                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.628332                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2772164122000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     97157580000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     40267816750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  213403680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  116440500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 596622000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                370740240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           190040226480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            88072375230                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1668497233500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1947907041630                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.478302                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2775541834250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     97157580000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     36896609250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                      9546                       # Table walker walks requested
system.cpu.dtb.walker.walksShort                 9546                       # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1         1255                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2         8291                       # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples         9546                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0            9546    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total         9546                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples         7382                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev  8540.848722                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767         7377     99.93%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total         7382                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples   1638910500                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      1638910500    100.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total   1638910500                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K          6174     83.64%     83.64% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M          1208     16.36%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total         7382                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data         9546                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total         9546                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7382                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7382                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total        16928                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     24520178                       # DTB read hits
system.cpu.dtb.read_misses                       8124                       # DTB read misses
system.cpu.dtb.write_hits                    19606457                       # DTB write hits
system.cpu.dtb.write_misses                      1422                       # DTB write misses
system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     4272                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   1650                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 24528302                       # DTB read accesses
system.cpu.dtb.write_accesses                19607879                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          44126635                       # DTB hits
system.cpu.dtb.misses                            9546                       # DTB misses
system.cpu.dtb.accesses                      44136181                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                      4763                       # Table walker walks requested
system.cpu.itb.walker.walksShort                 4763                       # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1          310                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2         4453                       # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples         4763                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0            4763    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total         4763                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples         3108                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12722.007722                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev  7865.701982                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383         2410     77.54%     77.54% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767          696     22.39%     99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total         3108                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   1638383000                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      1638383000    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   1638383000                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K          2798     90.03%     90.03% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M           310      9.97%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total         3108                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4763                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total         4763                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3108                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total         3108                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total         7871                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    115552414                       # ITB inst hits
system.cpu.itb.inst_misses                       4763                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           64                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2913                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                115557177                       # ITB inst accesses
system.cpu.itb.hits                         115552414                       # DTB hits
system.cpu.itb.misses                            4763                       # DTB misses
system.cpu.itb.accesses                     115557177                       # DTB accesses
system.cpu.numCycles                       5819192343                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
system.cpu.committedInsts                   112455206                       # Number of instructions committed
system.cpu.committedOps                     135585876                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             119891340                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
system.cpu.num_func_calls                     9892021                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     15230391                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    119891340                       # number of integer instructions
system.cpu.num_fp_insts                         11161                       # number of float instructions
system.cpu.num_int_register_reads           218059811                       # number of times the integer registers were read
system.cpu.num_int_register_writes           82644916                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            489735153                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            51893214                       # number of times the CC registers were written
system.cpu.num_mem_refs                      45407055                       # number of memory refs
system.cpu.num_load_insts                    24842618                       # Number of load instructions
system.cpu.num_store_insts                   20564437                       # Number of store instructions
system.cpu.num_idle_cycles               5379072985.844151                       # Number of idle cycles
system.cpu.num_busy_cycles               440119357.155849                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.075632                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.924368                       # Percentage of idle cycles
system.cpu.Branches                          25916470                       # Number of branches fetched
system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                  93173703     67.17%     67.18% # Class of executed instruction
system.cpu.op_class::IntMult                   114388      0.08%     67.26% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc               8453      0.01%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
system.cpu.op_class::MemRead                 24842618     17.91%     85.17% # Class of executed instruction
system.cpu.op_class::MemWrite                20564437     14.83%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  138705936                       # Class of executed instruction
system.cpu.dcache.tags.replacements            819217                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.702336                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            43235406                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            819729                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             52.743536                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1736147500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.702336                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999419                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999419                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         177109321                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        177109321                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     23112521                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        23112521                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18823879                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18823879                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       392783                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        392783                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       443242                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       443242                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       460216                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       460216                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      41936400                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         41936400                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42329183                       # number of overall hits
system.cpu.dcache.overall_hits::total        42329183                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       399911                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        399911                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       298704                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       298704                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       118377                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       118377                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        22757                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        22757                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data       698615                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         698615                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       816992                       # number of overall misses
system.cpu.dcache.overall_misses::total        816992                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   6486417000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   6486417000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  19109109000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  19109109000                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    294489000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    294489000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  25595526000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  25595526000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  25595526000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  25595526000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     23512432                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     23512432                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19122583                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19122583                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       511160                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       511160                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465999                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       465999                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       460218                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       460218                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42635015                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42635015                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     43146175                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     43146175                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017008                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.017008                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015620                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015620                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231585                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.231585                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048835                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048835                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.016386                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.018935                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.018935                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36637.527107                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31328.979966                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       683842                       # number of writebacks
system.cpu.dcache.writebacks::total            683842                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          930                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          930                       # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14247                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        14247                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          930                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          930                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          930                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          930                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       398981                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       398981                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298704                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       298704                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116321                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       116321                       # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8510                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total         8510                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       697685                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       697685                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       814006                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       814006                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6058107000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6058107000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18810405000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  18810405000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1614233500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1614233500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115353500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115353500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24868512000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  24868512000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26482745500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26482745500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6278172000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6278172000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089977500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089977500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11368149500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11368149500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016969                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016969                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015620                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015620                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227563                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227563                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018262                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018262                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016364                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016364                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018866                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.018866                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1695565                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.436866                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           113856331                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1696077                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             67.129223                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       29070355500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.436866                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996947                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         117248497                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        117248497                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    113856331                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113856331                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113856331                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113856331                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113856331                       # number of overall hits
system.cpu.icache.overall_hits::total       113856331                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1696083                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1696083                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1696083                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1696083                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1696083                       # number of overall misses
system.cpu.icache.overall_misses::total       1696083                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  24267960000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  24267960000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  24267960000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  24267960000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  24267960000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  24267960000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    115552414                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    115552414                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    115552414                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    115552414                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    115552414                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    115552414                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014678                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014678                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014678                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014678                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014678                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014678                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14308.238453                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14308.238453                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks      1695565                       # number of writebacks
system.cpu.icache.writebacks::total           1695565                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1696083                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1696083                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1696083                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1696083                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1696083                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1696083                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22571877000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  22571877000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22571877000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  22571877000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22571877000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  22571877000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1142541000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1142541000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1142541000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   1142541000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014678                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014678                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014678                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014678                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014678                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014678                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            87562                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64865.195753                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4544223                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           152797                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            29.740263                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.799338                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012652                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  9701.731977                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4962.980293                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.765940                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000058                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.148037                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.075729                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989764                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        65230                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6849                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56201                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995331                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         40509810                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        40509810                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7810                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4039                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          11849                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks       683842                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       683842                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1664795                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1664795                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           23                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       167026                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       167026                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1678074                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1678074                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       511640                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       511640                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         7810                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         4039                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1678074                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       678666                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2368589                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         7810                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         4039                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1678074                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       678666                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2368589                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2740                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2740                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       128915                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       128915                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        17976                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        17976                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        12172                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        12172                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        17976                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141087                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        159072                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        17976                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141087                       # number of overall misses
system.cpu.l2cache.overall_misses::total       159072                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       957500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       266000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total      1223500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1857500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      1857500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       159000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16383348000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16383348000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2349142000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2349142000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1612524000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   1612524000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       957500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       266000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2349142000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  17995872000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  20346237500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       957500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       266000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2349142000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  17995872000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  20346237500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7817                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4041                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        11858                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks       683842                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       683842                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1664795                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1664795                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2763                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2763                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       295941                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       295941                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1696050                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1696050                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       523812                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       523812                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7817                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         4041                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1696050                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       819753                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2527661                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7817                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         4041                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1696050                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       819753                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2527661                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000495                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.000759                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991676                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991676                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.435610                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.435610                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010599                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010599                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023237                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023237                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000495                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010599                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.172109                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.062932                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000495                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010599                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.172109                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.062932                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       133000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   677.919708                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   677.919708                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130682.131731                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132478.146566                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        81183                       # number of writebacks
system.cpu.l2cache.writebacks::total            81183                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2740                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2740                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       128915                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       128915                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17976                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17976                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12172                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12172                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        17976                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141087                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       159072                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        17976                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141087                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       159072                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       887500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       246000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1133500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    194003500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    194003500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       139000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15094198000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15094198000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2169382000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2169382000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1490804000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1490804000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       887500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       246000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2169382000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16585002000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  18755517500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       887500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       246000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2169382000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16585002000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  18755517500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888826500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6918592500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772574000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772574000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10661400500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11691166500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000759                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991676                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991676                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.435610                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.435610                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010599                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023237                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023237                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172109                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.062932                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172109                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.062932                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5052537                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536723                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38125                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops          581                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq          67213                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2287321                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       801217                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1664795                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       134627                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2763                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2765                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       295941                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       295941                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1696083                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       524040                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5074972                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2574565                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13257                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        25654                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7688448                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    215130168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96426845                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16164                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        31268                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          311604445                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      175875                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      2773837                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.020867                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.142939                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2715955     97.91%     97.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              57882      2.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2773837                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4957294000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       380876                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2553146500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1275944500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       9216000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      17837000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46338000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                97000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               644500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6287500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36469500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           186221548                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36418                       # number of replacements
system.iocache.tags.tagsinuse                1.084130                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         313812613000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.084130                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067758                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067758                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328068                       # Number of tag accesses
system.iocache.tags.data_accesses              328068                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          228                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          228                       # number of demand (read+write) misses
system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          228                       # number of overall misses
system.iocache.overall_misses::total              228                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28228376                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28228376                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4717653172                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4717653172                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28228376                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28228376                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28228376                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28228376                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          228                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             228                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          228                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            228                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123808.666667                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123808.666667                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123808.666667                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123808.666667                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123808.666667                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           910                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   81                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.234568                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          228                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16828376                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16828376                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2906453172                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2906453172                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16828376                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16828376                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16828376                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16828376                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 73808.666667                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 73808.666667                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70545                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       117373                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6392                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4499                       # Transaction distribution
system.membus.trans_dist::ReadExReq            127158                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127158                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30385                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       438817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total       546409                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 655303                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15302012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15465365                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17782485                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              492                       # Total snoops (count)
system.membus.snoop_fanout::samples            389997                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  389997    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              389997                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90470000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1726000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           823068661                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          952238748                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64113741                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks

---------- End Simulation Statistics   ----------