path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.616536                       # Number of seconds simulated
sim_ticks                                2616536483000                       # Number of ticks simulated
final_tick                               2616536483000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 552343                       # Simulator instruction rate (inst/s)
host_op_rate                                   702879                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            24008008080                       # Simulator tick rate (ticks/s)
host_mem_usage                                 395660                       # Number of bytes of host memory used
host_seconds                                   108.99                       # Real time elapsed on the host
sim_insts                                    60197580                       # Number of instructions simulated
sim_ops                                      76603973                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            703904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9089744                       # Number of bytes read from this memory
system.physmem.bytes_read::total            132477488                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       703904                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          703904                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      3706176                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6722248                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              17201                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             142061                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              15494693                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           57909                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               811927                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        46887705                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               269021                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3473960                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50630858                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          269021                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             269021                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1416443                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1152696                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2569140                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1416443                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       46887705                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              269021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             4626657                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               53199998                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                      15494693                       # Number of read requests accepted
system.physmem.writeReqs                       811927                       # Number of write requests accepted
system.physmem.readBursts                    15494693                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     811927                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                991555264                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    105088                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6843648                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                 132477488                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6722248                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1642                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                  704975                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4515                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0              967983                       # Per bank write bursts
system.physmem.perBankRdBursts::1              967714                       # Per bank write bursts
system.physmem.perBankRdBursts::2              967672                       # Per bank write bursts
system.physmem.perBankRdBursts::3              967769                       # Per bank write bursts
system.physmem.perBankRdBursts::4              974609                       # Per bank write bursts
system.physmem.perBankRdBursts::5              968229                       # Per bank write bursts
system.physmem.perBankRdBursts::6              967807                       # Per bank write bursts
system.physmem.perBankRdBursts::7              967736                       # Per bank write bursts
system.physmem.perBankRdBursts::8              968546                       # Per bank write bursts
system.physmem.perBankRdBursts::9              968137                       # Per bank write bursts
system.physmem.perBankRdBursts::10             967949                       # Per bank write bursts
system.physmem.perBankRdBursts::11             967746                       # Per bank write bursts
system.physmem.perBankRdBursts::12             967851                       # Per bank write bursts
system.physmem.perBankRdBursts::13             967741                       # Per bank write bursts
system.physmem.perBankRdBursts::14             967766                       # Per bank write bursts
system.physmem.perBankRdBursts::15             967796                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6610                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6410                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6422                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6344                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6906                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7096                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6901                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6892                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7193                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6845                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6667                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6550                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6596                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6392                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6532                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6576                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2616532122000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    6652                       # Read request sizes (log2)
system.physmem.readPktSize::3                15335424                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  152617                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  57909                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1265330                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                   1118297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                   1122310                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                   3740106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                   2667387                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                   2661184                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                   2667924                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     52364                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     54482                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                     20799                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                    20747                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                    20660                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                    20420                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                    20349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                    20284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                    20256                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      152                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        89727                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean    11127.069087                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean    1028.273701                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev   16706.873806                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71          23194     25.85%     25.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135        14559     16.23%     42.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199         2860      3.19%     45.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263         2118      2.36%     47.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327         1356      1.51%     49.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391         1216      1.36%     50.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455          947      1.06%     51.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519         1180      1.32%     52.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583          650      0.72%     53.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647          587      0.65%     54.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711          521      0.58%     54.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775          703      0.78%     55.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839          336      0.37%     55.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903          268      0.30%     56.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967          216      0.24%     56.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031          509      0.57%     57.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095          151      0.17%     57.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159          159      0.18%     57.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223          138      0.15%     57.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287          229      0.26%     57.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351          105      0.12%     57.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415         2288      2.55%     60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479          101      0.11%     60.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543          246      0.27%     60.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607           69      0.08%     60.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671           53      0.06%     61.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735           41      0.05%     61.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799          188      0.21%     61.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863           32      0.04%     61.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927           26      0.03%     61.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991           28      0.03%     61.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055          180      0.20%     61.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119           16      0.02%     61.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183           28      0.03%     61.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247           12      0.01%     61.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311          150      0.17%     61.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375           18      0.02%     61.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439           17      0.02%     61.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503           27      0.03%     61.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567          112      0.12%     62.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631           10      0.01%     62.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695           11      0.01%     62.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759           11      0.01%     62.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823          157      0.17%     62.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887           13      0.01%     62.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951           16      0.02%     62.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015           13      0.01%     62.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079          359      0.40%     62.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143           14      0.02%     62.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207           18      0.02%     62.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271           14      0.02%     62.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335          100      0.11%     62.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399           13      0.01%     62.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463           18      0.02%     62.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527            9      0.01%     62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591           89      0.10%     62.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655           10      0.01%     62.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719           18      0.02%     63.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783           39      0.04%     63.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847          147      0.16%     63.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911           12      0.01%     63.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975           13      0.01%     63.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039           10      0.01%     63.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103          177      0.20%     63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167            8      0.01%     63.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231           12      0.01%     63.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295            6      0.01%     63.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359          149      0.17%     63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423            6      0.01%     63.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487           10      0.01%     63.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551            9      0.01%     63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615          161      0.18%     63.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679            7      0.01%     63.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743            6      0.01%     63.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807           11      0.01%     63.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871           82      0.09%     63.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935            7      0.01%     63.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999           13      0.01%     63.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063            7      0.01%     63.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127          497      0.55%     64.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191           11      0.01%     64.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255            8      0.01%     64.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5319            7      0.01%     64.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383           18      0.02%     64.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447           18      0.02%     64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511           64      0.07%     64.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575           10      0.01%     64.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639          138      0.15%     64.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5703            1      0.00%     64.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831            1      0.00%     64.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895           89      0.10%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5959            1      0.00%     64.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023            2      0.00%     64.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151          276      0.31%     65.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215            1      0.00%     65.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407           33      0.04%     65.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535            3      0.00%     65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599            1      0.00%     65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663          146      0.16%     65.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727            1      0.00%     65.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919           83      0.09%     65.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047            5      0.01%     65.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175          526      0.59%     66.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7239            1      0.00%     66.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431           79      0.09%     66.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559            1      0.00%     66.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623            1      0.00%     66.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687           37      0.04%     66.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7879            1      0.00%     66.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943           10      0.01%     66.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071            2      0.00%     66.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199          407      0.45%     66.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8327            1      0.00%     66.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455           12      0.01%     66.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711           33      0.04%     66.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967           77      0.09%     66.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9031            1      0.00%     66.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9095            5      0.01%     66.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223          527      0.59%     67.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9351            2      0.00%     67.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479           85      0.09%     67.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735          150      0.17%     67.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9863            1      0.00%     67.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9927            1      0.00%     67.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991           29      0.03%     67.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10055            1      0.00%     67.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10119            2      0.00%     67.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247          279      0.31%     68.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503           84      0.09%     68.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759            6      0.01%     68.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015           13      0.01%     68.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11079            1      0.00%     68.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11143            4      0.00%     68.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271          496      0.55%     68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11399            2      0.00%     68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527           77      0.09%     68.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11655            4      0.00%     68.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783          153      0.17%     69.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039          141      0.16%     69.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12167            1      0.00%     69.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295          162      0.18%     69.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12359            1      0.00%     69.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12423            1      0.00%     69.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551          137      0.15%     69.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807           74      0.08%     69.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063           90      0.10%     69.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13191            2      0.00%     69.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319          343      0.38%     70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13575          145      0.16%     70.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13703            2      0.00%     70.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831           90      0.10%     70.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959            2      0.00%     70.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087          133      0.15%     70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215            1      0.00%     70.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343          164      0.18%     70.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14471            1      0.00%     70.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599          153      0.17%     70.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14727            1      0.00%     70.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855          162      0.18%     71.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14919            1      0.00%     71.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111           88      0.10%     71.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15175            1      0.00%     71.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15239            1      0.00%     71.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367          278      0.31%     71.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15495            1      0.00%     71.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623           83      0.09%     71.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15879          199      0.22%     71.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16007            2      0.00%     71.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135          139      0.15%     71.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16199            1      0.00%     71.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16263            9      0.01%     71.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391          416      0.46%     72.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16519            1      0.00%     72.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647          138      0.15%     72.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16903          203      0.23%     72.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17031            1      0.00%     72.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159           87      0.10%     72.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17287            1      0.00%     72.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415          275      0.31%     73.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671           89      0.10%     73.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17799            3      0.00%     73.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927          155      0.17%     73.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18048-18055            2      0.00%     73.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183          155      0.17%     73.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18240-18247            2      0.00%     73.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439          162      0.18%     73.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18560-18567            2      0.00%     73.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695          131      0.15%     73.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18816-18823            2      0.00%     73.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951           93      0.10%     74.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19008-19015            1      0.00%     74.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207          142      0.16%     74.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19328-19335            3      0.00%     74.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19392-19399            2      0.00%     74.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463          340      0.38%     74.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719           81      0.09%     74.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19776-19783            1      0.00%     74.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975           77      0.09%     74.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20096-20103            2      0.00%     74.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20160-20167            2      0.00%     74.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231          134      0.15%     74.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359            3      0.00%     74.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20416-20423            2      0.00%     74.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487          164      0.18%     75.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615            1      0.00%     75.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743          141      0.16%     75.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20864-20871            1      0.00%     75.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20928-20935            1      0.00%     75.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999          149      0.17%     75.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21120-21127            1      0.00%     75.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255           80      0.09%     75.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21312-21319            2      0.00%     75.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21376-21383            3      0.00%     75.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511          482      0.54%     76.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767           10      0.01%     76.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023            5      0.01%     76.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22208-22215            1      0.00%     76.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279           92      0.10%     76.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22336-22343            1      0.00%     76.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22400-22407            5      0.01%     76.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535          269      0.30%     76.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791           35      0.04%     76.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047          146      0.16%     76.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23168-23175            1      0.00%     76.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303           81      0.09%     76.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23424-23431            4      0.00%     76.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559          526      0.59%     77.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815           74      0.08%     77.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071           36      0.04%     77.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24128-24135            1      0.00%     77.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24256-24263            1      0.00%     77.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327           12      0.01%     77.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24448-24455            4      0.00%     77.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24512-24519            1      0.00%     77.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583          404      0.45%     78.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839            7      0.01%     78.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095           28      0.03%     78.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351           84      0.09%     78.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479            7      0.01%     78.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607          523      0.58%     78.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863           80      0.09%     78.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25920-25927            1      0.00%     78.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25984-25991            1      0.00%     78.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119          152      0.17%     78.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26240-26247            1      0.00%     79.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26304-26311            1      0.00%     79.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375           32      0.04%     79.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26496-26503            4      0.00%     79.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631          274      0.31%     79.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26688-26695            1      0.00%     79.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887           82      0.09%     79.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26944-26951            1      0.00%     79.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143            3      0.00%     79.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399           17      0.02%     79.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27520-27527            3      0.00%     79.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27591            1      0.00%     79.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655          484      0.54%     80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27712-27719            1      0.00%     80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27776-27783            1      0.00%     80.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911           77      0.09%     80.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27968-27975            2      0.00%     80.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28032-28039            1      0.00%     80.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167          152      0.17%     80.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28224-28231            1      0.00%     80.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28288-28295            1      0.00%     80.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28352-28359            1      0.00%     80.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423          140      0.16%     80.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28544-28551            1      0.00%     80.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679          163      0.18%     80.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28800-28807            2      0.00%     80.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935          130      0.14%     80.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191           75      0.08%     80.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447           86      0.10%     80.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29568-29575            3      0.00%     80.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703          336      0.37%     81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29824-29831            1      0.00%     81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29959          140      0.16%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30080-30087            1      0.00%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30144-30151            2      0.00%     81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215           91      0.10%     81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30336-30343            1      0.00%     81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30400-30407            1      0.00%     81.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471          134      0.15%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30592-30599            1      0.00%     81.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727          156      0.17%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30784-30791            1      0.00%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30912-30919            2      0.00%     81.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983          152      0.17%     82.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31104-31111            2      0.00%     82.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239          157      0.17%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31360-31367            2      0.00%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31424-31431            1      0.00%     82.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495           86      0.10%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31616-31623            2      0.00%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751          272      0.30%     82.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007           83      0.09%     82.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135            2      0.00%     82.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32192-32199            1      0.00%     82.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32263          202      0.23%     82.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32320-32327            1      0.00%     82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32384-32391            2      0.00%     82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519          144      0.16%     83.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32640-32647            2      0.00%     83.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775          415      0.46%     83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32896-32903            1      0.00%     83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031          148      0.16%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33152-33159            1      0.00%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33287          208      0.23%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33344-33351            1      0.00%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415            2      0.00%     84.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543           85      0.09%     84.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33664-33671            2      0.00%     84.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799          270      0.30%     84.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33920-33927            2      0.00%     84.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055           85      0.09%     84.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34112-34119            1      0.00%     84.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311          157      0.17%     84.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34432-34439            1      0.00%     84.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567          152      0.17%     84.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34624-34631            2      0.00%     84.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34688-34695            1      0.00%     84.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823          147      0.16%     85.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079          134      0.15%     85.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335           90      0.10%     85.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35392-35399            2      0.00%     85.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35456-35463            4      0.00%     85.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35520-35527            1      0.00%     85.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35584-35591          143      0.16%     85.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847          337      0.38%     85.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35968-35975            1      0.00%     85.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103           82      0.09%     85.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36224-36231            2      0.00%     85.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359           76      0.08%     85.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36416-36423            1      0.00%     85.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615          131      0.15%     86.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36736-36743            1      0.00%     86.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871          154      0.17%     86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36992-36999            2      0.00%     86.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127          139      0.15%     86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37184-37191            1      0.00%     86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37312-37319            1      0.00%     86.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383          153      0.17%     86.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37504-37511            2      0.00%     86.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37568-37575            2      0.00%     86.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639           81      0.09%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37760-37767            2      0.00%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37824-37831            1      0.00%     86.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895          483      0.54%     87.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37952-37959            1      0.00%     87.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151           12      0.01%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407            2      0.00%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535            4      0.00%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663           84      0.09%     87.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38848-38855            1      0.00%     87.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919          271      0.30%     87.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39040-39047            1      0.00%     87.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175           30      0.03%     87.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39232-39239            1      0.00%     87.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39296-39303            1      0.00%     87.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431          152      0.17%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39552-39559            3      0.00%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39616-39623            1      0.00%     87.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687           86      0.10%     88.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39808-39815            1      0.00%     88.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943          521      0.58%     88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40064-40071            2      0.00%     88.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199           77      0.09%     88.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455           28      0.03%     88.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40576-40583            4      0.00%     88.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711           10      0.01%     88.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967          402      0.45%     89.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223            9      0.01%     89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41280-41287            1      0.00%     89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41408-41415            1      0.00%     89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479           35      0.04%     89.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41600-41607            4      0.00%     89.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735           79      0.09%     89.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41856-41863            1      0.00%     89.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991          523      0.58%     89.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247           79      0.09%     89.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503          146      0.16%     90.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42624-42631            4      0.00%     90.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759           34      0.04%     90.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015          269      0.30%     90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43136-43143            1      0.00%     90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43200-43207            1      0.00%     90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271           89      0.10%     90.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43328-43335            1      0.00%     90.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527            3      0.00%     90.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43648-43655            3      0.00%     90.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43712-43719            1      0.00%     90.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783           13      0.01%     90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43904-43911            1      0.00%     90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039          482      0.54%     91.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44160-44167            1      0.00%     91.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44224-44231            2      0.00%     91.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295           78      0.09%     91.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551          151      0.17%     91.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44679            2      0.00%     91.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807          138      0.15%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44928-44935            3      0.00%     91.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063          153      0.17%     91.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45120-45127            2      0.00%     91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45191            1      0.00%     91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319          134      0.15%     91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575           77      0.09%     91.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45696-45703            2      0.00%     91.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831           82      0.09%     92.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087          341      0.38%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46144-46151            1      0.00%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46208-46215            2      0.00%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46336-46343          140      0.16%     92.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599           93      0.10%     92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46720-46727            1      0.00%     92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855          133      0.15%     92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-46983            3      0.00%     92.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111          149      0.17%     93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47232-47239            3      0.00%     93.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367          156      0.17%     93.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623          157      0.17%     93.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47744-47751            3      0.00%     93.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879           88      0.10%     93.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47936-47943            1      0.00%     93.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48000-48007            1      0.00%     93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135          298      0.33%     93.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48192-48199            4      0.00%     93.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48256-48263            1      0.00%     93.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48320-48327            3      0.00%     93.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391          110      0.12%     93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48512-48519            1      0.00%     93.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48647          200      0.22%     94.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48768-48775           70      0.08%     94.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903          136      0.15%     94.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48960-48967            5      0.01%     94.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031            9      0.01%     94.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095            6      0.01%     94.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159         5002      5.57%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          89727                       # Bytes accessed per row activation
system.physmem.totQLat                   373414318500                       # Total ticks spent queuing
system.physmem.totMemAccLat              469593144750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                  77465255000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                 18713571250                       # Total ticks spent accessing banks
system.physmem.avgQLat                       24102.05                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                     1207.87                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30309.92                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         378.96                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.62                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.63                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.57                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           2.98                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.96                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        14.75                       # Average write queue length when enqueuing
system.physmem.readRowHits                   15419103                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     91153                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  85.23                       # Row buffer hit rate for writes
system.physmem.avgGap                       160458.28                       # Average gap between requests
system.physmem.pageHitRate                      99.42                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               2.19                       # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput                     54116520                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq            16546551                       # Transaction distribution
system.membus.trans_dist::ReadResp           16546551                       # Transaction distribution
system.membus.trans_dist::WriteReq             763368                       # Transaction distribution
system.membus.trans_dist::WriteResp            763368                       # Transaction distribution
system.membus.trans_dist::Writeback             57909                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4515                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4515                       # Transaction distribution
system.membus.trans_dist::ReadExReq            132216                       # Transaction distribution
system.membus.trans_dist::ReadExResp           132216                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2382986                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893513                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280361                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               34951209                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390389                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16516344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18914457                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total           141597849                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus              141597849                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1206149500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3614000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer6.occupancy         17910601500                       # Layer occupancy (ticks)
system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4950348835                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
system.membus.respLayer2.occupancy        34633819250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.iobus.throughput                      47801275                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq             16518751                       # Transaction distribution
system.iobus.trans_dist::ReadResp            16518751                       # Transaction distribution
system.iobus.trans_dist::WriteReq                8166                       # Transaction distribution
system.iobus.trans_dist::WriteResp               8166                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        29936                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7944                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          534                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          746                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio      2342380                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total      2382986                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30670848                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total     30670848                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                33053834                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39180                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15888                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1068                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2084                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio          397                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio      2331126                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total      2390389                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total            125073781                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus               125073781                       # Total data (bytes)
system.iobus.reqLayer0.occupancy             21043000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy              3977000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               534000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy               527000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                27000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy               445000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy           1172909000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer22.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy         15335424000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
system.iobus.respLayer0.occupancy          2374820000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
system.iobus.respLayer1.occupancy         42037561750                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     14995644                       # DTB read hits
system.cpu.dtb.read_misses                       7334                       # DTB read misses
system.cpu.dtb.write_hits                    11230146                       # DTB write hits
system.cpu.dtb.write_misses                      2212                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3498                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    192                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 15002978                       # DTB read accesses
system.cpu.dtb.write_accesses                11232358                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          26225790                       # DTB hits
system.cpu.dtb.misses                            9546                       # DTB misses
system.cpu.dtb.accesses                      26235336                       # DTB accesses
system.cpu.itb.inst_hits                     61491413                       # ITB inst hits
system.cpu.itb.inst_misses                       4471                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 61495884                       # ITB inst accesses
system.cpu.itb.hits                          61491413                       # DTB hits
system.cpu.itb.misses                            4471                       # DTB misses
system.cpu.itb.accesses                      61495884                       # DTB accesses
system.cpu.numCycles                       5233072966                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    60197580                       # Number of instructions committed
system.cpu.committedOps                      76603973                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              68871033                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
system.cpu.num_func_calls                     2140403                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7948247                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     68871033                       # number of integer instructions
system.cpu.num_fp_insts                         10269                       # number of float instructions
system.cpu.num_int_register_reads           394768801                       # number of times the integer registers were read
system.cpu.num_int_register_writes           74180798                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
system.cpu.num_mem_refs                      27393280                       # number of memory refs
system.cpu.num_load_insts                    15659727                       # Number of load instructions
system.cpu.num_store_insts                   11733553                       # Number of store instructions
system.cpu.num_idle_cycles               4581527140.608249                       # Number of idle cycles
system.cpu.num_busy_cycles               651545825.391751                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.124505                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.875495                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    83016                       # number of quiesce instructions executed
system.cpu.icache.tags.replacements            856254                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.868538                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            60634647                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            856766                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             70.771537                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       19982971250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.868538                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997790                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997790                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     60634647                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        60634647                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      60634647                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         60634647                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     60634647                       # number of overall hits
system.cpu.icache.overall_hits::total        60634647                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       856766                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        856766                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       856766                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         856766                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       856766                       # number of overall misses
system.cpu.icache.overall_misses::total        856766                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11773893500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11773893500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11773893500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11773893500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11773893500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11773893500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     61491413                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     61491413                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     61491413                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     61491413                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     61491413                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     61491413                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013933                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013933                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013933                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013933                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013933                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013933                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.251093                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13742.251093                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.251093                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13742.251093                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.251093                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13742.251093                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856766                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       856766                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       856766                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       856766                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       856766                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       856766                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10056315500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  10056315500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10056315500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  10056315500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10056315500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  10056315500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    435321250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    435321250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    435321250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total    435321250                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013933                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013933                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013933                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.528683                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.528683                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.528683                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.528683                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.528683                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.528683                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            62509                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        50754.670173                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1682271                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           127891                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            13.153944                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     2565643785000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37718.408308                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884371                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000703                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  6993.399948                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  6038.976844                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.575537                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106711                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.092147                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.774455                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8705                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3532                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       844545                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       369635                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1226417                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       595234                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       595234                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       113385                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       113385                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         8705                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3532                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       844545                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       483020                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1339802                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         8705                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3532                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       844545                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       483020                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1339802                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        10585                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         9809                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        20401                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         2907                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         2907                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133824                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133824                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        10585                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       143633                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154225                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        10585                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       143633                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154225                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       305250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       150000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    752463500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    738211000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1491129750                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       469980                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       469980                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9619522392                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9619522392                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       305250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       150000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    752463500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10357733392                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11110652142                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       305250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       150000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    752463500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10357733392                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11110652142                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8710                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3534                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       855130                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       379444                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1246818                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       595234                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       595234                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2933                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2933                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       247209                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       247209                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8710                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3534                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       855130                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       626653                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1494027                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8710                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3534                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       855130                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       626653                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1494027                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000566                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012378                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025851                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.016362                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991135                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991135                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541340                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.541340                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000566                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012378                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.229207                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.103228                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000566                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012378                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.229207                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.103228                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        61050                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71087.718470                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75258.538077                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73091.012695                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   161.671827                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   161.671827                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71881.892575                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71881.892575                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71087.718470                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72112.490806                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72041.835902                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71087.718470                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72112.490806                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72041.835902                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        57909                       # number of writebacks
system.cpu.l2cache.writebacks::total            57909                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10585                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9809                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        20401                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2907                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         2907                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133824                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133824                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10585                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       143633                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154225                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10585                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       143633                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154225                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       242750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    619898500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    615330500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1235596750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29079907                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29079907                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7944865608                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7944865608                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       242750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    619898500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8560196108                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9180462358                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       242750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    619898500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8560196108                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9180462358                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    343871250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166656947250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167000818500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16702635650                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16702635650                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    343871250                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359582900                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183703454150                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025851                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016362                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991135                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991135                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541340                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541340                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229207                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.103228                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229207                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.103228                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58563.863958                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62731.216230                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60565.499240                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.407981                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.407981                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59368.017755                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59368.017755                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58563.863958                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59597.697660                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59526.421514                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58563.863958                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59597.697660                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59526.421514                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            626141                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.876746                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            23655438                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            626653                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             37.748863                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         664004250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.876746                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999759                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999759                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13195736                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13195736                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      9972597                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        9972597                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       236394                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       236394                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247778                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247778                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      23168333                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         23168333                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     23168333                       # number of overall hits
system.cpu.dcache.overall_hits::total        23168333                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       368059                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        368059                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       250142                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       250142                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        11385                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        11385                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       618201                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         618201                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       618201                       # number of overall misses
system.cpu.dcache.overall_misses::total        618201                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5416878250                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5416878250                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  11621403015                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  11621403015                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    158363750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total    158363750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  17038281265                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  17038281265                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  17038281265                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  17038281265                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13563795                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13563795                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10222739                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10222739                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247779                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       247779                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247778                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247778                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     23786534                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     23786534                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     23786534                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     23786534                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027135                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.027135                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024469                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.024469                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045948                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045948                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025990                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025990                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025990                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025990                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14717.418267                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14717.418267                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46459.223221                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 46459.223221                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13909.859464                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13909.859464                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 27561.070372                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 27561.070372                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27561.070372                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27561.070372                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       595234                       # number of writebacks
system.cpu.dcache.writebacks::total            595234                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368059                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       368059                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250142                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       250142                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11385                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total        11385                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       618201                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       618201                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       618201                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       618201                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4678465750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   4678465750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11069177985                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11069177985                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135539250                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135539250                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15747643735                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  15747643735                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15747643735                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  15747643735                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050613250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050613250                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26234152350                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26234152350                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284765600                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284765600                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027135                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027135                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024469                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024469                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045948                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045948                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025990                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.025990                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025990                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.025990                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12711.184212                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12711.184212                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44251.577044                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44251.577044                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11905.072464                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.072464                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25473.339149                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25473.339149                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25473.339149                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25473.339149                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput                52965120                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2454582                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2454582                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq        763368                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp       763368                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       595234                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2933                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2933                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       247209                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       247209                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725138                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5749352                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12460                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27430                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7514380                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54754804                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83615077                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34840                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      138418857                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         138418857                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       166312                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3008581500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1295429750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2534385915                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       8926000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      18720500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iocache.tags.replacements                    0                       # number of replacements
system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538389615750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1538389615750                       # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538389615750                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1538389615750                       # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------