path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.903518                       # Number of seconds simulated
sim_ticks                                2903517798500                       # Number of ticks simulated
final_tick                               2903517798500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 703123                       # Simulator instruction rate (inst/s)
host_op_rate                                   847748                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            18151522616                       # Simulator tick rate (ticks/s)
host_mem_usage                                 572756                       # Number of bytes of host memory used
host_seconds                                   159.96                       # Real time elapsed on the host
sim_insts                                   112471533                       # Number of instructions simulated
sim_ops                                     135605825                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           588836                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          3938784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           600704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5102020                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10231944                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       588836                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       600704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1189540                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7646016                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7663540                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             17654                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             62062                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              9386                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             79720                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                168847                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          119469                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123850                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            44                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              202801                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1356556                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              206888                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1757186                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3523982                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         202801                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         206888                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             409689                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2633363                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6033                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2639398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2633363                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           44                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             202801                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1362589                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             206888                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1757188                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6163380                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        168847                       # Number of read requests accepted
system.physmem.writeReqs                       123850                       # Number of write requests accepted
system.physmem.readBursts                      168847                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     123850                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10798016                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7677504                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10231944                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7663540                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          40733                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10014                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9659                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10299                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9948                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18863                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10091                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10301                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10599                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9915                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10209                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9947                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9027                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9869                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10471                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9980                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9527                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7419                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7262                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8122                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7539                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7355                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7348                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7576                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7905                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7603                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7846                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7540                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6940                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7394                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7835                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7358                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6919                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
system.physmem.totGap                    2903517476500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  159275                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 119469                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    167922                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       537                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       248                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6093                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6081                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6020                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7645                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      260                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        59278                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      311.674753                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.487125                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     333.482596                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21806     36.79%     36.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14989     25.29%     62.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5586      9.42%     71.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3267      5.51%     77.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2330      3.93%     80.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1628      2.75%     83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1108      1.87%     85.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1064      1.79%     87.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7500     12.65%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          59278                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5882                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.683781                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      547.352228                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5880     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5882                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5882                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.394594                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.624984                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.894436                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                16      0.27%      0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 8      0.14%      0.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                7      0.12%      0.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              10      0.17%      0.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4921     83.66%     84.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              66      1.12%     85.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             241      4.10%     89.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              88      1.50%     91.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              77      1.31%     92.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             178      3.03%     95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              14      0.24%     95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               7      0.12%     95.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               9      0.15%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              13      0.22%     96.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               6      0.10%     96.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.09%     96.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             174      2.96%     99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.07%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.05%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               3      0.05%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.24%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             4      0.07%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5882                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1493162250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4656643500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    843595000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8849.99                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27599.99                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.72                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.64                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.52                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.64                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.20                       # Average write queue length when enqueuing
system.physmem.readRowHits                     138806                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     90595                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.27                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.52                       # Row buffer hit rate for writes
system.physmem.avgGap                      9919874.40                       # Average gap between requests
system.physmem.pageHitRate                      79.47                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  229302360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  125115375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 700237200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                392208480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           189643549680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            87298782345                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1665531858750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1943921054190                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.505834                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2770598960250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     96954780000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35962503500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  218839320                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  119406375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 615763200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                385138800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           189643549680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            86123693430                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1666562638500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1943669029305                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.419034                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2772326743250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     96954780000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     34236177250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     6827                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                6827                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         2216                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4610                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples         6826                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           6826    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         6826                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         5786                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6703.217150                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         4631     80.04%     80.04% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1152     19.91%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303            2      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-180223            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         5786                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  -1209080312                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.765375                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      925400000    -76.54%    -76.54% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    -2134480312    176.54%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  -1209080312                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3595     62.14%     62.14% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         2190     37.86%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5785                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6827                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6827                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5785                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5785                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        12612                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12507441                       # DTB read hits
system.cpu0.dtb.read_misses                      5917                       # DTB read misses
system.cpu0.dtb.write_hits                    9856816                       # DTB write hits
system.cpu0.dtb.write_misses                      910                       # DTB write misses
system.cpu0.dtb.flush_tlb                        2937                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     486                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    4603                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   884                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      232                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12513358                       # DTB read accesses
system.cpu0.dtb.write_accesses                9857726                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         22364257                       # DTB hits
system.cpu0.dtb.misses                           6827                       # DTB misses
system.cpu0.dtb.accesses                     22371084                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3521                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3521                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          830                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2691                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3521                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3521    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3521                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2670                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6917.920498                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          769     28.80%     28.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1283     48.05%     76.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          616     23.07%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2670                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    925066000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      925066000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    925066000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1840     68.91%     68.91% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          830     31.09%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2670                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3521                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3521                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2670                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2670                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6191                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    58595537                       # ITB inst hits
system.cpu0.itb.inst_misses                      3521                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        2937                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     486                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2691                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                58599058                       # ITB inst accesses
system.cpu0.itb.hits                         58595537                       # DTB hits
system.cpu0.itb.misses                           3521                       # DTB misses
system.cpu0.itb.accesses                     58599058                       # DTB accesses
system.cpu0.numCycles                      2904052506                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   57017963                       # Number of instructions committed
system.cpu0.committedOps                     68702056                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             60736686                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5415                       # Number of float alu accesses
system.cpu0.num_func_calls                    5101109                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7710665                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    60736686                       # number of integer instructions
system.cpu0.num_fp_insts                         5415                       # number of float instructions
system.cpu0.num_int_register_reads          110496547                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          42022968                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                4193                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1224                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           248490103                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           26091255                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     23020484                       # number of memory refs
system.cpu0.num_load_insts                   12672781                       # Number of load instructions
system.cpu0.num_store_insts                  10347703                       # Number of store instructions
system.cpu0.num_idle_cycles              2689228469.175671                       # Number of idle cycles
system.cpu0.num_busy_cycles              214824036.824329                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.073974                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.926026                       # Percentage of idle cycles
system.cpu0.Branches                         13203328                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2205      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 47217639     67.16%     67.16% # Class of executed instruction
system.cpu0.op_class::IntMult                   59885      0.09%     67.25% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.25% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              4420      0.01%     67.26% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.26% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.26% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.26% # Class of executed instruction
system.cpu0.op_class::MemRead                12672781     18.03%     85.28% # Class of executed instruction
system.cpu0.op_class::MemWrite               10347703     14.72%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  70304633                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3029                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           820099                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.829843                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           43241744                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           820611                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            52.694570                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle        996611500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   401.515698                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   110.314145                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.784210                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.215457                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999668                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        177137427                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       177137427                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     11786116                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     11329399                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23115515                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      9461522                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      9365348                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18826870                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       201006                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       191753                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       392759                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       231308                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       212173                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       443481                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       239891                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       220488                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460379                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     21247638                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     20694747                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41942385                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     21448644                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     20886500                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42335144                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       202704                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       197921                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       400625                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       143580                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       155041                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       298621                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        59413                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        58849                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       118262                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        11581                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11100                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22681                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       346284                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       352962                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        699246                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       405697                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       411811                       # number of overall misses
system.cpu0.dcache.overall_misses::total       817508                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3011302500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2950015000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5961317500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5623507500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6931365000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  12554872500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    144229500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    137062000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    281291500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8634810000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   9881380000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  18516190000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8634810000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   9881380000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  18516190000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11988820                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     11527320                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23516140                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9605102                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9520389                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19125491                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       260419                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       250602                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       511021                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       242889                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       223273                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       466162                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       239893                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       220488                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460381                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     21593922                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     21047709                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42641631                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     21854341                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     21298311                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43152652                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016908                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.017170                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.017036                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014948                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.016285                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015614                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.228144                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.234831                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231423                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.047680                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049715                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048655                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016036                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016770                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016398                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018564                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019335                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018945                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14855.663924                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14905.012606                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14880.043682                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39166.370664                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44706.658239                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42042.831884                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12453.976341                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12347.927928                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12402.076628                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24935.630869                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27995.591593                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26480.222983                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21283.889208                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23994.939426                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22649.552053                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       683625                       # number of writebacks
system.cpu0.dcache.writebacks::total           683625                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          291                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          369                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          660                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7077                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7054                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14131                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          291                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          369                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          660                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          291                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          369                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          660                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       202413                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       197552                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       399965                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       143580                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       155041                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       298621                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        58532                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        57717                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       116249                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4504                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4046                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8550                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       345993                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       352593                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       698586                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       404525                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       410310                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       814835                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15867                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15271                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15968                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        11621                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31835                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        26892                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2803165500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2746358000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5549523500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5479927500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6776324000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12256251500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    768422500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    755594500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1524017000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     57248500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     52551500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    109800000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8283093000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9522682000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  17805775000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9051515500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10278276500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  19329792000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2904028500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3003756000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5907784500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2320925500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2251479500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4572405000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5224954000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5255235500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10480189500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016883                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017138                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017008                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014948                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.016285                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015614                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.224761                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.230313                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227484                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.018543                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.018121                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018341                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000008                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016023                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016752                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016383                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018510                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019265                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018883                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13109.936430                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12710.590586                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12988.507168                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12842.105263                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25050.026809                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23722.338878                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183023.161278                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196696.745465                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189729.093070                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145348.540832                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 193742.319938                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165732.900794                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164126.087639                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 195420.031980                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178456.067907                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1697906                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.737364                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          113870601                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1698418                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.045098                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      25672110500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   416.223441                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    94.513923                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.812936                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.184598                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997534                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        117267449                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       117267449                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     57739156                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     56131445                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      113870601                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     57739156                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     56131445                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       113870601                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     57739156                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     56131445                       # number of overall hits
system.cpu0.icache.overall_hits::total      113870601                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       856381                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       842043                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1698424                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       856381                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       842043                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1698424                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       856381                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       842043                       # number of overall misses
system.cpu0.icache.overall_misses::total      1698424                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11736376500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11602280500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  23338657000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11736376500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  11602280500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  23338657000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11736376500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  11602280500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  23338657000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     58595537                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     56973488                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115569025                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     58595537                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     56973488                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115569025                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     58595537                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     56973488                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115569025                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014615                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014780                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014696                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014615                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014780                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014696                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014615                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014780                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014696                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13704.620373                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.726858                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13741.360814                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13704.620373                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.726858                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13741.360814                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13704.620373                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.726858                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13741.360814                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       856381                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       842043                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1698424                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       856381                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       842043                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1698424                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       856381                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       842043                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1698424                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10879995500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10760237500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  21640233000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10879995500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10760237500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  21640233000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10879995500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10760237500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  21640233000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    676974000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    676974000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    676974000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    676974000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014615                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014780                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014696                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014615                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014780                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014696                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014615                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014780                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014696                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12704.620373                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12778.726858                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12741.360814                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12704.620373                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     6604                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                6604                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         1835                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4768                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples         6603                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           6603    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         6603                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5481                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6472.015315                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191         1651     30.12%     30.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383         2769     50.52%     80.64% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575         1058     19.30%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            3      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5481                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1004634564                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     1.995586                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1000200000    -99.56%    -99.56% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -2004834564    199.56%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1004634564                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3666     66.90%     66.90% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1814     33.10%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5480                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6604                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6604                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5480                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5480                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        12084                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12016469                       # DTB read hits
system.cpu1.dtb.read_misses                      5667                       # DTB read misses
system.cpu1.dtb.write_hits                    9752712                       # DTB write hits
system.cpu1.dtb.write_misses                      937                       # DTB write misses
system.cpu1.dtb.flush_tlb                        2933                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     431                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    4084                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   937                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12022136                       # DTB read accesses
system.cpu1.dtb.write_accesses                9753649                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         21769181                       # DTB hits
system.cpu1.dtb.misses                           6604                       # DTB misses
system.cpu1.dtb.accesses                     21775785                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     3234                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                3234                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          677                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2557                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         3234                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           3234    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         3234                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2430                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6613.791032                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143          712     29.30%     29.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::6144-8191            1      0.04%     29.34% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287          673     27.70%     57.04% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335          477     19.63%     76.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::14336-16383           16      0.66%     77.33% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575          551     22.67%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2430                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000178000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000178000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000178000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1753     72.14%     72.14% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          677     27.86%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2430                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3234                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3234                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2430                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2430                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         5664                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    56973488                       # ITB inst hits
system.cpu1.itb.inst_misses                      3234                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        2933                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     431                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2428                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                56976722                       # ITB inst accesses
system.cpu1.itb.hits                         56973488                       # DTB hits
system.cpu1.itb.misses                           3234                       # DTB misses
system.cpu1.itb.accesses                     56976722                       # DTB accesses
system.cpu1.numCycles                      2902983091                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   55453570                       # Number of instructions committed
system.cpu1.committedOps                     66903769                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             59172733                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5746                       # Number of float alu accesses
system.cpu1.num_func_calls                    4791563                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      7521701                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    59172733                       # number of integer instructions
system.cpu1.num_fp_insts                         5746                       # number of float instructions
system.cpu1.num_int_register_reads          107592864                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          40634379                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4256                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1492                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           241317525                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           25809860                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     22393766                       # number of memory refs
system.cpu1.num_load_insts                   12173697                       # Number of load instructions
system.cpu1.num_store_insts                  10220069                       # Number of store instructions
system.cpu1.num_idle_cycles              2697480671.520393                       # Number of idle cycles
system.cpu1.num_busy_cycles              205502419.479607                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.070790                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.929210                       # Percentage of idle cycles
system.cpu1.Branches                         12715726                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                  132      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 45969122     67.18%     67.19% # Class of executed instruction
system.cpu1.op_class::IntMult                   54656      0.08%     67.27% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4033      0.01%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.27% # Class of executed instruction
system.cpu1.op_class::MemRead                12173697     17.79%     85.06% # Class of executed instruction
system.cpu1.op_class::MemWrite               10220069     14.94%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  68421709                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           187451467                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.079135                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         309074032000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.079135                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067446                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067446                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          234                       # number of demand (read+write) misses
system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          234                       # number of overall misses
system.iocache.overall_misses::total              234                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28776877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28776877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4271859590                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4271859590                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28776877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28776877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28776877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28776877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          234                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             234                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          234                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            234                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122978.106838                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117928.986031                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117928.986031                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 122978.106838                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122978.106838                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 122978.106838                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122978.106838                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          234                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17076877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17076877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2460659590                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2460659590                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     17076877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     17076877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     17076877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     17076877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67928.986031                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67928.986031                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72978.106838                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72978.106838                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    89754                       # number of replacements
system.l2c.tags.tagsinuse                64926.218037                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4554949                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   154987                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.389233                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50375.736083                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.809030                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.965062                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4670.410821                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2880.132547                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.905198                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4955.443121                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2037.816176                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.768673                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000058                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.071265                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.043947                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000029                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.075614                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.031095                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.990695                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65227                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2130                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6959                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56093                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.995285                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 40606108                       # Number of tag accesses
system.l2c.tags.data_accesses                40606108                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5766                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3120                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5525                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         2899                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  17310                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          683625                       # number of Writeback hits
system.l2c.Writeback_hits::total               683625                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              10                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  23                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            85842                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            79037                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               164879                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        847732                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        832646                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1680378                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       259316                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       253156                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           512472                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5766                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3120                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              847732                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              345158                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5525                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          2899                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              832646                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              332193                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2375039                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5766                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3120                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             847732                       # number of overall hits
system.l2c.overall_hits::cpu0.data             345158                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5525                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         2899                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             832646                       # number of overall hits
system.l2c.overall_hits::cpu1.data             332193                       # number of overall hits
system.l2c.overall_hits::total                2375039                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   10                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1366                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1349                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2715                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          56359                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          74645                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             131004                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         8639                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         9386                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           18025                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         6133                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         6159                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          12292                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8639                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             62492                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9386                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             80804                       # number of demand (read+write) misses
system.l2c.demand_misses::total                161331                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8639                       # number of overall misses
system.l2c.overall_misses::cpu0.data            62492                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9386                       # number of overall misses
system.l2c.overall_misses::cpu1.data            80804                       # number of overall misses
system.l2c.overall_misses::total               161331                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       331000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker       165500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       405000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total         901500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       277500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       246000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       523500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       159000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4321008500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5672212000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   9993220500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst    690948000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    751164500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1442112500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    507685500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    507256000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1014941500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       331000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker       165500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    690948000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4828694000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       405000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    751164500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6179468000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     12451176000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       331000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker       165500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    690948000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4828694000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       405000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    751164500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6179468000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    12451176000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         5770                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3122                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5529                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         2899                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              17320                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       683625                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           683625                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1379                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1359                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2738                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       142201                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       153682                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295883                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       856371                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       842032                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1698403                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       265449                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       259315                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       524764                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         5770                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3122                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          856371                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          407650                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5529                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         2899                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          842032                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          412997                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2536370                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         5770                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3122                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         856371                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         407650                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5529                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         2899                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         842032                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         412997                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2536370                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000693                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000641                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000723                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000577                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990573                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.992642                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991600                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.396333                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.485711                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.442756                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.010088                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011147                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010613                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.023104                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.023751                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.023424                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000693                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.010088                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.153298                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000723                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011147                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.195653                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.063607                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000693                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.010088                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.153298                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000723                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011147                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.195653                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.063607                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        82750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        82750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker       101250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total        90150                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   203.147877                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   182.357302                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   192.817680                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76669.360705                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75989.175430                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76281.796739                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 79980.090288                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80030.311102                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 80006.241331                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 82779.308658                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82360.123397                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 82569.272698                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        82750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        82750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 79980.090288                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 77268.994431                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       101250                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80030.311102                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 76474.778476                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77177.826952                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        82750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        82750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 79980.090288                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 77268.994431                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       101250                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80030.311102                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 76474.778476                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77177.826952                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               83279                       # number of writebacks
system.l2c.writebacks::total                    83279                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              10                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1366                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1349                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2715                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        56359                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        74645                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        131004                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         8639                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         9386                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        18025                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6133                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         6159                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        12292                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8639                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        62492                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9386                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        80804                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           161331                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8639                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        62492                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9386                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        80804                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          161331                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15867                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        15271                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15968                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        11621                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        31835                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        26892                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       291000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       145500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       365000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total       801500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     28392000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     28047500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     56439500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3757418500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4925762000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8683180500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    604558000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    657304500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1261862500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    446355500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    445666000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total    892021500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       291000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       145500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    604558000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4203774000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       365000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    657304500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5371428000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10837866000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       291000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       145500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    604558000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4203774000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       365000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    657304500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5371428000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10837866000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    564199000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2705690000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2812868500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6082757500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2137293500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2117838000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4255131500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    564199000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4842983500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   4930706500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  10337889000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000693                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000641                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000723                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000577                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990573                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992642                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991600                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.396333                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.485711                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.442756                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010088                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011147                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010613                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.023104                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.023751                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023424                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000693                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000641                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010088                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.153298                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000723                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011147                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.195653                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.063607                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000693                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000641                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010088                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.153298                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000723                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011147                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.195653                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.063607                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        72750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        72750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        91250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total        80150                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20784.773060                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.326909                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20788.029466                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66669.360705                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65989.175430                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 66281.796739                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69980.090288                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70030.311102                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70006.241331                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 72779.308658                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72360.123397                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 72569.272698                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        72750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        72750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69980.090288                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67268.994431                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        91250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70030.311102                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66474.778476                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 67177.826952                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        72750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        72750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69980.090288                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67268.994431                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        91250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70030.311102                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66474.778476                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 67177.826952                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170523.098254                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184196.745465                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151463.085159                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133848.540832                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182242.319938                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154232.900794                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152127.642532                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 183352.167931                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 152591.019794                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70721                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::Writeback            119469                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6488                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4509                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4511                       # Transaction distribution
system.membus.trans_dist::ReadExReq            129210                       # Transaction distribution
system.membus.trans_dist::ReadExResp           129210                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30561                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       445477                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       553069                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 661969                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15578364                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     15741717                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                18058837                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              498                       # Total snoops (count)
system.membus.snoop_fanout::samples            394437                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  394437    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              394437                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90486000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1696500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           834684564                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          964305240                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64480996                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq              74970                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2298377                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           803098                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1802826                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2738                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2740                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           295883                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          295883                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1698424                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       524998                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5081680                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2577380                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18024                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34106                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7711190                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108733880                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96470557                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24084                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        45196                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              205273717                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          180370                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          5305015                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.037219                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.189299                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                5107565     96.28%     96.28% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 197450      3.72%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            5305015                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3268607000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           328500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2556658000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1277273499                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          12003000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          22807000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------