path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.903880                       # Number of seconds simulated
sim_ticks                                2903879904500                       # Number of ticks simulated
final_tick                               2903879904500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 952808                       # Simulator instruction rate (inst/s)
host_op_rate                                  1148802                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            24600165137                       # Simulator tick rate (ticks/s)
host_mem_usage                                 624836                       # Number of bytes of host memory used
host_seconds                                   118.04                       # Real time elapsed on the host
sim_insts                                   112472358                       # Number of instructions simulated
sim_ops                                     135608167                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           557092                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4007584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           629760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4985028                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10181064                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       557092                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       629760                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1186852                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7592448                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7609972                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             17158                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             63137                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              9840                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             77892                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                168052                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          118632                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               123013                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              191844                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1380079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           110                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              216868                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1716678                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              331                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3506021                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         191844                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         216868                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             408712                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2614587                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6032                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2620622                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2614587                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             191844                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1386111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          110                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             216868                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1716681                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             331                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6126643                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        168052                       # Number of read requests accepted
system.physmem.writeReqs                       123013                       # Number of write requests accepted
system.physmem.readBursts                      168052                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     123013                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10746816                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8512                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7623936                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10181064                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7609972                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      133                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9950                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9634                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10758                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10205                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18891                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10113                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10004                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10172                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9614                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10312                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9754                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9150                       # Per bank write bursts
system.physmem.perBankRdBursts::12              10004                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10185                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9904                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9269                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7437                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7207                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8535                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7773                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7341                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7352                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7319                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7510                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7314                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7939                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7417                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7018                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7498                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7483                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7310                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6671                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
system.physmem.totGap                    2903879542500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  158480                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 118632                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    167137                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       521                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       249                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5977                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6370                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6666                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7299                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8473                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     8836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6679                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6012                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       25                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        58767                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      312.602107                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     182.973761                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     334.010341                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21606     36.77%     36.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14724     25.05%     61.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5582      9.50%     71.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3238      5.51%     76.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2495      4.25%     81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1555      2.65%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          968      1.65%     85.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1073      1.83%     87.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7526     12.81%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          58767                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5814                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.881665                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      551.015664                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5812     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5814                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5814                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.489164                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.609616                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.405574                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                19      0.33%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                12      0.21%      0.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                4      0.07%      0.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              14      0.24%      0.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4869     83.75%     84.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              76      1.31%     85.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             108      1.86%     87.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              83      1.43%     89.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             296      5.09%     94.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              49      0.84%     95.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              13      0.22%     95.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              11      0.19%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              16      0.28%     95.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               6      0.10%     95.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.03%     95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.10%     96.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             172      2.96%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.14%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.07%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.07%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.07%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               4      0.07%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             6      0.10%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.19%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.05%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5814                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1475227250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4623708500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    839595000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8785.35                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27535.35                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.70                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.63                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.51                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.62                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.36                       # Average write queue length when enqueuing
system.physmem.readRowHits                     138207                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     90068                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.31                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.61                       # Row buffer hit rate for writes
system.physmem.avgGap                      9976739.02                       # Average gap between requests
system.physmem.pageHitRate                      79.53                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  228947040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  124921500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 699870600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                391871520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           189666943440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            87330979935                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1665718515750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1944162049785                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.506247                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2770909332000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     96966740000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35998339250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  215331480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  117492375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 609889800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                380052000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           189666943440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            85596128505                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1667240315250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1943826152850                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.390575                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2773463023000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     96966740000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     33450042500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                     6844                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                6844                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         2237                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4607                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walkWaitTime::samples         6844                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           6844    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         6844                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         5812                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12925.584997                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11265.166351                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  6611.780154                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-8191         1551     26.69%     26.69% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::8192-16383         2959     50.91%     77.60% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-24575         1234     21.23%     98.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::24576-32767           66      1.14%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-90111            2      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         5812                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples    941563500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      941563500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total    941563500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3596     61.87%     61.87% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         2216     38.13%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5812                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6844                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6844                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5812                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5812                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        12656                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12196931                       # DTB read hits
system.cpu0.dtb.read_misses                      5939                       # DTB read misses
system.cpu0.dtb.write_hits                    9657394                       # DTB write hits
system.cpu0.dtb.write_misses                      905                       # DTB write misses
system.cpu0.dtb.flush_tlb                        2937                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     471                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    4577                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   883                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      223                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12202870                       # DTB read accesses
system.cpu0.dtb.write_accesses                9658299                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         21854325                       # DTB hits
system.cpu0.dtb.misses                           6844                       # DTB misses
system.cpu0.dtb.accesses                     21861169                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                     3527                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3527                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          843                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2684                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3527                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3527    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3527                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2692                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13515.230312                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11626.856178                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  7003.990357                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191          705     26.19%     26.19% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383         1285     47.73%     73.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575          689     25.59%     99.52% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767           12      0.45%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2692                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples    941232000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0      941232000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total    941232000                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1849     68.68%     68.68% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          843     31.32%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2692                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3527                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3527                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2692                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2692                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         6219                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    57466570                       # ITB inst hits
system.cpu0.itb.inst_misses                      3527                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        2937                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     471                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2718                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                57470097                       # ITB inst accesses
system.cpu0.itb.hits                         57466570                       # DTB hits
system.cpu0.itb.misses                           3527                       # DTB misses
system.cpu0.itb.accesses                     57470097                       # DTB accesses
system.cpu0.numPwrStateTransitions               3088                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         1544                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    1559165456.796632                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   23913437415.201466                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         1498     97.02%     97.02% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10           41      2.66%     99.68% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.06%     99.74% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.06%     99.81% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            3      0.19%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499963862372                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           1544                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   496528439206                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2407351465294                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                      2904046767                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3031                       # number of quiesce instructions executed
system.cpu0.committedInsts                   55929982                       # Number of instructions committed
system.cpu0.committedOps                     67277087                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             59477787                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5777                       # Number of float alu accesses
system.cpu0.num_func_calls                    4936884                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7560751                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    59477787                       # number of integer instructions
system.cpu0.num_fp_insts                         5777                       # number of float instructions
system.cpu0.num_int_register_reads          108114498                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          41101378                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                4484                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1294                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           243146097                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           25735731                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     22502519                       # number of memory refs
system.cpu0.num_load_insts                   12359077                       # Number of load instructions
system.cpu0.num_store_insts                  10143442                       # Number of store instructions
system.cpu0.num_idle_cycles              2686489862.931067                       # Number of idle cycles
system.cpu0.num_busy_cycles              217556904.068932                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.074915                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.925085                       # Percentage of idle cycles
system.cpu0.Branches                         12907844                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2203      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 46271329     67.22%     67.22% # Class of executed instruction
system.cpu0.op_class::IntMult                   59336      0.09%     67.31% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              4393      0.01%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.31% # Class of executed instruction
system.cpu0.op_class::MemRead                12359077     17.95%     85.27% # Class of executed instruction
system.cpu0.op_class::MemWrite               10143442     14.73%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  68839780                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements           819212                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.827217                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           43241768                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           819724                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            52.751619                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1013369500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   311.161528                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   200.665688                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.607737                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.391925                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999663                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        177132717                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       177132717                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     11490299                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     11626240                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23116539                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      9270780                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      9555064                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18825844                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       200211                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       192673                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       392884                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       225024                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       218448                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       443472                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       232922                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       227346                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460268                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20761079                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21181304                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41942383                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20961290                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21373977                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42335267                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       199689                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       200118                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       399807                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       142721                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       155928                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       298649                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        56972                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        61224                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       118196                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10863                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11717                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22580                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       342410                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       356046                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        698456                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       399382                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       417270                       # number of overall misses
system.cpu0.dcache.overall_misses::total       816652                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2971524000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2998963500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5970487500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5760942000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6862631000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  12623573000                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    131745000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    146890000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    278635000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       166000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       166000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data   8732466000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   9861594500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  18594060500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data   8732466000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   9861594500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  18594060500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11689988                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     11826358                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23516346                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9413501                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9710992                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19124493                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       257183                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       253897                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       511080                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       235887                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230165                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       466052                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       232924                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       227346                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460270                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     21103489                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     21537350                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42640839                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     21360672                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     21791247                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43151919                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017082                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016921                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.017001                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015161                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.016057                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015616                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.221523                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.241137                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231267                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046052                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.050907                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048450                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000009                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016225                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016532                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016380                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.018697                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.019149                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018925                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14880.759581                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14985.975774                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.424127                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40365.061904                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44011.537376                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42268.927738                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12127.865231                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12536.485448                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12339.902569                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        83000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        83000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25502.952601                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27697.529252                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 26621.663355                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21864.946342                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23633.605339                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22768.646253                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       683633                       # number of writebacks
system.cpu0.dcache.writebacks::total           683633                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          281                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          383                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          664                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7123                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         6928                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14051                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          281                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          384                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          665                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          281                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          384                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          665                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       199408                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       199735                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       399143                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       142721                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       155927                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       298648                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        56083                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        60109                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       116192                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3740                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4789                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8529                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       342129                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       355662                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       697791                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       398212                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       415771                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       813983                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14424                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16714                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15123                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12466                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29547                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        29180                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2766355500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2792156000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5558511500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5618221000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6706526000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  12324747000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    723870500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    803461500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1527332000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     48171500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     60949500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    109121000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       164000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       164000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8384576500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   9498682000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  17883258500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9108447000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  10302143500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  19410590500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2834492500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3446734000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6281226500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2834492500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3446734000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6281226500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017058                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016889                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016973                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015161                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.016057                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015616                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.218067                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.236746                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227346                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.015855                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.020807                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018301                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000009                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016212                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016514                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016364                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018642                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.019080                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018863                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13872.841110                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13979.302576                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13926.115452                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39365.061904                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43010.678074                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41268.473253                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12907.128720                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13366.742085                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13144.898100                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12880.080214                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12726.978492                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.114199                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        82000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        82000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24507.061664                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26707.047703                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25628.388013                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22873.361426                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24778.408066                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.432296                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196512.236550                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206218.379801                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201722.220438                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95931.651267                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118119.739548                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.365896                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          1697986                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.728403                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          113871932                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1698498                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.042724                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      25838751500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   416.287276                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    94.441127                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.813061                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.184455                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.997516                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          264                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        117268940                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       117268940                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst     56612158                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     57259774                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      113871932                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     56612158                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     57259774                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       113871932                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     56612158                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     57259774                       # number of overall hits
system.cpu0.icache.overall_hits::total      113871932                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       854412                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       844092                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1698504                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       854412                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       844092                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1698504                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       854412                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       844092                       # number of overall misses
system.cpu0.icache.overall_misses::total      1698504                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11714597500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  11693314500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  23407912000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11714597500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  11693314500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  23407912000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11714597500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  11693314500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  23407912000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     57466570                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     58103866                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115570436                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     57466570                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     58103866                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115570436                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     57466570                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     58103866                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115570436                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014868                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014527                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014697                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014868                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014527                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014697                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014868                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014527                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014697                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13710.712747                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.127977                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.487709                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13710.712747                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.127977                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13781.487709                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13710.712747                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.127977                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13781.487709                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1697986                       # number of writebacks
system.cpu0.icache.writebacks::total          1697986                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       854412                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       844092                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1698504                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       854412                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       844092                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1698504                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       854412                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       844092                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1698504                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10860185500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  10849222500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  21709408000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10860185500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  10849222500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  21709408000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10860185500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  10849222500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  21709408000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    687287000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    687287000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    687287000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total    687287000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014868                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014527                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014697                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014868                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014527                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014697                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014868                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014527                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014697                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12710.712747                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.127977                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.487709                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12710.712747                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.127977                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.487709                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12710.712747                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.127977                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.487709                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872                       # average overall mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                     6555                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                6555                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         1891                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4663                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples         6554                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           6554    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         6554                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5423                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12314.493823                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 10586.515921                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7100.180026                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383         4356     80.32%     80.32% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767         1063     19.60%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-98303            2      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-114687            1      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::180224-196607            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5423                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1582538528                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.367973                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.482254                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1000207500     63.20%     63.20% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1      582331028     36.80%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1582538528                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3557     65.60%     65.60% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         1865     34.40%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5422                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6555                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6555                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5422                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5422                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        11977                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12327134                       # DTB read hits
system.cpu1.dtb.read_misses                      5631                       # DTB read misses
system.cpu1.dtb.write_hits                    9951026                       # DTB write hits
system.cpu1.dtb.write_misses                      924                       # DTB write misses
system.cpu1.dtb.flush_tlb                        2933                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     446                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    4004                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   895                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      222                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12332765                       # DTB read accesses
system.cpu1.dtb.write_accesses                9951950                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         22278160                       # DTB hits
system.cpu1.dtb.misses                           6555                       # DTB misses
system.cpu1.dtb.accesses                     22284715                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                     3197                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                3197                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          694                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2503                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         3197                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           3197    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         3197                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2377                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12629.995793                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 10731.102955                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7036.590613                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-8191          768     32.31%     32.31% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-16383         1084     45.60%     77.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-24575          512     21.54%     99.45% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-32767           12      0.50%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::90112-98303            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2377                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000178000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000178000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000178000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1683     70.80%     70.80% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          694     29.20%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2377                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3197                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3197                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2377                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2377                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         5574                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    58103866                       # ITB inst hits
system.cpu1.itb.inst_misses                      3197                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        2933                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     446                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2384                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                58107063                       # ITB inst accesses
system.cpu1.itb.hits                         58103866                       # DTB hits
system.cpu1.itb.misses                           3197                       # DTB misses
system.cpu1.itb.accesses                     58107063                       # DTB accesses
system.cpu1.numPwrStateTransitions               2958                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         1479                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    1717670727.160244                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   49232811122.635986                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         1466     99.12%     99.12% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10           10      0.68%     99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.07%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            1      0.07%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows            1      0.07%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 1799694071001                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           1479                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   363444899030                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2540435005470                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                      2903713042                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   56542376                       # Number of instructions committed
system.cpu1.committedOps                     68331080                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             60434186                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5384                       # Number of float alu accesses
system.cpu1.num_func_calls                    4958421                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      7671718                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    60434186                       # number of integer instructions
system.cpu1.num_fp_insts                         5384                       # number of float instructions
system.cpu1.num_int_register_reads          109955204                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          41558584                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                3965                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1422                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           246670957                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           26165253                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     22910809                       # number of memory refs
system.cpu1.num_load_insts                   12487681                       # Number of load instructions
system.cpu1.num_store_insts                  10423128                       # Number of store instructions
system.cpu1.num_idle_cycles              2692724474.472886                       # Number of idle cycles
system.cpu1.num_busy_cycles              210988567.527115                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.072662                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.927338                       # Percentage of idle cycles
system.cpu1.Branches                         13013850                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                  134      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 46919270     67.13%     67.13% # Class of executed instruction
system.cpu1.op_class::IntMult                   55219      0.08%     67.21% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.21% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4062      0.01%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::MemRead                12487681     17.87%     85.09% # Class of executed instruction
system.cpu1.op_class::MemWrite               10423128     14.91%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  69889494                       # Class of executed instruction
system.iobus.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46333000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                98000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               337000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                29500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                95500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               643000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6284000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36462000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187660851                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements                36424                       # number of replacements
system.iocache.tags.tagsinuse                1.079319                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         309377087000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.079319                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067457                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067457                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328122                       # Number of tag accesses
system.iocache.tags.data_accesses              328122                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide          234                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              234                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36458                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36458                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36458                       # number of overall misses
system.iocache.overall_misses::total            36458                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28898377                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28898377                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4277821474                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4277821474                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4306719851                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4306719851                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4306719851                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4306719851                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36458                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36458                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36458                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36458                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 123497.337607                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123497.337607                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118093.569843                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118093.569843                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 118128.253086                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 118128.253086                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 118128.253086                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 118128.253086                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          234                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          234                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36458                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36458                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36458                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36458                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     17198377                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     17198377                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2464512228                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2464512228                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2481710605                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2481710605                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2481710605                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2481710605                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73497.337607                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73497.337607                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68035.341983                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68035.341983                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68070.398952                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68070.398952                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68070.398952                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68070.398952                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                    88930                       # number of replacements
system.l2c.tags.tagsinuse                64921.564367                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4554585                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   154189                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.538975                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50439.038395                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.855329                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000489                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4115.597994                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2621.496048                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.860554                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.964520                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5480.404826                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2258.346213                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.769639                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000044                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.062799                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.040001                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000044                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.083624                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.034460                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.990624                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65253                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2127                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6981                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56097                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.995682                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 40592424                       # Number of tag accesses
system.l2c.tags.data_accesses                40592424                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker         6056                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3327                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         5249                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         2715                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  17347                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       683633                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          683633                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1666927                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1666927                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              11                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              13                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  24                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            83399                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            82059                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               165458                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        846260                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        834237                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1680497                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       253600                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       258179                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           511779                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6056                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3327                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              846260                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              336999                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          5249                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          2715                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              834237                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              340238                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2375081                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6056                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3327                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             846260                       # number of overall hits
system.l2c.overall_hits::cpu0.data             336999                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         5249                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         2715                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             834237                       # number of overall hits
system.l2c.overall_hits::cpu1.data             340238                       # number of overall hits
system.l2c.overall_hits::total                2375081                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            5                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   10                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1330                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1405                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2735                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          57981                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72450                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130431                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         8141                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         9842                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           17983                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         5631                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         6454                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          12085                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8141                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             63612                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            5                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9842                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             78904                       # number of demand (read+write) misses
system.l2c.demand_misses::total                160509                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8141                       # number of overall misses
system.l2c.overall_misses::cpu0.data            63612                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            5                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9842                       # number of overall misses
system.l2c.overall_misses::cpu1.data            78904                       # number of overall misses
system.l2c.overall_misses::total               160509                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       251000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker        84000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       447000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker        83500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total         865500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       321500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       201500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       523000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       161000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       161000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   4487898000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5568339500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  10056237500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst    663327500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    794138000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   1457465500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    478260000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    540016500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1018276500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       251000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker        84000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    663327500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   4966158000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       447000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker        83500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    794138000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6108356000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     12532845000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       251000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker        84000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    663327500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   4966158000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       447000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker        83500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    794138000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6108356000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    12532845000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         6059                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3328                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         5254                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         2716                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              17357                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       683633                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       683633                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1666927                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1666927                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1341                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1418                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2759                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       141380                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       154509                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295889                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       854401                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       844079                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1698480                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       259231                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       264633                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       523864                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6059                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3328                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          854401                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          400611                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         5254                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         2716                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          844079                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          419142                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2535590                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6059                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3328                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         854401                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         400611                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         5254                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         2716                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         844079                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         419142                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2535590                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000495                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000300                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000952                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000368                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000576                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.991797                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.990832                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991301                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.410108                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.468905                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.440811                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.009528                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011660                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010588                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.021722                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.024388                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.023069                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000495                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000300                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.009528                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.158787                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000952                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000368                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011660                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.188251                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.063302                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000495                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000300                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.009528                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.158787                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000952                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000368                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011660                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.188251                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.063302                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83666.666667                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        84000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        89400                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        83500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total        86550                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   241.729323                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   143.416370                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   191.224863                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        80500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        80500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77402.907849                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76857.688061                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77100.056735                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81479.855055                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.681162                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81046.849803                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84933.404369                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83671.599008                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 84259.536616                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83666.666667                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 81479.855055                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 78069.515186                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89400                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80688.681162                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 77415.035993                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 78081.883259                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker        84000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 81479.855055                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78069.515186                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89400                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80688.681162                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 77415.035993                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 78081.883259                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               82442                       # number of writebacks
system.l2c.writebacks::total                    82442                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            5                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              10                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1330                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1405                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2735                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        57981                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72450                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        130431                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         8141                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         9842                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        17983                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         5631                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         6454                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        12085                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8141                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        63612                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            5                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9842                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        78904                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           160509                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8141                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        63612                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            5                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9842                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        78904                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          160509                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        14424                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16714                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15123                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        12466                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        29547                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        29180                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       221000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        74000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       397000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        73500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total       765500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     25317500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     26732000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     52049500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       141000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       141000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3908088000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4843839500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   8751927500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    581917500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    695718000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   1277635500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    421950000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    475476500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total    897426500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       221000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        74000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    581917500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   4330038000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       397000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    695718000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5319316000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  10927755000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       221000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        74000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    581917500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   4330038000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       397000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    695718000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5319316000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  10927755000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    574512000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2654142000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3237757500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6466411500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    574512000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2654142000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3237757500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6466411500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000495                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000300                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000952                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000368                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000576                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.991797                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.990832                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991301                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.410108                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.468905                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.440811                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009528                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011660                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010588                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.021722                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.024388                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023069                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000495                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000300                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009528                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.158787                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000952                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000368                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011660                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.188251                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.063302                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000495                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000300                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009528                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.158787                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000952                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000368                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011660                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.188251                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.063302                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        79400                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total        76550                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19026.334520                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19030.895795                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        70500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67402.907849                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66857.688061                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 67100.056735                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71479.855055                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.681162                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.849803                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74933.404369                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73671.599008                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74259.536616                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71479.855055                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68069.515186                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        79400                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.681162                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67415.035993                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 68081.883259                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        74000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71479.855055                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68069.515186                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        79400                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.681162                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67415.035993                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 68081.883259                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184008.735441                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193715.298552                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.222610                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89827.799777                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110958.104866                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.596998                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        325066                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       134283                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests          482                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70472                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       118632                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6722                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4502                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            128664                       # Transaction distribution
system.membus.trans_dist::ReadExResp           128664                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30312                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438547                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       546139                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72897                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 619036                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15473916                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     15637269                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17954389                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              498                       # Total snoops (count)
system.membus.snoop_fanout::samples            267453                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.018325                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.134123                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  262552     98.17%     98.17% # Request fanout histogram
system.membus.snoop_fanout::1                    4901      1.83%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              267453                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90452000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1730500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           831225033                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          950845250                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1219623                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests      5058603                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2540370                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        38310                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            250                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          250                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903879904500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              74739                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2297326                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       766075                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1697986                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          142067                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2759                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2761                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           295889                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          295889                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1698504                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       524085                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq         4401                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5113014                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2581913                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        17955                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        33981                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7746863                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    217409912                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96413853                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        24176                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        45252                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              313893193                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          111017                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2716898                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021705                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.145719                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2657927     97.83%     97.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  58971      2.17%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2716898                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4965685500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           389377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2556778000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1275944496                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          11911000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          22668000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------