path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.909645                       # Number of seconds simulated
sim_ticks                                2909644861500                       # Number of ticks simulated
final_tick                               2909644861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 753896                       # Simulator instruction rate (inst/s)
host_op_rate                                   908960                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            19506336140                       # Simulator tick rate (ticks/s)
host_mem_usage                                 580236                       # Number of bytes of host memory used
host_seconds                                   149.16                       # Real time elapsed on the host
sim_insts                                   112454211                       # Number of instructions simulated
sim_ops                                     135584166                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           522464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4660352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           664132                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4241316                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10089736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       522464                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       664132                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1186596                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7511872                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data          8852                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data          8672                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7529396                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             13451                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             73321                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             13543                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             66287                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166625                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117373                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2213                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2168                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121754                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              179563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1601691                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              228252                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1457675                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3467686                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         179563                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         228252                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             407815                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2581714                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               3042                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data               2980                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2587737                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2581714                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             179563                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1604733                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             228252                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1460655                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6055424                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166625                       # Number of read requests accepted
system.physmem.writeReqs                       121754                       # Number of write requests accepted
system.physmem.readBursts                      166625                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     121754                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10658176                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5824                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7541376                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10089736                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7529396                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       91                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10080                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10697                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10657                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18793                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9662                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9670                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10491                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9280                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9982                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9231                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8678                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9823                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10380                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9718                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8284                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8168                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7485                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7667                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6694                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7527                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7260                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
system.physmem.totGap                    2909644504500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  157053                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117373                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    165652                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       613                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5940                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6538                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6903                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        58581                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      310.672197                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.145957                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.231527                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21388     36.51%     36.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14603     24.93%     61.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5975     10.20%     71.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3225      5.51%     77.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2561      4.37%     81.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1528      2.61%     84.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1012      1.73%     85.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1135      1.94%     87.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7154     12.21%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          58581                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5570                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.894255                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      552.382236                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5567     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.04%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5570                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5570                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.155117                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.796345                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       15.496905                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                17      0.31%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 9      0.16%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                8      0.14%      0.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              13      0.23%      0.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4758     85.42%     86.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             105      1.89%     88.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              66      1.18%     89.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              70      1.26%     90.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              40      0.72%     91.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              17      0.31%     91.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              48      0.86%     92.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.18%     92.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             152      2.73%     95.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.14%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.09%     95.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              10      0.18%     95.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              62      1.11%     96.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               9      0.16%     97.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               1      0.02%     97.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              27      0.48%     97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             105      1.89%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.04%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.04%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             4      0.07%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.04%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.13%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.02%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.04%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             5      0.09%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5570                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1610742500                       # Total ticks spent queuing
system.physmem.totMemAccLat                4733255000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    832670000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9672.15                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28422.15                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.59                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.25                       # Average write queue length when enqueuing
system.physmem.readRowHits                     136266                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89520                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.82                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.95                       # Row buffer hit rate for writes
system.physmem.avgGap                     10089654.60                       # Average gap between requests
system.physmem.pageHitRate                      79.39                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  230678280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  125866125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 702226200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                392901840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           190043786400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            90291916755                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1666582969500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1948370345100                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.624992                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2772326098500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     97159400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     40158524000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  212194080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  115780500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 596731200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                370662480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           190043786400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            88418921265                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1668225948000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1947984023925                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.492219                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2775082980250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     97159400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     37402333250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     6403                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                6403                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1830                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4572                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples         6402                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           6402    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         6402                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         5332                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13399.287322                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11603.034588                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7407.871184                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         4008     75.17%     75.17% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1320     24.76%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455            4      0.08%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         5332                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   2989035968                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.330748                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.470482                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     2000419000     66.93%     66.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1      988616968     33.07%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   2989035968                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3528     66.18%     66.18% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1803     33.82%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5331                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6403                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6403                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5331                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5331                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        11734                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12042048                       # DTB read hits
system.cpu0.dtb.read_misses                      5594                       # DTB read misses
system.cpu0.dtb.write_hits                    9609454                       # DTB write hits
system.cpu0.dtb.write_misses                      809                       # DTB write misses
system.cpu0.dtb.flush_tlb                        2941                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3984                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   860                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12047642                       # DTB read accesses
system.cpu0.dtb.write_accesses                9610263                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         21651502                       # DTB hits
system.cpu0.dtb.misses                           6403                       # DTB misses
system.cpu0.dtb.accesses                     21657905                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3203                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3203                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          686                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2517                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3203                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3203    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3203                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2349                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13262.452107                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11543.567684                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6519.168051                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::4096-6143          600     25.54%     25.54% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::10240-12287          662     28.18%     53.72% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::12288-14335          191      8.13%     61.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::14336-16383          387     16.48%     78.33% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-18431            3      0.13%     78.46% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::22528-24575          498     21.20%     99.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-26623            8      0.34%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2349                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   2000380500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     2000380500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   2000380500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1663     70.80%     70.80% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          686     29.20%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2349                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3203                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3203                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2349                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2349                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5552                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    56738612                       # ITB inst hits
system.cpu0.itb.inst_misses                      3203                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        2941                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2371                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                56741815                       # ITB inst accesses
system.cpu0.itb.hits                         56738612                       # DTB hits
system.cpu0.itb.misses                           3203                       # DTB misses
system.cpu0.itb.accesses                     56741815                       # DTB accesses
system.cpu0.numCycles                      2910043779                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3033                       # number of quiesce instructions executed
system.cpu0.committedInsts                   55199902                       # Number of instructions committed
system.cpu0.committedOps                     66610456                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             58846956                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5257                       # Number of float alu accesses
system.cpu0.num_func_calls                    4818664                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7556613                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    58846956                       # number of integer instructions
system.cpu0.num_fp_insts                         5257                       # number of float instructions
system.cpu0.num_int_register_reads          106933232                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          40497320                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3778                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1482                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           240479401                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           25666284                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     22274939                       # number of memory refs
system.cpu0.num_load_insts                   12196843                       # Number of load instructions
system.cpu0.num_store_insts                  10078096                       # Number of store instructions
system.cpu0.num_idle_cycles              2694635007.442764                       # Number of idle cycles
system.cpu0.num_busy_cycles              215408771.557236                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.074023                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.925977                       # Percentage of idle cycles
system.cpu0.Branches                         12742817                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                  133      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 45792240     67.22%     67.22% # Class of executed instruction
system.cpu0.op_class::IntMult                   56099      0.08%     67.30% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              3963      0.01%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::MemRead                12196843     17.90%     85.21% # Class of executed instruction
system.cpu0.op_class::MemWrite               10078096     14.79%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  68127374                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           819099                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.702232                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           43234609                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           819611                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            52.750157                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1736913500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data    43.298558                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   468.403674                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.084567                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.914851                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999418                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        177105423                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       177105423                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     11354436                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     11757578                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23112014                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      9226475                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      9597217                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18823692                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190286                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202415                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       392701                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       213920                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       229309                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       443229                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       221967                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       238239                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460206                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20580911                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21354795                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41935706                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20771197                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21557210                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42328407                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       199328                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       200534                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       399862                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       149618                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       149039                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       298657                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58774                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        59550                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       118324                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10841                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11919                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22760                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       348946                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       349573                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        698519                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       407720                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       409123                       # number of overall misses
system.cpu0.dcache.overall_misses::total       816843                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3302461000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3180866500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6483327500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9863039500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9227377000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  19090416500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137120000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    157150000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    294270000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  13165500500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  12408243500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  25573744000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  13165500500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  12408243500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  25573744000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11553764                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     11958112                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23511876                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9376093                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9746256                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19122349                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       249060                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       261965                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       511025                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       224761                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       241228                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       465989                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       221967                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       238241                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460208                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     20929857                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     21704368                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42634225                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     21178917                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     21966333                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43145250                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017252                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016770                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.017007                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015957                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015292                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015618                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235983                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227320                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231542                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048233                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049410                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048842                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016672                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016106                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016384                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019251                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018625                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018932                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16567.973391                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15861.981011                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16213.912550                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65921.476694                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61912.499413                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63920.874113                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12648.279679                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13184.830942                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12929.261863                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37729.334911                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35495.428709                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36611.379218                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.543756                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30328.882757                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31308.028593                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs          148                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               22                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs     6.727273                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       683901                       # number of writebacks
system.cpu0.dcache.writebacks::total           683901                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          477                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          439                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          916                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7004                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7232                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14236                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          477                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          439                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          916                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          477                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          439                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          916                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       198851                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       200095                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       398946                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149618                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       149039                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       298657                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57662                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58611                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       116273                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3837                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4687                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8524                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       348469                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       349134                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       697603                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       406131                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       407745                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       813876                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15000                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16138                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13390                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14199                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28390                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30337                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3086715500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2967879500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6054595000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9713421500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9078338000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18791759500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    797262500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    818412000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1615674500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52113500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63305500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115419000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12800137000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  12046217500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  24846354500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13597399500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12864629500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  26462029000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3048418500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3229696000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6278114500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3048418500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3229696000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6278114500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017211                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016733                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016968                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015957                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015292                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015618                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231519                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.223736                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227529                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017071                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019430                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018292                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000008                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016649                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016086                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016363                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019176                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018562                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018864                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.755732                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14832.352133                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15176.477518                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64921.476694                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60912.499413                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62920.874113                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13826.480178                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13963.453959                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13895.526046                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13581.834767                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13506.614039                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.473956                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36732.498443                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34503.134899                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35616.754085                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33480.329007                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31550.673828                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements          1695677                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.436645                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          113855199                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1696189                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.124123                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      29075840500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst    59.966796                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   450.469848                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.117123                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.879824                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        117247589                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       117247589                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     55898438                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     57956761                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      113855199                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     55898438                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     57956761                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       113855199                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     55898438                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     57956761                       # number of overall hits
system.cpu0.icache.overall_hits::total      113855199                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       840174                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       856021                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1696195                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       840174                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       856021                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1696195                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       840174                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       856021                       # number of overall misses
system.cpu0.icache.overall_misses::total      1696195                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11888847500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12382350500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  24271198000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11888847500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  12382350500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  24271198000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11888847500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  12382350500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  24271198000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     56738612                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     58812782                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115551394                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     56738612                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     58812782                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115551394                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     56738612                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     58812782                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115551394                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014808                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014555                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014679                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014808                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014555                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014679                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014808                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014555                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014679                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14150.458715                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14465.007868                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.202657                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14150.458715                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14465.007868                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14309.202657                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14150.458715                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14465.007868                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14309.202657                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1695677                       # number of writebacks
system.cpu0.icache.writebacks::total          1695677                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       840174                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       856021                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1696195                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       840174                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       856021                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1696195                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       840174                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       856021                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1696195                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11048673500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11526329500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  22575003000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11048673500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11526329500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  22575003000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11048673500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11526329500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  22575003000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1142893000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1142893000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014808                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014555                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014679                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014808                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014555                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014679                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014808                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014555                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014679                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13150.458715                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13465.007868                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.202657                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13150.458715                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13465.007868                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.202657                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13150.458715                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13465.007868                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.202657                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671                       # average overall mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     6953                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                6953                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2221                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4731                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples         6952                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           6952    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         6952                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5860                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13274.317406                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11562.470731                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7349.012526                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767         5859     99.98%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5860                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples    292297068                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean    -4.609996                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1639785500    561.00%    561.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -1347488432   -461.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total    292297068                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3658     62.43%     62.43% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         2201     37.57%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5859                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6953                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6953                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5859                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5859                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        12812                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12477429                       # DTB read hits
system.cpu1.dtb.read_misses                      5926                       # DTB read misses
system.cpu1.dtb.write_hits                    9996759                       # DTB write hits
system.cpu1.dtb.write_misses                     1027                       # DTB write misses
system.cpu1.dtb.flush_tlb                        2941                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    4677                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   918                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      228                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12483355                       # DTB read accesses
system.cpu1.dtb.write_accesses                9997786                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         22474188                       # DTB hits
system.cpu1.dtb.misses                           6953                       # DTB misses
system.cpu1.dtb.accesses                     22481141                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     3501                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                3501                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          842                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2659                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         3501                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           3501    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         3501                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2700                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13966.111111                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12105.021463                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7193.126612                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         1956     72.44%     72.44% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767          743     27.52%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2700                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1638889000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1638889000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1638889000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1858     68.81%     68.81% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          842     31.19%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2700                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3501                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3501                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2700                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2700                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         6201                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    58812782                       # ITB inst hits
system.cpu1.itb.inst_misses                      3501                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        2941                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2701                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                58816283                       # ITB inst accesses
system.cpu1.itb.hits                         58812782                       # DTB hits
system.cpu1.itb.misses                           3501                       # DTB misses
system.cpu1.itb.accesses                     58816283                       # DTB accesses
system.cpu1.numCycles                      2909245944                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   57254309                       # Number of instructions committed
system.cpu1.committedOps                     68973710                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             61043070                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5904                       # Number of float alu accesses
system.cpu1.num_func_calls                    5072826                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      7673629                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    61043070                       # number of integer instructions
system.cpu1.num_fp_insts                         5904                       # number of float instructions
system.cpu1.num_int_register_reads          111123439                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          42146017                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4671                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1234                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           249248543                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           26227592                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     23131346                       # number of memory refs
system.cpu1.num_load_insts                   12645224                       # Number of load instructions
system.cpu1.num_store_insts                  10486122                       # Number of store instructions
system.cpu1.num_idle_cycles              2689856281.302534                       # Number of idle cycles
system.cpu1.num_busy_cycles              219389662.697466                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.075411                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.924589                       # Percentage of idle cycles
system.cpu1.Branches                         13172935                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                 2204      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 47380499     67.13%     67.14% # Class of executed instruction
system.cpu1.op_class::IntMult                   58319      0.08%     67.22% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4490      0.01%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::MemRead                12645224     17.92%     85.14% # Class of executed instruction
system.cpu1.op_class::MemWrite               10486122     14.86%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  70576858                       # Class of executed instruction
system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46333000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                98000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               336000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                95000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy               644000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6279500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36457000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           187070020                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36418                       # number of replacements
system.iocache.tags.tagsinuse                1.084263                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         313834387000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.084263                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067766                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067766                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328068                       # Number of tag accesses
system.iocache.tags.data_accesses              328068                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          228                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36452                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36452                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36452                       # number of overall misses
system.iocache.overall_misses::total            36452                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28181877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28181877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4548907143                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4548907143                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   4577089020                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   4577089020                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   4577089020                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   4577089020                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36452                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36452                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36452                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36452                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123604.723684                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125564.825524                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125564.825524                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125564.825524                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125564.825524                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        36452                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        36452                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        36452                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        36452                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16781877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16781877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2736290629                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2736290629                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   2753072506                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   2753072506                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   2753072506                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   2753072506                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75525.965818                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75525.965818                       # average overall mshr miss latency
system.l2c.tags.replacements                    87562                       # number of replacements
system.l2c.tags.tagsinuse                64865.213908                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4551019                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   152797                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.784741                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50199.163746                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.905024                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4089.871618                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2504.674114                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.838098                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000605                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5610.944787                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2455.815915                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.765978                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000029                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.062406                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.038218                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000043                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.085616                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.037473                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989765                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65231                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6849                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56202                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.995346                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 40564313                       # Number of tag accesses
system.l2c.tags.data_accesses                40564313                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5816                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3025                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6360                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3489                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  18690                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       683901                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          683901                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1664900                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1664900                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              15                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               8                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  23                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            80918                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            86062                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               166980                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        832345                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        845838                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1678183                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       253790                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       257782                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           511572                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5816                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3025                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              832345                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              334708                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6360                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3489                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              845838                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              343844                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2375425                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5816                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3025                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             832345                       # number of overall hits
system.l2c.overall_hits::cpu0.data             334708                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6360                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3489                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             845838                       # number of overall hits
system.l2c.overall_hits::cpu1.data             343844                       # number of overall hits
system.l2c.overall_hits::total                2375425                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                    8                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1389                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1353                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2742                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          67296                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          61616                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             128912                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         7811                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10168                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           17979                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         6560                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         5611                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          12171                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7811                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             73856                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             67227                       # number of demand (read+write) misses
system.l2c.demand_misses::total                159070                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7811                       # number of overall misses
system.l2c.overall_misses::cpu0.data            73856                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10168                       # number of overall misses
system.l2c.overall_misses::cpu1.data            67227                       # number of overall misses
system.l2c.overall_misses::total               159070                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       530500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       398500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker       133000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        1062000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1012500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       780000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1792500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       159000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8529037500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   7843663000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  16372700500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1020054500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1330939500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2350994000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    872232500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    739124500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1611357000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       530500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1020054500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   9401270000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       398500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1330939500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   8582787500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     20336113500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       530500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1020054500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   9401270000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       398500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1330939500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   8582787500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    20336113500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         5820                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3025                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         6363                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         3490                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              18698                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       683901                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       683901                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1664900                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1664900                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1404                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1361                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2765                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       148214                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       147678                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295892                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       840156                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       856006                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1696162                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       260350                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       263393                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       523743                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         5820                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3025                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          840156                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          408564                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         6363                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         3490                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          856006                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          411071                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2534495                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         5820                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3025                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         840156                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         408564                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         6363                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         3490                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         856006                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         411071                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2534495                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000687                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000471                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000287                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000428                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989316                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.994122                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991682                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.454046                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.417232                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.435672                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.009297                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011878                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010600                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.025197                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021303                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.023238                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000687                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.009297                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.180770                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000471                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000287                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011878                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.163541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.062762                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000687                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.009297                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.180770                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000471                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000287                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011878                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.163541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.062762                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       132625                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total       132750                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   728.941685                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   576.496674                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   653.719912                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126739.144971                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127299.126850                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127006.799212                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130592.049674                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130894.915421                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 130763.335002                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132962.271341                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131727.766886                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 132393.147646                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 130592.049674                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 127291.892331                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 130894.915421                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 127668.756601                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 127843.801471                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 130592.049674                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 127291.892331                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 130894.915421                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 127668.756601                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 127843.801471                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               81183                       # number of writebacks
system.l2c.writebacks::total                    81183                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total               8                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1389                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1353                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2742                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        67296                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        61616                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        128912                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         7811                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10168                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        17979                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6560                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         5611                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        12171                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7811                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        73856                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        67227                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           159070                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7811                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        73856                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        67227                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          159070                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15000                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16138                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        13390                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14199                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        28390                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        30337                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       490500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       368500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       123000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total       982000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     94515000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     92030500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    186545500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7856077500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   7227503000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  15083580500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    941944500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1229259500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2171204000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    806632500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    683014500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1489647000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       490500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    941944500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   8662710000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       368500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1229259500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   7910517500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  18745413500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       490500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    941944500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   8662710000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       368500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1229259500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   7910517500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  18745413500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2860870000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3027916000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6918904000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2860870000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3027916000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6918904000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000687                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000287                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000428                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989316                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.994122                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991682                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.454046                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.417232                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.435672                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009297                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011878                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010600                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.025197                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021303                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023238                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000687                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009297                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.180770                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000287                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011878                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.163541                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.062762                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000687                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009297                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.180770                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000287                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011878                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.163541                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.062762                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total       122750                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68045.356371                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68019.586105                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68032.640408                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116739.144971                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117299.126850                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117006.799212                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120592.049674                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120894.915421                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120763.335002                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122962.271341                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121727.766886                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122393.147646                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120592.049674                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117291.892331                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120894.915421                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117668.756601                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 117843.801471                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120592.049674                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117291.892331                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120894.915421                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117668.756601                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 117843.801471                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669                       # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70546                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       117373                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6607                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            127157                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127157                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30386                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       434320                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       541912                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        72885                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        72885                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 614797                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15302012                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     15465365                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17782485                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              492                       # Total snoops (count)
system.membus.snoop_fanout::samples            390010                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  390010    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              390010                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90443000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1721000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           823181865                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          943214000                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            1187123                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5053855                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2538047                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        38136                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            581                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              74697                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2294848                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       801289                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1695677                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          141805                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2765                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2767                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           295892                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          295892                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1696195                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       523971                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5106078                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2581570                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18395                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34840                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7740883                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    217113784                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96423069                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26060                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        48732                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              313611645                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          176532                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2781330                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021292                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.144357                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2722109     97.87%     97.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  59221      2.13%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2781330                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4961202000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           380377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2553314500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1275768500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          11880000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          22657000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------