path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.909654                       # Number of seconds simulated
sim_ticks                                2909653700500                       # Number of ticks simulated
final_tick                               2909653700500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 367664                       # Simulator instruction rate (inst/s)
host_op_rate                                   443285                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9513271691                       # Simulator tick rate (ticks/s)
host_mem_usage                                 578564                       # Number of bytes of host memory used
host_seconds                                   305.85                       # Real time elapsed on the host
sim_insts                                   112450652                       # Number of instructions simulated
sim_ops                                     135579653                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           521248                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4656256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           665348                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4245540                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10089864                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       521248                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       665348                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1186596                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7511936                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data          8852                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data          8672                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7529460                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             13432                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             73257                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             13562                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             66353                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166627                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117374                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2213                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2168                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121755                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              179144                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1600278                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              228669                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1459122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3467720                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         179144                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         228669                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             407813                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2581729                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               3042                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data               2980                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2587751                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2581729                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             179144                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1603321                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             228669                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1462103                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6055471                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166627                       # Number of read requests accepted
system.physmem.writeReqs                       121755                       # Number of write requests accepted
system.physmem.readBursts                      166627                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     121755                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10658432                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5696                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7541440                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10089864                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7529460                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       89                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          47114                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10080                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10697                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10658                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18793                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9660                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9676                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10492                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9982                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9231                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8678                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9823                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10380                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9720                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8284                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8168                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7485                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7667                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6694                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7527                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
system.physmem.perBankWrBursts::14               7261                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
system.physmem.totGap                    2909653343500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  157055                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117374                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    165652                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       617                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2515                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6773                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7042                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6467                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6039                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        58556                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      310.810301                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.232220                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.272692                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21388     36.53%     36.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14563     24.87%     61.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6001     10.25%     71.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3238      5.53%     77.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2533      4.33%     81.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1526      2.61%     84.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1009      1.72%     85.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1158      1.98%     87.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7140     12.19%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          58556                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5712                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        29.151786                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      545.492775                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5709     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.04%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5712                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5712                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.629377                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.719500                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.211627                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                18      0.32%      0.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 9      0.16%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                8      0.14%      0.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              11      0.19%      0.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4765     83.42%     84.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             125      2.19%     86.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              59      1.03%     87.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             204      3.57%     91.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              32      0.56%     91.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             148      2.59%     94.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              51      0.89%     95.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               8      0.14%     95.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               9      0.16%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              17      0.30%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.09%     95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               8      0.14%     95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             167      2.92%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.09%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               6      0.11%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              19      0.33%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.07%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.04%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.02%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.05%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.02%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.04%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.04%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            15      0.26%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.04%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5712                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1608810750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4731398250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    832690000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9660.32                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28410.32                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.59                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.25                       # Average write queue length when enqueuing
system.physmem.readRowHits                     136274                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89542                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.97                       # Row buffer hit rate for writes
system.physmem.avgGap                     10089580.29                       # Average gap between requests
system.physmem.pageHitRate                      79.40                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  230519520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  125779500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 702273000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                392901840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           190044294960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            90285662430                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1666593127500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1948374558750                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.624648                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2772342347250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     97159660000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     40149801500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  212163840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  115764000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 596715600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                370668960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           190044294960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            88503009660                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1668156858000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1947999475020                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.495738                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2774969217000                       # Time in different power states
system.physmem_1.memoryStateTime::REF     97159660000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     37524675500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     6385                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                6385                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1824                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4559                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            2                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples         6383                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           6383    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         6383                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         5318                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 13413.689357                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11614.000174                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7416.349168                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         3990     75.03%     75.03% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1324     24.90%     99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455            4      0.08%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         5318                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1993677436                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean    -0.003389                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     2000434000    100.34%    100.34% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1       -6756564     -0.34%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1993677436                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3519     66.20%     66.20% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1797     33.80%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5316                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6385                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6385                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5316                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5316                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        11701                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12043498                       # DTB read hits
system.cpu0.dtb.read_misses                      5581                       # DTB read misses
system.cpu0.dtb.write_hits                    9607194                       # DTB write hits
system.cpu0.dtb.write_misses                      804                       # DTB write misses
system.cpu0.dtb.flush_tlb                        2940                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3980                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   867                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12049079                       # DTB read accesses
system.cpu0.dtb.write_accesses                9607998                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         21650692                       # DTB hits
system.cpu0.dtb.misses                           6385                       # DTB misses
system.cpu0.dtb.accesses                     21657077                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3199                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3199                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          683                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2516                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3199                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3199    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3199                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2347                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 13274.818918                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11551.422255                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6527.623179                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::4096-6143          600     25.56%     25.56% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::10240-12287          656     27.95%     53.52% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::12288-14335          193      8.22%     61.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::14336-16383          387     16.49%     78.23% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-18431            3      0.13%     78.36% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::22528-24575          500     21.30%     99.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-26623            8      0.34%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2347                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   2000380500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     2000380500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   2000380500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1664     70.90%     70.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          683     29.10%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2347                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3199                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3199                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2347                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2347                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5546                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    56739503                       # ITB inst hits
system.cpu0.itb.inst_misses                      3199                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        2940                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2369                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                56742702                       # ITB inst accesses
system.cpu0.itb.hits                         56739503                       # DTB hits
system.cpu0.itb.misses                           3199                       # DTB misses
system.cpu0.itb.accesses                     56742702                       # DTB accesses
system.cpu0.numCycles                      2910044532                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3033                       # number of quiesce instructions executed
system.cpu0.committedInsts                   55201459                       # Number of instructions committed
system.cpu0.committedOps                     66609946                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             58847772                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5145                       # Number of float alu accesses
system.cpu0.num_func_calls                    4820077                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7555989                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    58847772                       # number of integer instructions
system.cpu0.num_fp_insts                         5145                       # number of float instructions
system.cpu0.num_int_register_reads          106933475                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          40499308                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                3730                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1418                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           240486031                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           25664833                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     22274491                       # number of memory refs
system.cpu0.num_load_insts                   12198391                       # Number of load instructions
system.cpu0.num_store_insts                  10076100                       # Number of store instructions
system.cpu0.num_idle_cycles              2694628360.005429                       # Number of idle cycles
system.cpu0.num_busy_cycles              215416171.994570                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.074025                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.925975                       # Percentage of idle cycles
system.cpu0.Branches                         12743161                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                  131      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 45792912     67.22%     67.22% # Class of executed instruction
system.cpu0.op_class::IntMult                   56104      0.08%     67.30% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              3963      0.01%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.30% # Class of executed instruction
system.cpu0.op_class::MemRead                12198391     17.91%     85.21% # Class of executed instruction
system.cpu0.op_class::MemWrite               10076100     14.79%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  68127601                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           819018                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.702192                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           43232909                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           819530                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            52.753296                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1736913500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data    43.309115                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   468.393077                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.084588                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.914830                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999418                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        177098246                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       177098246                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     11355856                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     11755360                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23111216                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      9224406                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      9598440                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18822846                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190279                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202400                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       392679                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       213881                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       229331                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       443212                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       221919                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       238270                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460189                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20580262                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21353800                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41934062                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20770541                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21556200                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42326741                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       199428                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       200396                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       399824                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       149476                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       149150                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       298626                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58742                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        59581                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       118323                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10843                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11913                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22756                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       348904                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       349546                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        698450                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       407646                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       409127                       # number of overall misses
system.cpu0.dcache.overall_misses::total       816773                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3300764500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3177768500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6478533000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9862313500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9244759000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  19107072500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137644000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    156454000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    294098000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  13163078000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  12422527500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  25585605500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  13163078000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  12422527500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  25585605500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11555284                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     11955756                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23511040                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9373882                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9747590                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19121472                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       249021                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       261981                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       511002                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       224724                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       241244                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       465968                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       221919                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       238272                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460191                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     20929166                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     21703346                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42632512                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     21178187                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     21965327                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43143514                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017259                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016761                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.017006                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015946                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015301                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015617                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235892                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227425                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231551                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048250                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049382                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048836                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016671                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016106                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016383                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019248                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018626                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018932                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16551.158814                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15857.444759                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16203.462023                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65979.244160                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61982.963460                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63983.285112                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12694.272803                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13133.047931                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12923.976094                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37726.933483                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35539.034920                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36631.978667                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.462804                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30363.499598                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31325.234184                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       683842                       # number of writebacks
system.cpu0.dcache.writebacks::total           683842                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          485                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          439                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          924                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7005                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7232                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14237                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          485                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          439                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          924                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          485                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          439                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          924                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       198943                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       199957                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       398900                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149476                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       149150                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       298626                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57623                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58651                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       116274                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3838                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4681                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8519                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       348419                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       349107                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       697526                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       406042                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       407758                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       813800                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15006                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16132                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13389                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14200                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28395                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30332                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3085102500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2965375000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6050477500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9712837500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9095609000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18808446500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    798019000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    816464500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1614483500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52409500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62952500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115362000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12797940000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  12060984000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  24858924000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13595959000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12877448500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  26473407500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3049211500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3229832500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6279044000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2494979500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2594954500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5089934000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5544191000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5824787000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368978000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017217                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016725                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016966                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015946                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015301                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231398                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.223875                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227541                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017079                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019404                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018282                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000008                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016648                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016085                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016361                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019173                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018564                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018863                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15507.469476                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14830.063464                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15167.905490                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64979.244160                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60982.963460                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62983.285112                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13848.966558                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13920.725989                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13885.163493                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13655.419489                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13448.515275                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.730250                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36731.464128                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34548.101298                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.705941                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33484.119869                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31581.105705                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.606414                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203199.486872                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200212.775849                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201652.129231                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186345.470162                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182743.274648                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.427743                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195252.368375                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192034.386127                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193590.307695                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1695285                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.436603                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          113852008                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1695797                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.137758                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      29075840500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst    59.971705                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   450.464899                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.117132                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.879814                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.996946                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        117243614                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       117243614                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     55899037                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     57952971                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      113852008                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     55899037                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     57952971                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       113852008                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     55899037                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     57952971                       # number of overall hits
system.cpu0.icache.overall_hits::total      113852008                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       840466                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       855337                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1695803                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       840466                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       855337                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1695803                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       840466                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       855337                       # number of overall misses
system.cpu0.icache.overall_misses::total      1695803                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11890019000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12374432000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  24264451000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11890019000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  12374432000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  24264451000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11890019000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  12374432000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  24264451000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     56739503                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     58808308                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115547811                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     56739503                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     58808308                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115547811                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     56739503                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     58808308                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115547811                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014813                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014544                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014676                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014813                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014544                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014676                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014813                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014544                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014676                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14146.936342                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.317560                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14308.531710                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14146.936342                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14467.317560                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14308.531710                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14146.936342                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14467.317560                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14308.531710                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks      1695285                       # number of writebacks
system.cpu0.icache.writebacks::total          1695285                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       840466                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       855337                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1695803                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       840466                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       855337                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1695803                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       840466                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       855337                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1695803                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11049553000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11519095000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  22568648000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11049553000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11519095000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  22568648000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11049553000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11519095000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  22568648000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1142893000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1142893000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014813                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014544                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014676                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014813                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014544                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014676                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014813                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014544                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014676                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13146.936342                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13467.317560                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13308.531710                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13146.936342                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13467.317560                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13308.531710                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13146.936342                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13467.317560                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13308.531710                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     6953                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                6953                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2226                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4727                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         6953                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           6953    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         6953                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5856                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13269.296448                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11561.565854                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7342.287931                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767         5855     99.98%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5856                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1639416500                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1639416500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1639416500                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3650     62.33%     62.33% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         2206     37.67%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5856                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6953                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6953                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5856                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5856                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        12809                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12475099                       # DTB read hits
system.cpu1.dtb.read_misses                      5924                       # DTB read misses
system.cpu1.dtb.write_hits                    9998125                       # DTB write hits
system.cpu1.dtb.write_misses                     1029                       # DTB write misses
system.cpu1.dtb.flush_tlb                        2942                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    4683                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   921                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      228                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12481023                       # DTB read accesses
system.cpu1.dtb.write_accesses                9999154                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         22473224                       # DTB hits
system.cpu1.dtb.misses                           6953                       # DTB misses
system.cpu1.dtb.accesses                     22480177                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     3510                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                3510                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          846                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2664                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         3510                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           3510    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         3510                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2707                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13960.103436                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12104.099399                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7184.126564                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         1964     72.55%     72.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767          742     27.41%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2707                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1638889000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1638889000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1638889000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1861     68.75%     68.75% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          846     31.25%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2707                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3510                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3510                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2707                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2707                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         6217                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    58808308                       # ITB inst hits
system.cpu1.itb.inst_misses                      3510                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        2942                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2708                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                58811818                       # ITB inst accesses
system.cpu1.itb.hits                         58808308                       # DTB hits
system.cpu1.itb.misses                           3510                       # DTB misses
system.cpu1.itb.accesses                     58811818                       # DTB accesses
system.cpu1.numCycles                      2909262869                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                   57249193                       # Number of instructions committed
system.cpu1.committedOps                     68969707                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             61038090                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5951                       # Number of float alu accesses
system.cpu1.num_func_calls                    5071147                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      7673896                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    61038090                       # number of integer instructions
system.cpu1.num_fp_insts                         5951                       # number of float instructions
system.cpu1.num_int_register_reads          111115264                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          42140927                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4654                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1298                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           249224724                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           26227815                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     23129732                       # number of memory refs
system.cpu1.num_load_insts                   12642519                       # Number of load instructions
system.cpu1.num_store_insts                  10487213                       # Number of store instructions
system.cpu1.num_idle_cycles              2689871255.481362                       # Number of idle cycles
system.cpu1.num_busy_cycles              219391613.518638                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.075411                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.924589                       # Percentage of idle cycles
system.cpu1.Branches                         13171953                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                 2206      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 47377307     67.13%     67.14% # Class of executed instruction
system.cpu1.op_class::IntMult                   58319      0.08%     67.22% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4478      0.01%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::MemRead                12642519     17.91%     85.14% # Class of executed instruction
system.cpu1.op_class::MemWrite               10487213     14.86%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  70572042                       # Class of executed instruction
system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             46335000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                98000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                30000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                16000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                95000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               644000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               52000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             6286500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              172500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            36458500                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              126500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186202055                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               37000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36418                       # number of replacements
system.iocache.tags.tagsinuse                1.084308                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         313834390000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.084308                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067769                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067769                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328068                       # Number of tag accesses
system.iocache.tags.data_accesses              328068                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          228                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          228                       # number of demand (read+write) misses
system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          228                       # number of overall misses
system.iocache.overall_misses::total              228                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28182877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28182877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4712497178                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4712497178                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28182877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28182877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28182877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28182877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          228                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             228                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          228                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            228                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 123609.109649                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123609.109649                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130093.230400                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130093.230400                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123609.109649                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123609.109649                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123609.109649                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123609.109649                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           617                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   60                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.283333                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          228                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16782877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16782877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2901297178                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2901297178                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16782877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16782877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16782877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16782877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73609.109649                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73609.109649                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80093.230400                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80093.230400                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73609.109649                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 73609.109649                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73609.109649                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 73609.109649                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    87564                       # number of replacements
system.l2c.tags.tagsinuse                64865.205876                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4550112                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   152799                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.778415                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50199.141301                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.905024                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4090.389058                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2504.726247                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.838093                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000605                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5610.428826                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2455.776722                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.765978                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000029                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.062414                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.038219                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000043                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.085608                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.037472                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989764                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65231                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6848                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56203                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.995346                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 40556804                       # Number of tag accesses
system.l2c.tags.data_accesses                40556804                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5806                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3022                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6360                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3498                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  18686                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks       683842                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          683842                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks      1664516                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total         1664516                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               9                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  23                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            80852                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            86095                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               166947                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        832656                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        845134                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1677790                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       253841                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       257681                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           511522                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5806                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3022                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              832656                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              334693                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6360                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3498                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              845134                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              343776                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2374945                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5806                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3022                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             832656                       # number of overall hits
system.l2c.overall_hits::cpu0.data             334693                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6360                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3498                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             845134                       # number of overall hits
system.l2c.overall_hits::cpu1.data             343776                       # number of overall hits
system.l2c.overall_hits::total                2374945                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                    8                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1384                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1358                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2742                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          67226                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          61688                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             128914                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         7792                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10187                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           17979                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         6563                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         5608                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          12171                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              7792                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             73789                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10187                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             67296                       # number of demand (read+write) misses
system.l2c.demand_misses::total                159072                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             7792                       # number of overall misses
system.l2c.overall_misses::cpu0.data            73789                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10187                       # number of overall misses
system.l2c.overall_misses::cpu1.data            67296                       # number of overall misses
system.l2c.overall_misses::total               159072                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       530500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       398500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker       133000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        1062000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data      1048500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data       809000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1857500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       159000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8525926000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   7856246500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  16382172500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1017223000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1332151500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2349374500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    871059500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    735537500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1606597000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       530500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1017223000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   9396985500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       398500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1332151500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   8591784000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     20339206000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       530500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1017223000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   9396985500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       398500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1332151500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   8591784000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    20339206000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         5810                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3022                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         6363                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         3499                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              18694                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks       683842                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       683842                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks      1664516                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total      1664516                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1398                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1367                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2765                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       148078                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       147783                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           295861                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       840448                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       855321                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1695769                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       260404                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       263289                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       523693                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         5810                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3022                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          840448                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          408482                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         6363                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         3499                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          855321                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          411072                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2534017                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         5810                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3022                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         840448                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         408482                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         6363                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         3499                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         855321                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         411072                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2534017                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000688                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000471                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000286                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000428                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.989986                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.993416                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991682                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.453990                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.417423                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.435725                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.009271                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011910                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010602                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.025203                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.021300                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.023241                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000688                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.009271                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.180642                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000471                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000286                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011910                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.163709                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.062775                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000688                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.009271                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.180642                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000471                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000286                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011910                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.163709                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.062775                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       132625                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total       132750                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   757.586705                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   595.729013                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   677.425237                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126824.829679                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127354.534107                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127078.304141                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130547.099589                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130769.755571                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 130673.257690                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132722.763980                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131158.612696                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 132002.054063                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 130547.099589                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 127349.408448                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 130769.755571                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 127671.540656                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 127861.634983                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 130547.099589                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 127349.408448                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 130769.755571                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 127671.540656                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 127861.634983                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81184                       # number of writebacks
system.l2c.writebacks::total                    81184                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total               8                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1384                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1358                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2742                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        67226                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        61688                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        128914                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         7792                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10187                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        17979                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6563                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         5608                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        12171                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         7792                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        73789                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10187                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        67296                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           159072                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         7792                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        73789                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10187                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        67296                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          159072                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15006                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16132                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        13389                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14200                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        28395                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        30332                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       490500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       368500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       123000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total       982000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     98005000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     96151000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    194156000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7853666000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   7239366500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  15093032500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    939303000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1230281500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2169584500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    805429500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    679457500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1484887000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       490500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    939303000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   8659095500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       368500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1230281500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   7918824000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  18748486000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       490500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    939303000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   8659095500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       368500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1230281500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   7918824000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  18748486000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2861588500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3028128000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6919834500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2340936000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2431594500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4772530500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5202524500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5459722500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11692365000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000688                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000428                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989986                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.993416                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991682                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.453990                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.417423                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.435725                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009271                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011910                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010602                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.025203                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021300                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023241                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000688                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009271                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.180642                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011910                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.163709                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.062775                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000688                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009271                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.180642                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011910                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.163709                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.062775                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total       122750                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70812.861272                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70803.387334                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70808.169220                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116824.829679                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117354.534107                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117078.304141                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120547.099589                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120769.755571                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120673.257690                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122722.763980                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121158.612696                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122002.054063                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120547.099589                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117349.408448                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120769.755571                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117671.540656                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 117861.634983                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120547.099589                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117349.408448                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120769.755571                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117671.540656                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 117861.634983                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190696.288151                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187709.397471                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172306.635956                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174840.241990                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171239.049296                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.715720                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183219.739391                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179998.763682                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 172583.580569                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70546                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       117374                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6393                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4499                       # Transaction distribution
system.membus.trans_dist::ReadExReq            127159                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127159                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30386                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438823                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       546415                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 655309                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15302204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     15465557                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17782677                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              492                       # Total snoops (count)
system.membus.snoop_fanout::samples            390002                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  390002    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              390002                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90453500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1722000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           823113783                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          952221498                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64071640                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5052869                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2537534                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        38120                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            581                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              74671                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2294380                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       801219                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean      1664516                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          134433                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2765                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2767                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           295861                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          295861                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1695803                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       523921                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5074132                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2573976                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18410                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34795                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7701313                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    215094328                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96414109                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26084                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        48692                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              311583213                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          176501                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          2780821                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021276                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.144303                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                2721656     97.87%     97.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  59165      2.13%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            2780821                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         4960265000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           380377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2552726500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1275647499                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          11889000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          22622000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------