path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.909388                       # Number of seconds simulated
sim_ticks                                2909387991500                       # Number of ticks simulated
final_tick                               2909387991500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 670421                       # Simulator instruction rate (inst/s)
host_op_rate                                   808321                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            17345176485                       # Simulator tick rate (ticks/s)
host_mem_usage                                 625252                       # Number of bytes of host memory used
host_seconds                                   167.73                       # Real time elapsed on the host
sim_insts                                   112452815                       # Number of instructions simulated
sim_ops                                     135583410                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           538144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4761988                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           646852                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          4138720                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10087176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       538144                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       646852                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1184996                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      7517248                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data          8860                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data          8664                       # Number of bytes written to this memory
system.physmem.bytes_written::total           7534772                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             13696                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             74910                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             13273                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             64683                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                166585                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          117457                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2215                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2166                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               121838                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              184968                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1636766                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst              222333                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data             1422540                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3467113                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         184968                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst         222333                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             407301                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2583790                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               3045                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data               2978                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2589813                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2583790                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             184968                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1639812                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst             222333                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1425518                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6056926                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        166585                       # Number of read requests accepted
system.physmem.writeReqs                       121838                       # Number of write requests accepted
system.physmem.readBursts                      166585                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     121838                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 10654272                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7168                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   7548800                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  10087176                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                7534772                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      112                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          40727                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10228                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9700                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10356                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10495                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18506                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10022                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10178                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10614                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9477                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10047                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9317                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9342                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9423                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10228                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9339                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9201                       # Per bank write bursts
system.physmem.perBankWrBursts::0                7595                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7036                       # Per bank write bursts
system.physmem.perBankWrBursts::2                7887                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8047                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7152                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7580                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7566                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7770                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7275                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7619                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6806                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7096                       # Per bank write bursts
system.physmem.perBankWrBursts::12               7204                       # Per bank write bursts
system.physmem.perBankWrBursts::13               7753                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6924                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6640                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    2909387547000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  157013                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 117457                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    165681                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       523                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5781                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5826                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     7640                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7823                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     7672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     6968                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5809                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      226                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        58549                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      310.902116                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     183.522866                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.172226                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21290     36.36%     36.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        14652     25.03%     61.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6083     10.39%     71.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3178      5.43%     77.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2491      4.25%     81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1565      2.67%     84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1038      1.77%     85.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1041      1.78%     87.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7211     12.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          58549                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5743                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.986941                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      548.492879                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5740     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5743                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5743                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.538046                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.602147                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.025411                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                27      0.47%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                14      0.24%      0.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               12      0.21%      0.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              14      0.24%      1.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4750     82.71%     83.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             125      2.18%     86.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              82      1.43%     87.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             205      3.57%     91.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              32      0.56%     91.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             152      2.65%     94.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              51      0.89%     95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.10%     95.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              11      0.19%     95.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              18      0.31%     95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.16%     95.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.02%     95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             172      2.99%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               6      0.10%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               5      0.09%     99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              21      0.37%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.02%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.05%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.02%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.02%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.24%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.05%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5743                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1603192250                       # Total ticks spent queuing
system.physmem.totMemAccLat                4724561000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    832365000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9630.34                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28380.34                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.59                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         7.27                       # Average write queue length when enqueuing
system.physmem.readRowHits                     136293                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     89580                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.87                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.95                       # Row buffer hit rate for writes
system.physmem.avgGap                     10087224.48                       # Average gap between requests
system.physmem.pageHitRate                      79.41                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  229158720                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  125037000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 702772200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                392901840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           190027003920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            90369730305                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1666360544250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1948207148235                       # Total energy per rank (pJ)
system.physmem_0.averagePower              669.628037                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2771956641500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     97150820000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     40279614750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  213471720                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  116477625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 595709400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                371414160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           190027003920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            88357601520                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1668125569500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1947807247845                       # Total energy per rank (pJ)
system.physmem_1.averagePower              669.490585                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2774916457500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     97150820000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     37320566000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     6929                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                6929                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         2193                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4735                       # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples         6928                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           6928    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         6928                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples         5821                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev  7211.949482                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383         4588     78.82%     78.82% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1229     21.11%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-147455            4      0.07%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total         5821                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   1237488496                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean    -0.616549                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     2000461000    161.65%    161.65% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     -762972504    -61.65%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   1237488496                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3649     62.70%     62.70% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         2171     37.30%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         5820                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6929                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6929                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5820                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5820                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        12749                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    12044488                       # DTB read hits
system.cpu0.dtb.read_misses                      5975                       # DTB read misses
system.cpu0.dtb.write_hits                    9654865                       # DTB write hits
system.cpu0.dtb.write_misses                      954                       # DTB write misses
system.cpu0.dtb.flush_tlb                        2940                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     481                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    4388                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   864                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      231                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                12050463                       # DTB read accesses
system.cpu0.dtb.write_accesses                9655819                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         21699353                       # DTB hits
system.cpu0.dtb.misses                           6929                       # DTB misses
system.cpu0.dtb.accesses                     21706282                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3426                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3426                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1          828                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2598                       # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples         3426                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3426    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3426                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples         2558                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev  6399.295854                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::4096-6143          694     27.13%     27.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::10240-12287          823     32.17%     59.30% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::12288-14335          178      6.96%     66.26% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::14336-16383          343     13.41%     79.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-18431            1      0.04%     79.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::22528-24575          515     20.13%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-26623            4      0.16%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total         2558                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   2000380500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     2000380500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   2000380500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1730     67.63%     67.63% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          828     32.37%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2558                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3426                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3426                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2558                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2558                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5984                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    56823446                       # ITB inst hits
system.cpu0.itb.inst_misses                      3426                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        2940                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     481                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2582                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                56826872                       # ITB inst accesses
system.cpu0.itb.hits                         56823446                       # DTB hits
system.cpu0.itb.misses                           3426                       # DTB misses
system.cpu0.itb.accesses                     56826872                       # DTB accesses
system.cpu0.numCycles                      2910048510                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   55288600                       # Number of instructions committed
system.cpu0.committedOps                     66713599                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             58931600                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5354                       # Number of float alu accesses
system.cpu0.num_func_calls                    4809440                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      7565706                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    58931600                       # number of integer instructions
system.cpu0.num_fp_insts                         5354                       # number of float instructions
system.cpu0.num_int_register_reads          107138015                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          40582750                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                4124                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1232                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           240777875                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           25734446                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     22316238                       # number of memory refs
system.cpu0.num_load_insts                   12197914                       # Number of load instructions
system.cpu0.num_store_insts                  10118324                       # Number of store instructions
system.cpu0.num_idle_cycles              2666885275.671365                       # Number of idle cycles
system.cpu0.num_busy_cycles              243163234.328635                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.083560                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.916440                       # Percentage of idle cycles
system.cpu0.Branches                         12750711                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                  119      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 45844704     67.20%     67.20% # Class of executed instruction
system.cpu0.op_class::IntMult                   57827      0.08%     67.28% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.28% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              3997      0.01%     67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.29% # Class of executed instruction
system.cpu0.op_class::MemRead                12197914     17.88%     85.17% # Class of executed instruction
system.cpu0.op_class::MemWrite               10118324     14.83%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  68222885                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3033                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           821400                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.702036                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           43232181                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           821912                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            52.599525                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1736913500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   174.965504                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   336.736532                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.341730                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.657689                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999418                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          344                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2          105                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        177107266                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       177107266                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     11359748                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     11750430                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       23110178                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data      9271451                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      9551716                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      18823167                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190318                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202376                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       392694                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       212739                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       230449                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       443188                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       220738                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       239445                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       460183                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     20631199                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     21302146                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        41933345                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     20821517                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     21504522                       # number of overall hits
system.cpu0.dcache.overall_hits::total       42326039                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       197790                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       204093                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       401883                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       151382                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       147597                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       298979                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58506                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        59775                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       118281                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10799                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11977                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        22776                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       349172                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       351690                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        700862                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       407678                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       411465                       # number of overall misses
system.cpu0.dcache.overall_misses::total       819143                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3205236500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3305769000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   6511005500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10124353500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   8964207000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  19088560500                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137582000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    157353000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    294935000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  13329590000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  12269976000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  25599566000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  13329590000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  12269976000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  25599566000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     11557538                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     11954523                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     23512061                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data      9422833                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      9699313                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     19122146                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       248824                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       262151                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       510975                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       223538                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       242426                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       465964                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       220738                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       239447                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       460185                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     20980371                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     21653836                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     42634207                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     21229195                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     21915987                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     43145182                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017114                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.017072                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.017093                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016065                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015217                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015635                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235130                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.228017                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231481                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048309                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049405                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048879                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000008                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016643                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016241                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.016439                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019204                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018775                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.018986                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16205.250518                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16197.365907                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16201.246383                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 66879.506811                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60734.344194                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63845.823620                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12740.253727                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13137.931034                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12949.376537                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38174.853654                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 34888.612130                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 36525.829621                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32696.368212                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29820.218002                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 31251.644707                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       685305                       # number of writebacks
system.cpu0.dcache.writebacks::total           685305                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          467                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          450                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total          917                       # number of ReadReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         6966                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7290                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14256                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data          467                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data          450                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total          917                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data          467                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data          450                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total          917                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       197323                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       203643                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       400966                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151382                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       147597                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       298979                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57401                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58845                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       116246                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3833                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4687                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8520                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data       348705                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       351240                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       699945                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data       406106                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       410085                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       816191                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15125                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16013                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13276                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14313                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28401                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30326                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2991931500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3087967000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6079898500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9972971500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   8816610000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18789581500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    804001000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    810571000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1614572000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52152500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63092500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115245000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12964903000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  11904577000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  24869480000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13768904000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12715148000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  26484052000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2876770000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3059986500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5936756500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2305348000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2486099500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   4791447500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5182118000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5546086000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  10728204000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017073                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.017035                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017054                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.016065                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015217                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015635                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230689                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.224470                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227498                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017147                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019334                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018285                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000008                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016621                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016221                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016417                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019130                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018712                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018917                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37180.146542                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 33892.999089                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35530.620263                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33904.704683                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31006.127998                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32448.350937                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190199.669421                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191093.892462                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.531762                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173647.785478                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173695.207154                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173672.387546                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182462.518925                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182882.213282                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182679.244640                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1696133                       # number of replacements
system.cpu0.icache.tags.tagsinuse          510.440350                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          113853580                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1696645                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            67.105128                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      28968175500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   264.675620                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   245.764730                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.516945                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.480009                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.996954                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        117246882                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       117246882                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     55981187                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     57872393                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      113853580                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     55981187                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     57872393                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       113853580                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     55981187                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     57872393                       # number of overall hits
system.cpu0.icache.overall_hits::total      113853580                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       842259                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       854392                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1696651                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       842259                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       854392                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1696651                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       842259                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       854392                       # number of overall misses
system.cpu0.icache.overall_misses::total      1696651                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11932408500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12314837000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  24247245500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  11932408500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  12314837000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  24247245500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  11932408500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  12314837000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  24247245500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     56823446                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     58726785                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    115550231                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     56823446                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     58726785                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    115550231                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     56823446                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     58726785                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    115550231                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014822                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014549                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.014683                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014822                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014549                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.014683                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014822                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014549                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.014683                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14167.148704                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14413.567777                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14291.239330                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14167.148704                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14413.567777                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14291.239330                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14167.148704                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14413.567777                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14291.239330                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       842259                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       854392                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      1696651                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst       842259                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       854392                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      1696651                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst       842259                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       854392                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      1696651                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11090149500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11460445000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  22550594500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11090149500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11460445000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  22550594500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11090149500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11460445000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  22550594500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1142893000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1142893000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014822                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014549                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014683                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014822                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014549                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.014683                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014822                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014549                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.014683                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     6703                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                6703                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2138                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4565                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         6703                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           6703    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         6703                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         5647                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  7443.565061                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767         5646     99.98%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         5647                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1639416500                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1639416500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1639416500                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         3534     62.58%     62.58% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M         2113     37.42%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         5647                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6703                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6703                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5647                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5647                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        12350                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12475099                       # DTB read hits
system.cpu1.dtb.read_misses                      5811                       # DTB read misses
system.cpu1.dtb.write_hits                    9951122                       # DTB write hits
system.cpu1.dtb.write_misses                      892                       # DTB write misses
system.cpu1.dtb.flush_tlb                        2942                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     436                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    4467                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   929                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      214                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12480910                       # DTB read accesses
system.cpu1.dtb.write_accesses                9952014                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         22426221                       # DTB hits
system.cpu1.dtb.misses                           6703                       # DTB misses
system.cpu1.dtb.accesses                     22432924                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     3400                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                3400                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          811                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2589                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples         3400                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           3400    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         3400                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples         2613                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  7032.742162                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-16383         1945     74.44%     74.44% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-32767          667     25.53%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total         2613                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1638889000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1638889000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1638889000                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K         1802     68.96%     68.96% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          811     31.04%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         2613                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3400                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3400                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2613                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2613                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         6013                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    58726785                       # ITB inst hits
system.cpu1.itb.inst_misses                      3400                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        2942                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     436                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    2616                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                58730185                       # ITB inst accesses
system.cpu1.itb.hits                         58726785                       # DTB hits
system.cpu1.itb.misses                           3400                       # DTB misses
system.cpu1.itb.accesses                     58730185                       # DTB accesses
system.cpu1.numCycles                      2908727473                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   57164215                       # Number of instructions committed
system.cpu1.committedOps                     68869811                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             60957593                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  5807                       # Number of float alu accesses
system.cpu1.num_func_calls                    5082908                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      7664467                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    60957593                       # number of integer instructions
system.cpu1.num_fp_insts                         5807                       # number of float instructions
system.cpu1.num_int_register_reads          110918664                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          42060766                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                4325                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes               1484                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           248948036                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           26157973                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     23089661                       # number of memory refs
system.cpu1.num_load_insts                   12644031                       # Number of load instructions
system.cpu1.num_store_insts                  10445630                       # Number of store instructions
system.cpu1.num_idle_cycles              2688977301.144567                       # Number of idle cycles
system.cpu1.num_busy_cycles              219750171.855433                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.075549                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.924451                       # Percentage of idle cycles
system.cpu1.Branches                         13165858                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                 2218      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 47327866     67.15%     67.15% # Class of executed instruction
system.cpu1.op_class::IntMult                   56561      0.08%     67.23% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              4450      0.01%     67.24% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.24% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.24% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.24% # Class of executed instruction
system.cpu1.op_class::MemRead                12644031     17.94%     85.18% # Class of executed instruction
system.cpu1.op_class::MemWrite               10445630     14.82%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  70480756                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          449                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             38469000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                85000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                74000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy               506000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               40000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer21.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             5287000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              143000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            30680000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              102000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           186329023                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36418                       # number of replacements
system.iocache.tags.tagsinuse                1.084103                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         313630728000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     1.084103                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.067756                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.067756                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328068                       # Number of tag accesses
system.iocache.tags.data_accesses              328068                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          228                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              228                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          228                       # number of demand (read+write) misses
system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          228                       # number of overall misses
system.iocache.overall_misses::total              228                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     28361877                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     28361877                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   4696967146                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   4696967146                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     28361877                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     28361877                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     28361877                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     28361877                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          228                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             228                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          228                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            228                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124394.197368                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124394.197368                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124394.197368                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124394.197368                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124394.197368                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          228                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          228                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     16961877                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     16961877                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2885767146                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2885767146                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     16961877                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     16961877                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     16961877                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     16961877                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74394.197368                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74394.197368                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79664.508227                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79664.508227                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74394.197368                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74394.197368                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74394.197368                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74394.197368                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    87592                       # number of replacements
system.l2c.tags.tagsinuse                64865.832577                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4555575                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   152761                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.821584                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   50194.873681                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.905171                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4138.424328                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2240.226521                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.840428                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000599                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     5521.257429                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2766.304421                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.765913                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000029                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063147                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.034183                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000043                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.084248                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.042210                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.989774                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65165                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2128                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         6804                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56179                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994339                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 40610992                       # Number of tag accesses
system.l2c.tags.data_accesses                40610992                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         6164                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3132                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6231                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         3376                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  18903                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          685305                       # number of Writeback hits
system.l2c.Writeback_hits::total               685305                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              10                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data              14                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  24                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            80673                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            86743                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               167416                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        834184                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        844481                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1678665                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       252476                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       260979                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           513455                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6164                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3132                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              834184                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              333149                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6231                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          3376                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              844481                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              347722                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2378439                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6164                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3132                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             834184                       # number of overall hits
system.l2c.overall_hits::cpu0.data             333149                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6231                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         3376                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             844481                       # number of overall hits
system.l2c.overall_hits::cpu1.data             347722                       # number of overall hits
system.l2c.overall_hits::total                2378439                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            3                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                    8                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1406                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1339                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2745                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          69293                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          59501                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             128794                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         8056                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         9898                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           17954                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         6081                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         6196                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          12277                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8056                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             75374                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            3                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9898                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             65697                       # number of demand (read+write) misses
system.l2c.demand_misses::total                159033                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8056                       # number of overall misses
system.l2c.overall_misses::cpu0.data            75374                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            3                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9898                       # number of overall misses
system.l2c.overall_misses::cpu1.data            65697                       # number of overall misses
system.l2c.overall_misses::total               159033                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       531000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       412000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker       133000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        1076000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data       807500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      1049000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total      1856500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data       159000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   8785071500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   7576077500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  16361149000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1050880500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   1294053500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   2344934000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data    804079500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    815434500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1619514000                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker       531000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   1050880500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   9589151000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker       412000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker       133000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   1294053500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   8391512000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     20326673000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker       531000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   1050880500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   9589151000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker       412000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker       133000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   1294053500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   8391512000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    20326673000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         6168                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         3132                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         6234                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         3377                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              18911                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       685305                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           685305                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1416                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         1353                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2769                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       149966                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       146244                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296210                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       842240                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       854379                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1696619                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       258557                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       267175                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       525732                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6168                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         3132                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          842240                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          408523                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         6234                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         3377                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          854379                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          413419                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2537472                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6168                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         3132                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         842240                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         408523                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         6234                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         3377                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         854379                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         413419                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2537472                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000649                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000481                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000296                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.000423                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992938                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.989653                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991333                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.462058                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.406861                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.434806                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.009565                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011585                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010582                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.023519                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.023191                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.023352                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000649                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.009565                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.184504                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000481                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.000296                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.011585                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.158911                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.062674                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000649                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.009565                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.184504                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000481                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.000296                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.011585                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.158911                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.062674                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       132750                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137333.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total       134500                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   574.324324                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   783.420463                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   676.320583                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126781.514727                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127326.893666                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 127033.472056                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130446.933962                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130738.886644                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 130607.886822                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132228.169709                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131606.601033                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 131914.474220                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       132750                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 130446.933962                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 127220.938255                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 130738.886644                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 127730.520420                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 127814.183220                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       132750                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 130446.933962                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 127220.938255                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 130738.886644                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 127730.520420                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 127814.183220                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               81267                       # number of writebacks
system.l2c.writebacks::total                    81267                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total               8                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1406                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1339                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2745                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        69293                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        59501                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        128794                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst         8056                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         9898                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        17954                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data         6081                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         6196                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        12277                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8056                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data        75374                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            3                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9898                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        65697                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           159033                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker            4                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8056                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data        75374                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            3                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9898                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        65697                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          159033                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15125                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16013                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        13276                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14313                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        28401                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        30326                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       491000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       382000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       123000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total       996000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     99569000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     94780500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    194349500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   8092141500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   6981067500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  15073209000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst    970320500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   1195073500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   2165394000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data    743269500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    753474500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1496744000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       491000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    970320500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   8835411000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       382000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       123000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   1195073500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   7734542000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  18736343000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       491000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    970320500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   8835411000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       382000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       123000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   1195073500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   7734542000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  18736343000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2687706500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2859824000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6577648500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2152674000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2321500000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   4474174000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4840380500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5181324000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  11051822500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000649                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000481                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000296                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.000423                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.992938                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.989653                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.991333                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.462058                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.406861                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.434806                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009565                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011585                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010582                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.023519                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.023191                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023352                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000649                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009565                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.184504                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000481                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000296                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011585                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.158911                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.062674                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000649                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009565                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.184504                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000481                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000296                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011585                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.158911                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.062674                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker       122750                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total       124500                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70817.211949                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70784.540702                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70801.275046                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116781.514727                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117326.893666                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117033.472056                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120446.933962                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120738.886644                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120607.886822                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122228.169709                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121606.601033                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 121914.474220                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       122750                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120446.933962                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117220.938255                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120738.886644                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117730.520420                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 117814.183220                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       122750                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 117814.183220                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
system.membus.trans_dist::ReadResp              70627                       # Transaction distribution
system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
system.membus.trans_dist::Writeback            117457                       # Transaction distribution
system.membus.trans_dist::CleanEvict             6338                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4503                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4505                       # Transaction distribution
system.membus.trans_dist::ReadExReq            127036                       # Transaction distribution
system.membus.trans_dist::ReadExResp           127036                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         30467                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438779                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       546371                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 655265                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15304828                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     15468181                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                17785301                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              492                       # Total snoops (count)
system.membus.snoop_fanout::samples            389991                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  389991    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              389991                       # Request fanout histogram
system.membus.reqLayer0.occupancy            90490000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1693000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           821977659                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          952225245                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           64492032                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests      5059453                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      2540884                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests        38074                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops            582                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops          582                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              75104                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2297700                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           802762                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1800707                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2769                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2771                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296210                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296210                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1696651                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       525960                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5076713                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2581153                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18522                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        35333                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               7711721                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    108619704                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96660573                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26036                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        49608                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              205355921                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          176740                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          5302052                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.018353                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.134225                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5204742     98.16%     98.16% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                  97310      1.84%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            5302052                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         3269894500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           380377                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        2553998500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        1279231000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          12013000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          22931000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------