path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.398431                       # Number of seconds simulated
sim_ticks                                47398431268500                       # Number of ticks simulated
final_tick                               47398431268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 671569                       # Simulator instruction rate (inst/s)
host_op_rate                                   790318                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            37657329129                       # Simulator tick rate (ticks/s)
host_mem_usage                                 861000                       # Number of bytes of host memory used
host_seconds                                  1258.68                       # Real time elapsed on the host
sim_insts                                   845288376                       # Number of instructions simulated
sim_ops                                     994755388                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        36416                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        41984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           768052                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          7936536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     44723840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        83456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        97984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           589368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          8667104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     21031552                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        441920                       # Number of bytes read from this memory
system.physmem.bytes_read::total             84418212                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       768052                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       589368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1357420                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     65101248                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20812                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          65122064                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker          569                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker          656                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             52408                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            124030                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       698810                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1304                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1531                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              9297                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            135438                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       328618                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6905                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1359566                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1017207                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2602                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1019810                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker           886                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               16204                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              167443                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       943572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1761                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2067                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               12434                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              182856                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       443718                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9324                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1781034                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          16204                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          12434                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              28639                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1373490                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                439                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1373929                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1373490                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          768                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker          886                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              16204                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             167882                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       943572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1761                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2067                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              12434                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             182856                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       443718                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9324                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3154963                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1359566                       # Number of read requests accepted
system.physmem.writeReqs                      1139623                       # Number of write requests accepted
system.physmem.readBursts                     1359566                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1139623                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 86962304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     49920                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  72439488                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  84418212                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               72790096                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      780                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    7732                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          85004                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               81504                       # Per bank write bursts
system.physmem.perBankRdBursts::1               94599                       # Per bank write bursts
system.physmem.perBankRdBursts::2               79086                       # Per bank write bursts
system.physmem.perBankRdBursts::3               89082                       # Per bank write bursts
system.physmem.perBankRdBursts::4               90127                       # Per bank write bursts
system.physmem.perBankRdBursts::5               94039                       # Per bank write bursts
system.physmem.perBankRdBursts::6               78740                       # Per bank write bursts
system.physmem.perBankRdBursts::7               79772                       # Per bank write bursts
system.physmem.perBankRdBursts::8               80197                       # Per bank write bursts
system.physmem.perBankRdBursts::9              124149                       # Per bank write bursts
system.physmem.perBankRdBursts::10              71869                       # Per bank write bursts
system.physmem.perBankRdBursts::11              83577                       # Per bank write bursts
system.physmem.perBankRdBursts::12              73174                       # Per bank write bursts
system.physmem.perBankRdBursts::13              83519                       # Per bank write bursts
system.physmem.perBankRdBursts::14              78794                       # Per bank write bursts
system.physmem.perBankRdBursts::15              76558                       # Per bank write bursts
system.physmem.perBankWrBursts::0               70549                       # Per bank write bursts
system.physmem.perBankWrBursts::1               76959                       # Per bank write bursts
system.physmem.perBankWrBursts::2               69527                       # Per bank write bursts
system.physmem.perBankWrBursts::3               76268                       # Per bank write bursts
system.physmem.perBankWrBursts::4               71760                       # Per bank write bursts
system.physmem.perBankWrBursts::5               76111                       # Per bank write bursts
system.physmem.perBankWrBursts::6               67646                       # Per bank write bursts
system.physmem.perBankWrBursts::7               68141                       # Per bank write bursts
system.physmem.perBankWrBursts::8               69345                       # Per bank write bursts
system.physmem.perBankWrBursts::9               72887                       # Per bank write bursts
system.physmem.perBankWrBursts::10              65485                       # Per bank write bursts
system.physmem.perBankWrBursts::11              73987                       # Per bank write bursts
system.physmem.perBankWrBursts::12              65828                       # Per bank write bursts
system.physmem.perBankWrBursts::13              73935                       # Per bank write bursts
system.physmem.perBankWrBursts::14              66021                       # Per bank write bursts
system.physmem.perBankWrBursts::15              67418                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
system.physmem.totGap                    47398428076000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1316329                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1137020                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    566894                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    282234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    134057                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    101972                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     67644                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     58693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     53670                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     46721                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     35916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      3762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1955                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      882                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      709                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      471                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      229                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      184                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       75                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    16911                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    22466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    30737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    39170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    44059                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    50283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    58139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    68202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    72051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    76579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    76851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    78478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    78341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    80363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    74556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    75992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    78312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    75395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                    11828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     7611                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     4129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1848                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      916                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      712                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      505                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      356                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      286                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       648906                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      245.646870                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     142.183985                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     295.195613                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         325424     50.15%     50.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       135792     20.93%     71.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        50411      7.77%     78.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        26706      4.12%     82.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        22287      3.43%     86.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        16108      2.48%     88.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10950      1.69%     90.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        13619      2.10%     92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        47609      7.34%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         648906                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         58676                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.156827                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      139.787244                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          58673     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           58676                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         58676                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.290119                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.850822                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.308232                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           54948     93.65%     93.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             970      1.65%     95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             598      1.02%     96.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             219      0.37%     96.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             626      1.07%     97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             147      0.25%     98.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             195      0.33%     98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             132      0.22%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             184      0.31%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              81      0.14%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            205      0.35%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            24      0.04%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            63      0.11%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            38      0.06%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135           129      0.22%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            15      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            27      0.05%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159            11      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            19      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             8      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            11      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             6      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             3      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           58676                       # Writes before turning the bus around for reads
system.physmem.totQLat                    69966976258                       # Total ticks spent queuing
system.physmem.totMemAccLat               95444213758                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6793930000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       51492.27                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  70242.27                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.83                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.78                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.54                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.73                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.44                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1114788                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    726958                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  64.23                       # Row buffer hit rate for writes
system.physmem.avgGap                     18965523.65                       # Average gap between requests
system.physmem.pageHitRate                      73.95                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     45538400789750                       # Time in different power states
system.physmem.memoryStateTime::REF      1582737780000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      277292625250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                2564850960                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                2340878400                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1399472250                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1277265000                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               5358202200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               5240320800                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              3738707280                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              3595790880                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3095835097680                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3095835097680                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1171174509540                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1161726671475                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          27411712647750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          27420000225000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            31691783487660                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            31690016249235                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.625157                       # Core power per rank (mW)
system.physmem.averagePower::1             668.587872                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1670                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6842880                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1673                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    74706058                       # DTB read hits
system.cpu0.dtb.read_misses                     64792                       # DTB read misses
system.cpu0.dtb.write_hits                   67192400                       # DTB write hits
system.cpu0.dtb.write_misses                    21129                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   33482                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3817                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     8375                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                74770850                       # DTB read accesses
system.cpu0.dtb.write_accesses               67213529                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        141898458                       # DTB hits
system.cpu0.dtb.misses                          85921                       # DTB misses
system.cpu0.dtb.accesses                    141984379                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   397874920                       # ITB inst hits
system.cpu0.itb.inst_misses                     49120                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   23760                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               397924040                       # ITB inst accesses
system.cpu0.itb.hits                        397874920                       # DTB hits
system.cpu0.itb.misses                          49120                       # DTB misses
system.cpu0.itb.accesses                    397924040                       # DTB accesses
system.cpu0.numCycles                     94796862537                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  397643174                       # Number of instructions committed
system.cpu0.committedOps                    466635553                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            429030148                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                322477                       # Number of float alu accesses
system.cpu0.num_func_calls                   23930039                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     59901605                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   429030148                       # number of integer instructions
system.cpu0.num_fp_insts                       322477                       # number of float instructions
system.cpu0.num_int_register_reads          621630892                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         340702516                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              547437                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             211832                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           102593685                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          102325899                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    141893093                       # number of memory refs
system.cpu0.num_load_insts                   74704433                       # Number of load instructions
system.cpu0.num_store_insts                  67188660                       # Number of store instructions
system.cpu0.num_idle_cycles              93886429062.298019                       # Number of idle cycles
system.cpu0.num_busy_cycles              910433474.701981                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.009604                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.990396                       # Percentage of idle cycles
system.cpu0.Branches                         88352328                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                323823287     69.35%     69.35% # Class of executed instruction
system.cpu0.op_class::IntMult                 1114929      0.24%     69.59% # Class of executed instruction
system.cpu0.op_class::IntDiv                    56737      0.01%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             22377      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::MemRead                74704433     16.00%     85.61% # Class of executed instruction
system.cpu0.op_class::MemWrite               67188660     14.39%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 466910423                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5105                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          4859280                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          480.680410                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          136835586                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          4859789                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.156693                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3644536500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.680410                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938829                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.938829                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          406                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2            9                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        288671468                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       288671468                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     69599952                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       69599952                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     63413457                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      63413457                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       173858                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       173858                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       133135                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       133135                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1596886                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1596886                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1561841                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1561841                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    133013409                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       133013409                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    133187267                       # number of overall hits
system.cpu0.dcache.overall_hits::total      133187267                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2622769                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      2622769                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1185607                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1185607                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       553155                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       553155                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       697992                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total       697992                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       145021                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       145021                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       178721                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       178721                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3808376                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       3808376                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4361531                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4361531                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36725560788                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  36725560788                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  18496940456                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  18496940456                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  11951080104                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  11951080104                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2007745317                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2007745317                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3807661334                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   3807661334                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       927000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total       927000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  55222501244                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  55222501244                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  55222501244                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  55222501244                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     72222721                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     72222721                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     64599064                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     64599064                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       727013                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       727013                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       831127                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total       831127                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1741907                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1741907                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1740562                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1740562                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    136821785                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    136821785                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    137548798                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    137548798                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036315                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036315                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018353                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018353                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.760860                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760860                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.839814                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.839814                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.083254                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.083254                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.102680                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.102680                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027835                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027835                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031709                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.031709                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3276433                       # number of writebacks
system.cpu0.dcache.writebacks::total          3276433                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        20828                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        20828                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21424                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21424                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        36174                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        36174                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        42252                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        42252                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        42252                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        42252                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2601941                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2601941                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1164183                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1164183                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       551435                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       551435                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       697992                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total       697992                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       108847                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       108847                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       178721                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       178721                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3766124                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      3766124                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4317559                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4317559                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  30561578872                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  30561578872                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  15647124797                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  15647124797                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  11524265112                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  11524265112                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  10542114896                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  10542114896                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1234908207                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1234908207                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3440508666                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3440508666                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       879000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       879000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  46208703669                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  46208703669                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  57732968781                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  57732968781                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2384094697                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2384094697                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2386757695                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2386757695                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4770852392                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4770852392                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036027                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036027                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018022                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018022                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.758494                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.758494                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.839814                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.839814                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062487                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.062487                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.102680                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.102680                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027526                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027526                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031389                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031389                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          4269396                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.932974                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          393605012                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          4269908                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            92.181146                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      18918806750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.932974                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999869                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          222                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        800019748                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       800019748                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    393605012                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      393605012                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    393605012                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       393605012                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    393605012                       # number of overall hits
system.cpu0.icache.overall_hits::total      393605012                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      4269908                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      4269908                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      4269908                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       4269908                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      4269908                       # number of overall misses
system.cpu0.icache.overall_misses::total      4269908                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  37643365597                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  37643365597                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  37643365597                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  37643365597                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  37643365597                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  37643365597                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    397874920                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    397874920                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    397874920                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    397874920                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    397874920                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    397874920                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010732                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.010732                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010732                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.010732                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010732                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.010732                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8815.966432                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8815.966432                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8815.966432                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8815.966432                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8815.966432                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8815.966432                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4269908                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      4269908                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      4269908                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      4269908                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      4269908                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      4269908                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  31235618425                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  31235618425                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  31235618425                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  31235618425                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  31235618425                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  31235618425                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3405609750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3405609750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010732                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.010732                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010732                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.010732                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010732                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.010732                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7315.290733                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7315.290733                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7315.290733                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7315.290733                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7315.290733                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7315.290733                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     45505774                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr      2657797                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     39900232                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8744                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          580                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      2938421                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3808538                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements         3291824                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16191.272385                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           9909292                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         3307923                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            2.995624                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     16044231500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  5217.724609                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    49.949148                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    58.574202                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   727.292976                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2667.900561                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  7469.830889                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.318465                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003049                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003575                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.044390                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.162836                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.455922                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.988237                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8632                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023          100                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7367                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           22                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          210                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         1111                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         7012                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          277                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            6                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           77                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1042                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         1532                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4604                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          127                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.526855                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006104                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.449646                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       215960486                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      215960486                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       166834                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       106498                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4104943                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2390641                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       6768916                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3276433                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3276433                       # number of Writeback hits
system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data       610572                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.WriteInvalidateReq_hits::total       610572                       # number of WriteInvalidateReq hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        75583                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        75583                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        31346                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        31346                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       814537                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       814537                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       166834                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       106498                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4104943                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3205178                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        7583453                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       166834                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       106498                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4104943                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3205178                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       7583453                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         9451                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7593                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       164965                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       871580                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1053589                       # number of ReadReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data        86357                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.WriteInvalidateReq_misses::total        86357                       # number of WriteInvalidateReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       106896                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       106896                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       147374                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       147374                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       172967                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       172967                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         9451                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7593                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       164965                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1044547                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1226556                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         9451                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7593                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       164965                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1044547                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1226556                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    247144715                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    215825476                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   4449371565                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  25701723776                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  30614065532                       # number of ReadReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data   5651418353                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total   5651418353                       # number of WriteInvalidateReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2080242902                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2080242902                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2994303005                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2994303005                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       855000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       855000                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   6538293027                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total   6538293027                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    247144715                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    215825476                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4449371565                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  32240016803                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  37152358559                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    247144715                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    215825476                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4449371565                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  32240016803                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  37152358559                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       176285                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       114091                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      4269908                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3262221                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      7822505                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3276433                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3276433                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data       696929                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.WriteInvalidateReq_accesses::total       696929                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       182479                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       182479                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       178720                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       178720                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       987504                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       987504                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       176285                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       114091                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      4269908                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4249725                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      8810009                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       176285                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       114091                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      4269908                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4249725                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      8810009                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.053612                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.066552                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.038634                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.267174                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.134687                       # miss rate for ReadReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data     0.123911                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total     0.123911                       # miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.585799                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.585799                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.824608                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.824608                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.175156                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.175156                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.053612                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.066552                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.038634                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.245792                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.139223                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.053612                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.066552                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.038634                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.245792                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.139223                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26150.112686                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 28424.269195                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26971.609523                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29488.657124                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29056.933522                       # average ReadReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 65442.504406                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 65442.504406                       # average WriteInvalidateReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19460.437266                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19460.437266                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20317.715506                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20317.715506                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       855000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       855000                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37800.811872                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37800.811872                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26150.112686                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 28424.269195                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26971.609523                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 30865.070507                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 30289.981508                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26150.112686                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 28424.269195                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26971.609523                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 30865.070507                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 30289.981508                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs        52335                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs             662                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    79.055891                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1358617                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1358617                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst        24755                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         5238                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total        29993                       # number of ReadReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data        37532                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total        37532                       # number of WriteInvalidateReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         2960                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         2960                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        24755                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data         8198                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        32953                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        24755                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data         8198                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        32953                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker         9451                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         7593                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       140210                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       866342                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1023596                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      2938301                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total      2938301                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data        48825                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total        48825                       # number of WriteInvalidateReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       106896                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       106896                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       147374                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       147374                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       170007                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       170007                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker         9451                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         7593                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       140210                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1036349                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1193603                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker         9451                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         7593                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       140210                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1036349                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher      2938301                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      4131904                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    180794801                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    162470030                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   3053904483                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  19401824260                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  22798993574                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 128557799780                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 128557799780                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data    892232564                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total    892232564                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1781047970                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1781047970                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2043441791                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2043441791                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       687000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       687000                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   5046326892                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   5046326892                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    180794801                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    162470030                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3053904483                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  24448151152                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  27845320466                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    180794801                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    162470030                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3053904483                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  24448151152                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 128557799780                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 156403120246                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2268534801                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5330399551                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2268405055                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2268405055                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4536939856                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7598804606                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.053612                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.066552                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.032837                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.265568                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.130853                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.070057                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.070057                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.585799                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.585799                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.824608                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.824608                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.172158                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.172158                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.053612                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.066552                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.032837                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.243863                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.135483                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.053612                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.066552                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.032837                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.243863                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.469001                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21780.932052                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22395.109853                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22273.429726                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43752.426923                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 18274.092453                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 18274.092453                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16661.502488                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16661.502488                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13865.687238                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13865.687238                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       687000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       687000                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 29683.053592                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 29683.053592                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21780.932052                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 23590.654453                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      11465749                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      8074092                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        15773                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        15773                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      3276433                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      4228803                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq       811507                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       696929                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       407420                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       328722                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       423022                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           30                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           53                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1108208                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       995011                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      8626066                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     14109371                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       260774                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       426575                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         23422786                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    273446612                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    532438419                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       912728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1410280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         808208039                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    8581549                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     21569506                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.385644                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.486747                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5          13251364     61.44%     61.44% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6           8318142     38.56%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      21569506                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   10644176370                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    173370992                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   6459583336                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   6973558574                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    146771777                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    250366041                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    84980512                       # DTB read hits
system.cpu1.dtb.read_misses                     74547                       # DTB read misses
system.cpu1.dtb.write_hits                   77969612                       # DTB write hits
system.cpu1.dtb.write_misses                    26781                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   37319                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4156                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10210                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                85055059                       # DTB read accesses
system.cpu1.dtb.write_accesses               77996393                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        162950124                       # DTB hits
system.cpu1.dtb.misses                         101328                       # DTB misses
system.cpu1.dtb.accesses                    163051452                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                   447940407                       # ITB inst hits
system.cpu1.itb.inst_misses                     68561                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              37660                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1002                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   26339                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               448008968                       # ITB inst accesses
system.cpu1.itb.hits                        447940407                       # DTB hits
system.cpu1.itb.misses                          68561                       # DTB misses
system.cpu1.itb.accesses                    448008968                       # DTB accesses
system.cpu1.numCycles                     94796862537                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  447645202                       # Number of instructions committed
system.cpu1.committedOps                    528119835                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            486291398                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                624474                       # Number of float alu accesses
system.cpu1.num_func_calls                   27450761                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     67545606                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   486291398                       # number of integer instructions
system.cpu1.num_fp_insts                       624474                       # number of float instructions
system.cpu1.num_int_register_reads          698728829                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         384530758                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              985803                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             576512                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           114161169                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          113813296                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    162934099                       # number of memory refs
system.cpu1.num_load_insts                   84972579                       # Number of load instructions
system.cpu1.num_store_insts                  77961520                       # Number of store instructions
system.cpu1.num_idle_cycles              93770083152.566025                       # Number of idle cycles
system.cpu1.num_busy_cycles              1026779384.433978                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.010831                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.989169                       # Percentage of idle cycles
system.cpu1.Branches                        100081816                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                364276895     68.94%     68.94% # Class of executed instruction
system.cpu1.op_class::IntMult                 1051011      0.20%     69.14% # Class of executed instruction
system.cpu1.op_class::IntDiv                    60606      0.01%     69.15% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.15% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             92495      0.02%     69.17% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.17% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.17% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.17% # Class of executed instruction
system.cpu1.op_class::MemRead                84972579     16.08%     85.25% # Class of executed instruction
system.cpu1.op_class::MemWrite               77961520     14.75%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 528415149                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13701                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5194711                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          457.134068                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          157559099                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5195223                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            30.327687                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8367548601000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   457.134068                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.892840                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.892840                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        331059949                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       331059949                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     79405575                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       79405575                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     74066119                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      74066119                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       191889                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       191889                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       197632                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total       197632                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1669680                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1669680                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1654141                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1654141                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    153471694                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       153471694                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    153663583                       # number of overall hits
system.cpu1.dcache.overall_hits::total      153663583                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2946837                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2946837                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1283113                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1283113                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       571898                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       571898                       # number of SoftPFReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data       550709                       # number of WriteInvalidateReq misses
system.cpu1.dcache.WriteInvalidateReq_misses::total       550709                       # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       171203                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       171203                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       185528                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       185528                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4229950                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4229950                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      4801848                       # number of overall misses
system.cpu1.dcache.overall_misses::total      4801848                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  41215882509                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  41215882509                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  19312866378                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  19312866378                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data   6595698094                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.WriteInvalidateReq_miss_latency::total   6595698094                       # number of WriteInvalidateReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2383654561                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2383654561                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   3901847697                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   3901847697                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1095500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1095500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  60528748887                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  60528748887                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  60528748887                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  60528748887                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     82352412                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     82352412                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     75349232                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     75349232                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       763787                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       763787                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       748341                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       748341                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1840883                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1840883                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1839669                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1839669                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    157701644                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    157701644                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    158465431                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    158465431                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035783                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.035783                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017029                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.017029                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.748766                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.748766                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.735906                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_miss_rate::total     0.735906                       # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.093000                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.093000                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.100849                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.100849                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026822                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.026822                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.030302                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.030302                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13986.481950                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13986.481950                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15051.570967                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 15051.570967                       # average WriteReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 11976.739247                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 11976.739247                       # average WriteInvalidateReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13922.971916                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13922.971916                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14309.566044                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14309.566044                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12605.302976                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 12605.302976                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3397427                       # number of writebacks
system.cpu1.dcache.writebacks::total          3397427                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        14736                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        14736                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          407                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          407                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        48814                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        48814                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        15143                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        15143                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        15143                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        15143                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2932101                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2932101                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1282706                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1282706                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       571898                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       571898                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       550709                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total       550709                       # number of WriteInvalidateReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       122389                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       122389                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       185528                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       185528                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4214807                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4214807                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4786705                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4786705                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  34665979416                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  34665979416                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  16693598628                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  16693598628                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11612454284                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  11612454284                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   5490664906                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total   5490664906                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1373965707                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1373965707                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3521472303                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3521472303                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1037500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1037500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  51359578044                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  51359578044                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  62972032328                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  62972032328                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3972621225                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3972621225                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3807943973                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3807943973                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7780565198                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7780565198                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035604                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035604                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017023                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017023                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.748766                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.748766                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.735906                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.735906                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066484                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066484                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.100849                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.100849                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026726                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.026726                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030207                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.030207                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data  9970.174640                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total  9970.174640                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          5786522                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.339295                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          442153368                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5787034                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            76.404142                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8367526246000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.339295                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969413                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969413                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          339                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        901667853                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       901667853                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    442153368                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      442153368                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    442153368                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       442153368                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    442153368                       # number of overall hits
system.cpu1.icache.overall_hits::total      442153368                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5787039                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5787039                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5787039                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5787039                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5787039                       # number of overall misses
system.cpu1.icache.overall_misses::total      5787039                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  50052191468                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  50052191468                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  50052191468                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  50052191468                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  50052191468                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  50052191468                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    447940407                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    447940407                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    447940407                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    447940407                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    447940407                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    447940407                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.012919                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.012919                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.012919                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.012919                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.012919                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.012919                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8649.015752                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8649.015752                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8649.015752                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8649.015752                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8649.015752                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8649.015752                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5787039                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5787039                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5787039                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5787039                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5787039                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5787039                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  41368714588                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  41368714588                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  41368714588                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  41368714588                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  41368714588                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  41368714588                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      9075250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      9075250                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      9075250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      9075250                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.012919                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.012919                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.012919                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.012919                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.012919                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.012919                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7148.511456                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7148.511456                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7148.511456                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7148.511456                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7148.511456                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7148.511456                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     55302288                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       976452                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     51578919                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         9282                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          584                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2737051                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4557576                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements         3265247                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13732.593717                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          11929802                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         3281353                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            3.635635                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    9719592338000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  3548.297662                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    58.425503                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    65.675774                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   758.406628                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2477.157386                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6824.630764                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.216571                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003566                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004009                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.046289                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.151194                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.416542                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.838171                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8592                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           40                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         7474                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           93                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          541                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         2721                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4842                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          395                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           15                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          810                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         3409                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2963                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          229                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.524414                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002441                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.456177                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       249010603                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      249010603                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       204488                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       158918                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      5602514                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2695724                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       8661644                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3397427                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3397427                       # number of Writeback hits
system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data       491178                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.WriteInvalidateReq_hits::total       491178                       # number of WriteInvalidateReq hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        77109                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        77109                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35497                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        35497                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       899510                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       899510                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       204488                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       158918                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      5602514                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3595234                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9561154                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       204488                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       158918                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      5602514                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3595234                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9561154                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        11072                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9747                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       184525                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data       930664                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1136008                       # number of ReadReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data        58187                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.WriteInvalidateReq_misses::total        58187                       # number of WriteInvalidateReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       111708                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       111708                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       150027                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       150027                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            4                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       196006                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       196006                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        11072                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9747                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       184525                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1126670                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1332014                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        11072                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9747                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       184525                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1126670                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1332014                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    339143470                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    328936960                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   4835548618                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  27845292450                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  33348921498                       # number of ReadReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data   1715319866                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total   1715319866                       # number of WriteInvalidateReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2196780170                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2196780170                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3055684059                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3055684059                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1008500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1008500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   6932150792                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total   6932150792                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    339143470                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    328936960                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   4835548618                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  34777443242                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  40281072290                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    339143470                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    328936960                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   4835548618                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  34777443242                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  40281072290                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       215560                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       168665                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      5787039                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3626388                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      9797652                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3397427                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3397427                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data       549365                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.WriteInvalidateReq_accesses::total       549365                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       188817                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       188817                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       185524                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       185524                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1095516                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1095516                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       215560                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       168665                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5787039                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4721904                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10893168                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       215560                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       168665                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5787039                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4721904                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10893168                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.051364                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.057789                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.031886                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.256637                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.115947                       # miss rate for ReadReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data     0.105917                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total     0.105917                       # miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.591620                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.591620                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.808666                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.808666                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.178917                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.178917                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.051364                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.057789                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.031886                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.238605                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.122280                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.051364                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.057789                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.031886                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.238605                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.122280                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30630.732478                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 33747.507951                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26205.384734                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 29919.812575                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29356.238247                       # average ReadReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 29479.434685                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 29479.434685                       # average WriteInvalidateReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19665.379113                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19665.379113                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20367.560899                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20367.560899                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       252125                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       252125                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 35367.033621                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35367.033621                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30630.732478                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 33747.507951                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26205.384734                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30867.461850                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 30240.727417                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30630.732478                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 33747.507951                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26205.384734                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30867.461850                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 30240.727417                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs        13039                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             326                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    39.996933                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1118692                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1118692                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        28597                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          597                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total        29194                       # number of ReadReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data         9933                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total         9933                       # number of WriteInvalidateReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         2789                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         2789                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        28597                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         3386                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        31983                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        28597                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         3386                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        31983                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        11072                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9747                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       155928                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       930067                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1106814                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      2736889                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total      2736889                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data        48254                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total        48254                       # number of WriteInvalidateReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       111708                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       111708                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       150027                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       150027                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       193217                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       193217                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        11072                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9747                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       155928                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1123284                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1300031                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        11072                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9747                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       155928                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1123284                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      2736889                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      4036920                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    261197050                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    260217544                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   3279178209                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  21257509518                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  25058102321                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  69697772473                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  69697772473                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data    739531321                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total    739531321                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   1851219395                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   1851219395                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2073994150                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2073994150                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       805500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       805500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   5288290642                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   5288290642                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    261197050                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    260217544                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   3279178209                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  26545800160                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  30346392963                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    261197050                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    260217544                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   3279178209                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  26545800160                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  69697772473                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 100044165436                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8211750                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3785003026                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3793214776                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3642241027                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3642241027                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8211750                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7427244053                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7435455803                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.051364                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.057789                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.026944                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.256472                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.112967                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.087836                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.087836                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.591620                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.591620                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.808666                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.808666                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.176371                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.176371                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.051364                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.057789                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.026944                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.237888                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.119344                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.051364                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.057789                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.026944                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.237888                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.370592                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       201375                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       201375                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      13482596                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10019474                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        22090                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        22090                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      3397427                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      3948207                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq       669175                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       549365                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       394300                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       332875                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       429984                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           28                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           53                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1203009                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1101184                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     11574298                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     14922836                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       373561                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       511408                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         27382103                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    370370936                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    560535931                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1349320                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1724480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         933980667                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    8332859                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     23404111                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.344949                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.475352                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5          15330876     65.51%     65.51% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6           8073235     34.49%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      23404111                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   11646725084                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    158989494                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8682146940                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7623277083                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    205120292                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    296049290                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40487                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40487                       # Transaction distribution
system.iobus.trans_dist::WriteReq              137083                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30163                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106920                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48390                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29756                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123480                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231580                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231580                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  355140                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48410                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17674                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156518                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7351088                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7351088                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7509692                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36789000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            22103000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1044839337                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93320000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179372271                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115786                       # number of replacements
system.iocache.tags.tagsinuse               11.223287                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115802                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9123835798000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.412555                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.810732                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463285                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.238171                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.701455                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1042467                       # Number of tag accesses
system.iocache.tags.data_accesses             1042467                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8870                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8907                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106920                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106920                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8870                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8910                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8870                       # number of overall misses
system.iocache.overall_misses::total             8910                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5627000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1958941092                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1964568092                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28897474974                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28897474974                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5984000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1958941092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1964925092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5984000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1958941092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1964925092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8870                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8907                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106920                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106920                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8870                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8910                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8870                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8910                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 220564.510161                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       149600                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 220850.179481                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 220530.313356                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       149600                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 220850.179481                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 220530.313356                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        225288                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27401                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.221890                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106886                       # number of writebacks
system.iocache.writebacks::total               106886                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8870                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8907                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106920                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106920                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8870                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8910                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8870                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8910                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3703000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1497575112                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1501278112                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23337113496                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23337113496                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3904000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1497575112                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1501479112                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3904000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1497575112                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1501479112                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        97600                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 168516.174186                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        97600                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 168516.174186                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1310456                       # number of replacements
system.l2c.tags.tagsinuse                64677.337118                       # Cycle average of tags in use
system.l2c.tags.total_refs                    7257968                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1373726                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     5.283418                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               5621833500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    9998.305247                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    56.991260                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    77.146603                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      791.679733                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4513.780403                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   150.211809                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   222.184258                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      784.998757                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     7219.989726                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.152562                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000870                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.001177                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.012080                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.068875                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.363444                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002292                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003390                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.011978                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.110168                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.260061                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.986898                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        38915                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          205                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        24150                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0           26                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1           26                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          487                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         8729                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        29647                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          188                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5282                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        18136                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.593796                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003128                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.368500                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 74054042                       # Number of tag accesses
system.l2c.tags.data_accesses                74054042                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5514                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4407                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             131001                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             549137                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1653135                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         7096                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         6374                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             146834                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             607953                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1853450                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                4964901                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         2477309                       # number of Writeback hits
system.l2c.Writeback_hits::total              2477309                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data         3452                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data         4029                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total         7481                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data           31717                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           34608                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               66325                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          7299                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          8593                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             15892                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            45918                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            59655                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               105573                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5514                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4407                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              131001                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              595055                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher      1653135                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          7096                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          6374                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              146834                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              667608                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher      1853450                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 5070474                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5514                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4407                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             131001                       # number of overall hits
system.l2c.overall_hits::cpu0.data             595055                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher      1653135                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         7096                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         6374                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             146834                       # number of overall hits
system.l2c.overall_hits::cpu1.data             667608                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher      1853450                       # number of overall hits
system.l2c.overall_hits::total                5070474                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker          569                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker          656                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             9314                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data            87213                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       698997                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         1304                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         1531                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             9213                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            99987                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       328949                       # number of ReadReq misses
system.l2c.ReadReq_misses::total              1237733                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data         9435                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data         3626                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total        13061                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         30881                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         31286                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             62167                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data         9976                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         9599                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           19575                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          38485                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          37338                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              75823                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker          569                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker          656                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              9314                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            125698                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       698997                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1304                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1531                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9213                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            137325                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       328949                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1313556                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker          569                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker          656                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             9314                       # number of overall misses
system.l2c.overall_misses::cpu0.data           125698                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       698997                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1304                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1531                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9213                       # number of overall misses
system.l2c.overall_misses::cpu1.data           137325                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       328949                       # number of overall misses
system.l2c.overall_misses::total              1313556                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker     46419250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker     56195000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    845205741                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data   7070866945                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 100071825385                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    105377999                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    124997499                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    812177995                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   7981910698                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  38448513875                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total   155563490387                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data      1840421                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu1.data      2071411                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total      3911832                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    134255920                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    141850516                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    276106436                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     49268414                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     49362431                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     98630845                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   2848027798                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   2731267565                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   5579295363                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker     46419250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker     56195000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    845205741                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data   9918894743                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 100071825385                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    105377999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    124997499                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    812177995                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  10713178263                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  38448513875                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    161142785750                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker     46419250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker     56195000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    845205741                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data   9918894743                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 100071825385                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    105377999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    124997499                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    812177995                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  10713178263                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  38448513875                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   161142785750                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         6083                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         5063                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         140315                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         636350                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2352132                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         8400                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker         7905                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         156047                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         707940                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2182399                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            6202634                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      2477309                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          2477309                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data        12887                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data         7655                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total        20542                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        62598                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        65894                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          128492                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        17275                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        18192                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         35467                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data        84403                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        96993                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           181396                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         6083                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         5063                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          140315                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          720753                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2352132                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         8400                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7905                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          156047                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          804933                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2182399                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             6384030                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         6083                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         5063                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         140315                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         720753                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2352132                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         8400                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7905                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         156047                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         804933                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2182399                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            6384030                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.093539                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.129567                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.066379                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.137052                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.297176                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.155238                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.193675                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.059040                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.141237                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.150728                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.199550                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.732133                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.473677                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.635819                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.493322                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.474793                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.483820                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.577482                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.527650                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.551922                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.455967                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.384956                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.417997                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.093539                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.129567                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.066379                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.174398                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.297176                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.155238                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.193675                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.059040                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.170604                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.150728                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.205757                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.093539                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.129567                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.066379                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.174398                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.297176                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.155238                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.193675                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.059040                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.170604                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.150728                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.205757                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81580.404218                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85663.109756                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 90745.731265                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 81075.836687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80811.348926                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81644.349445                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88155.649083                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 79829.484813                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 125684.206842                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data   195.063169                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data   571.266133                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total   299.504785                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4347.525015                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4533.993352                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4441.366577                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4938.694266                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5142.455568                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  5038.612771                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74003.580564                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73149.808908                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73583.152381                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81580.404218                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85663.109756                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 90745.731265                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 78910.521591                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80811.348926                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 81644.349445                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 88155.649083                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78013.313403                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 122676.753599                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81580.404218                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85663.109756                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 90745.731265                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78910.521591                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80811.348926                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81644.349445                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 88155.649083                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78013.313403                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116882.902441                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 122676.753599                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              4412                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       93                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     47.440860                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              910321                       # number of writebacks
system.l2c.writebacks::total                   910321                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          129                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          122                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               295                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          129                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          122                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                295                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          129                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          122                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               295                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker          569                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker          656                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         9307                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data        87196                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       698868                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         1304                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         1531                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         9203                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        99977                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       328827                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total         1237438                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data         9435                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data         3626                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total        13061                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        30881                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        31286                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        62167                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data         9976                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         9599                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        19575                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        38485                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        37338                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         75823                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker          569                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker          656                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         9307                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       125681                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       698868                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1304                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1531                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9203                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       137315                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       328827                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1313261                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker          569                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker          656                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         9307                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       125681                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       698868                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1304                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1531                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9203                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       137315                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       328827                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1313261                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker     39310750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker     47990500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    728789245                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   5976245749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  91523692653                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     89033499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    105818499                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    697155745                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data   6727481950                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  34415077377                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 140350595967                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data    188587078                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data     72419588                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total    261006666                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    312906599                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    316193537                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    629100136                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    101000382                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     97535510                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    198535892                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2362166158                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2259616901                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   4621783059                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker     39310750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker     47990500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    728789245                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data   8338411907                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  91523692653                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     89033499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    105818499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    697155745                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   8987098851                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  34415077377                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 144972379026                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker     39310750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker     47990500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    728789245                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data   8338411907                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  91523692653                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     89033499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    105818499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    697155745                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   8987098851                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  34415077377                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 144972379026                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2006968250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      6158750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3361769998                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7621094248                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1998731000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3265755499                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5264486499                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4005699250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      6158750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6627525497                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12885580747                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.093539                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.129567                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.066329                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.137025                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.297121                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.155238                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.193675                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.058976                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.141222                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.150672                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.199502                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.732133                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.473677                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.635819                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.493322                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.474793                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.483820                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.577482                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.527650                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.551922                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.455967                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.384956                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.417997                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.093539                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.129567                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.066329                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.174375                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.297121                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.155238                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.193675                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.058976                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.170592                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.150672                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.205710                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.093539                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.129567                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.066329                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.174375                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.297121                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.155238                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.193675                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.058976                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.170592                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.150672                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.205710                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 78305.495326                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68538.072262                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75753.096273                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67290.296268                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 113420.305476                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 19988.031585                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 19972.307777                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 19983.666335                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10132.657589                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10106.550438                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10119.518973                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10124.336608                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10161.007397                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10142.318876                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61378.878992                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60517.887969                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60954.895731                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 78305.495326                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66345.843103                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75753.096273                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65448.777271                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 110391.140090                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 69087.434095                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73156.250000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 78305.495326                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66345.843103                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130959.913250                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68277.223160                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 69117.242978                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75753.096273                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65448.777271                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104660.132462                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 110391.140090                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             1327465                       # Transaction distribution
system.membus.trans_dist::ReadResp            1327465                       # Transaction distribution
system.membus.trans_dist::WriteReq              37863                       # Transaction distribution
system.membus.trans_dist::WriteResp             37863                       # Transaction distribution
system.membus.trans_dist::Writeback           1017207                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       119813                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       119813                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           367379                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         281461                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           85028                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
system.membus.trans_dist::ReadExReq             87184                       # Transaction distribution
system.membus.trans_dist::ReadExResp            72708                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123480                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        22714                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4395675                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4541961                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       336541                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       336541                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4878502                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156518                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        45428                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    143082804                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    143284954                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14125504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14125504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               157410458                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           581037                       # Total snoops (count)
system.membus.snoop_fanout::samples           3119395                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3119395    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3119395                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101251489                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               55500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            19693498                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         11963097483                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy        12443113804                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          187409729                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            7096727                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           7089473                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             37863                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            37863                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          2477309                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq       127465                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp        20542                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          430421                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        297353                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         727774                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           53                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           53                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           228196                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          228196                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8832957                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8435767                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17268724                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    294458407                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    274483891                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              568942298                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1532220                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         10576474                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.010952                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.104077                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               10460641     98.90%     98.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115833      1.10%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           10576474                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        15316484616                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          7440499                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       16737915607                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       16438547163                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------