path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.566016                       # Number of seconds simulated
sim_ticks                                47566015848000                       # Number of ticks simulated
final_tick                               47566015848000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 675626                       # Simulator instruction rate (inst/s)
host_op_rate                                   794684                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            35963293075                       # Simulator tick rate (ticks/s)
host_mem_usage                                 873656                       # Number of bytes of host memory used
host_seconds                                  1322.63                       # Real time elapsed on the host
sim_insts                                   893600449                       # Number of instructions simulated
sim_ops                                    1051070162                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       233408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       408704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           743028                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13616152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     28206528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       271488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       437568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           534776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         13513568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     26761152                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        461312                       # Number of bytes read from this memory
system.physmem.bytes_read::total             85187684                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       743028                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       534776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1277804                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     43935424                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data      56825292                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data      43859652                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      6846976                       # Number of bytes written to this memory
system.physmem.bytes_written::total         151467344                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3647                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         6386                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             52017                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            212774                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       440727                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         4242                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         6837                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              8444                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            211164                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       418143                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           7208                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1371589                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          686491                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           890172                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           685308                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide        106984                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              2368955                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          4907                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          8592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               15621                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              286258                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       592997                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          5708                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          9199                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               11243                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              284101                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       562611                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9698                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1790936                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          15621                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          11243                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              26864                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            923673                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data            1194662                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             922080                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          143947                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3184361                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            923673                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4907                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         8592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              15621                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1480920                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       592997                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         5708                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         9199                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              11243                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1206181                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       562611                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          153645                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4975296                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1371589                       # Number of read requests accepted
system.physmem.writeReqs                      2368955                       # Number of write requests accepted
system.physmem.readBursts                     1371589                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    2368955                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 87480576                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    301120                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 145871552                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  85187684                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              151467344                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     4705                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   89687                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          96177                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               85059                       # Per bank write bursts
system.physmem.perBankRdBursts::1               83413                       # Per bank write bursts
system.physmem.perBankRdBursts::2               77756                       # Per bank write bursts
system.physmem.perBankRdBursts::3               83623                       # Per bank write bursts
system.physmem.perBankRdBursts::4               79267                       # Per bank write bursts
system.physmem.perBankRdBursts::5               92440                       # Per bank write bursts
system.physmem.perBankRdBursts::6               79265                       # Per bank write bursts
system.physmem.perBankRdBursts::7               88179                       # Per bank write bursts
system.physmem.perBankRdBursts::8               75468                       # Per bank write bursts
system.physmem.perBankRdBursts::9              124700                       # Per bank write bursts
system.physmem.perBankRdBursts::10              77875                       # Per bank write bursts
system.physmem.perBankRdBursts::11              89966                       # Per bank write bursts
system.physmem.perBankRdBursts::12              78954                       # Per bank write bursts
system.physmem.perBankRdBursts::13              87199                       # Per bank write bursts
system.physmem.perBankRdBursts::14              85039                       # Per bank write bursts
system.physmem.perBankRdBursts::15              78681                       # Per bank write bursts
system.physmem.perBankWrBursts::0              146127                       # Per bank write bursts
system.physmem.perBankWrBursts::1              131230                       # Per bank write bursts
system.physmem.perBankWrBursts::2              144620                       # Per bank write bursts
system.physmem.perBankWrBursts::3              127213                       # Per bank write bursts
system.physmem.perBankWrBursts::4              148937                       # Per bank write bursts
system.physmem.perBankWrBursts::5              150009                       # Per bank write bursts
system.physmem.perBankWrBursts::6              182023                       # Per bank write bursts
system.physmem.perBankWrBursts::7              144700                       # Per bank write bursts
system.physmem.perBankWrBursts::8              124458                       # Per bank write bursts
system.physmem.perBankWrBursts::9              140305                       # Per bank write bursts
system.physmem.perBankWrBursts::10             119798                       # Per bank write bursts
system.physmem.perBankWrBursts::11             155853                       # Per bank write bursts
system.physmem.perBankWrBursts::12             153554                       # Per bank write bursts
system.physmem.perBankWrBursts::13             129042                       # Per bank write bursts
system.physmem.perBankWrBursts::14             144270                       # Per bank write bursts
system.physmem.perBankWrBursts::15             137104                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    47566012867000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1328352                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                2366352                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    854051                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    158360                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     84564                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     68503                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     51448                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     44074                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     37830                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     31756                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     25068                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4404                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1973                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1006                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      782                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      292                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      229                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    89303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    97776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   118763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   123056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   124315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   149365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   133979                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   128880                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   131405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   133820                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   133411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   132599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   131583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   133798                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   128352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   124285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   123534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   120195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     4121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      384                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       832768                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      280.211728                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     152.211424                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     337.275385                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         413524     49.66%     49.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       160093     19.22%     68.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        57236      6.87%     75.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        29306      3.52%     79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        24972      3.00%     82.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        16042      1.93%     84.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        12534      1.51%     85.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        12228      1.47%     87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       106833     12.83%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         832768                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples        117976                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        11.586017                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      192.972695                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047         117973    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-22527            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-59391            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total          117976                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples        117976                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.319548                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.993188                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        4.933657                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           75459     63.96%     63.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23           36712     31.12%     95.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            3025      2.56%     97.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             865      0.73%     98.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             773      0.66%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             198      0.17%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             143      0.12%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              73      0.06%     99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              88      0.07%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              20      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              14      0.01%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.01%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             383      0.32%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              36      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              51      0.04%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              22      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              46      0.04%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               9      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             5      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             6      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            16      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total          117976                       # Writes before turning the bus around for reads
system.physmem.totQLat                    39242427762                       # Total ticks spent queuing
system.physmem.totMemAccLat               64871502762                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6834420000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28709.41                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47459.41                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.84                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.07                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.79                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.18                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.32                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.10                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1063781                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1749574                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.76                       # Row buffer hit rate for writes
system.physmem.avgGap                     12716335.61                       # Average gap between requests
system.physmem.pageHitRate                      77.16                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     45509072189751                       # Time in different power states
system.physmem.memoryStateTime::REF      1588333760000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      468608703999                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                3171472920                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                3124253160                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1730466375                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1704701625                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               5218192200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               5443409400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              7613086320                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              7156408320                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3106780834560                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3106780834560                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1266482203425                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1265693181210                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          27428659482750                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          27429351607500                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            31819655738550                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            31819254395775                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.957784                       # Core power per rank (mW)
system.physmem.averagePower::1             668.949346                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    86716512                       # DTB read hits
system.cpu0.dtb.read_misses                     82712                       # DTB read misses
system.cpu0.dtb.write_hits                   78633728                       # DTB write hits
system.cpu0.dtb.write_misses                    28389                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   34135                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4682                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9159                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                86799224                       # DTB read accesses
system.cpu0.dtb.write_accesses               78662117                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        165350240                       # DTB hits
system.cpu0.dtb.misses                         111101                       # DTB misses
system.cpu0.dtb.accesses                    165461341                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   459685693                       # ITB inst hits
system.cpu0.itb.inst_misses                     60045                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   24187                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               459745738                       # ITB inst accesses
system.cpu0.itb.hits                        459685693                       # DTB hits
system.cpu0.itb.misses                          60045                       # DTB misses
system.cpu0.itb.accesses                    459745738                       # DTB accesses
system.cpu0.numCycles                     95132031682                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  459439593                       # Number of instructions committed
system.cpu0.committedOps                    539347874                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            495403687                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                451172                       # Number of float alu accesses
system.cpu0.num_func_calls                   27064307                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     69711991                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   495403687                       # number of integer instructions
system.cpu0.num_fp_insts                       451172                       # number of float instructions
system.cpu0.num_int_register_reads          715734727                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         392523746                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              749199                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             337216                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           119686995                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          119275623                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    165340768                       # number of memory refs
system.cpu0.num_load_insts                   86711184                       # Number of load instructions
system.cpu0.num_store_insts                  78629584                       # Number of store instructions
system.cpu0.num_idle_cycles              94014587829.536469                       # Number of idle cycles
system.cpu0.num_busy_cycles              1117443852.463529                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011746                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988254                       # Percentage of idle cycles
system.cpu0.Branches                        102470244                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                373021399     69.12%     69.12% # Class of executed instruction
system.cpu0.op_class::IntMult                 1165287      0.22%     69.34% # Class of executed instruction
system.cpu0.op_class::IntDiv                    62749      0.01%     69.35% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             46895      0.01%     69.36% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.36% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.36% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.36% # Class of executed instruction
system.cpu0.op_class::MemRead                86711184     16.07%     85.43% # Class of executed instruction
system.cpu0.op_class::MemWrite               78629584     14.57%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 539637098                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5368                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          5553236                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          507.463915                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          159572063                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5553747                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.732325                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3644536500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.463915                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.991140                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.991140                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        336276505                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       336276505                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80841388                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       80841388                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     74354122                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      74354122                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186421                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       186421                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       887570                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       887570                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1858688                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1858688                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1820106                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1820106                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    155195510                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       155195510                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    155381931                       # number of overall hits
system.cpu0.dcache.overall_hits::total      155381931                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3020518                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3020518                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1355895                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1355895                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       638649                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       638649                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       156836                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       156836                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194186                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       194186                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4376413                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4376413                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5015062                       # number of overall misses
system.cpu0.dcache.overall_misses::total      5015062                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  44235181893                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  44235181893                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  23644478419                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  23644478419                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2243299062                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2243299062                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4135736633                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4135736633                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1563000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1563000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  67879660312                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  67879660312                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  67879660312                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  67879660312                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83861906                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     83861906                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     75710017                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     75710017                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       825070                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       825070                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       887570                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total       887570                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2015524                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2015524                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2014292                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2014292                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    159571923                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    159571923                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    160396993                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    160396993                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036018                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036018                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017909                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.017909                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.774054                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.774054                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077814                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077814                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.096404                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.096404                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027426                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027426                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031267                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.031267                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17438.281297                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14303.470262                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21297.810517                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15510.341531                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15510.341531                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13535.158750                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                 887570                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      3048439                       # number of writebacks
system.cpu0.dcache.writebacks::total          3048439                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        28957                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        28957                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21342                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21342                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        43075                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        43075                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        50299                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        50299                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        50299                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        50299                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2991561                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2991561                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1334553                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1334553                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       637409                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       637409                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113761                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113761                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194186                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       194186                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4326114                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4326114                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4963523                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4963523                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  36853741584                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  36853741584                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  20599874090                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  20599874090                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14249969925                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14249969925                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  39555111210                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  39555111210                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1322683967                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1322683967                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3736995367                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3736995367                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1491000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1491000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  57453615674                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  57453615674                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  71703585599                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  71703585599                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2269904707                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2269904707                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2228690449                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2228690449                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4498595156                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4498595156                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.035672                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.035672                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017627                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017627                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.772551                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.772551                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056442                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056442                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.096404                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.096404                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027111                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027111                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030945                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.030945                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.234535                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.234535                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15435.785683                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15435.785683                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22356.085222                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22356.085222                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11626.866562                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19244.411889                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19244.411889                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13280.652261                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13280.652261                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14446.107251                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14446.107251                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          5136279                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.921269                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          454548902                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5136791                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.488884                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      24248022750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.921269                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        924508177                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       924508177                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    454548902                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      454548902                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    454548902                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       454548902                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    454548902                       # number of overall hits
system.cpu0.icache.overall_hits::total      454548902                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5136791                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5136791                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5136791                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5136791                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5136791                       # number of overall misses
system.cpu0.icache.overall_misses::total      5136791                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  44728233484                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  44728233484                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  44728233484                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  44728233484                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  44728233484                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  44728233484                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    459685693                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    459685693                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    459685693                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    459685693                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    459685693                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    459685693                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011175                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011175                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011175                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011175                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011175                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011175                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8707.427163                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8707.427163                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8707.427163                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8707.427163                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8707.427163                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8707.427163                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5136791                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      5136791                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      5136791                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      5136791                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      5136791                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      5136791                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  37020068050                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  37020068050                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  37020068050                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  37020068050                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  37020068050                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  37020068050                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3405609750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3405609750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011175                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011175                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011175                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.011175                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011175                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.011175                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7206.847242                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7206.847242                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7206.847242                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7206.847242                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7206.847242                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7206.847242                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     47709911                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       798067                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     44351595                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8146                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          467                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      2551636                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3941553                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements         3159231                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16263.767973                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          10999510                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         3175316                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.464068                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     20647851500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  3883.106993                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    48.905367                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    55.754013                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   900.341601                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  2586.177603                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8789.482396                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.237006                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002985                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003403                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.054952                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.157848                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.536467                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.992662                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8304                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023          112                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7669                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           44                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          543                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2171                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         5264                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          282                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1           10                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           43                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           59                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          738                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3430                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         3305                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          150                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.506836                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.006836                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.468079                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       240919913                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      240919913                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       231031                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       134927                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4959117                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2742170                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       8067245                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      3048439                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      3048439                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        86825                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        86825                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        33826                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        33826                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       910939                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       910939                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       231031                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       134927                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4959117                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3653109                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8978184                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       231031                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       134927                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4959117                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3653109                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8978184                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12665                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11145                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       177674                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data      1000560                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1202044                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       109590                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       109590                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       160357                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       160357                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            3                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       232216                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       232216                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12665                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11145                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       177674                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1232776                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1434260                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12665                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11145                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       177674                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1232776                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1434260                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    536996706                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    703824955                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   4673573829                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  32218538016                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  38132933506                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2159798630                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2159798630                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3254740509                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3254740509                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1454999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1454999                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  10558981803                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  10558981803                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    536996706                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    703824955                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4673573829                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  42777519819                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  48691915309                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    536996706                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    703824955                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4673573829                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  42777519819                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  48691915309                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       243696                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       146072                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      5136791                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3742730                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      9269289                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      3048439                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      3048439                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       196415                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       196415                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       194183                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       194183                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1143155                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1143155                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       243696                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       146072                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5136791                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4885885                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     10412444                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       243696                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       146072                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5136791                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4885885                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     10412444                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.051970                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.076298                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.034589                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.267334                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.129680                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.557951                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.557951                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.825803                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.825803                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.203136                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.203136                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.051970                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.076298                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034589                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.252314                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.137745                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.051970                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.076298                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034589                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.252314                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.137745                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42400.055744                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63151.633468                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26304.207869                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32200.505733                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31723.409048                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19707.990054                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19707.990054                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20296.840855                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20296.840855                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 484999.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 484999.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45470.517979                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45470.517979                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42400.055744                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63151.633468                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26304.207869                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34700.156248                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 33949.155180                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42400.055744                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63151.633468                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26304.207869                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34700.156248                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 33949.155180                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs        12605                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs             256                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    49.238281                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks      1033934                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1033934                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst        26777                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         5375                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total        32152                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4949                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         4949                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        26777                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10324                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        37101                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        26777                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10324                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        37101                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12665                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11145                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       150897                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       995185                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1169892                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      2551548                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total      2551548                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       109590                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       109590                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       160357                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       160357                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       227267                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       227267                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12665                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11145                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       150897                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1222452                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1397159                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12665                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        11145                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       150897                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1222452                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher      2551548                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      3948707                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    447628804                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    624653553                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   3182608268                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  25035600452                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  29290491077                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  74439584886                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  74439584886                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  32897037766                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  32897037766                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1861391719                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1861391719                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2218823079                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2218823079                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1202999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1202999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   8430579619                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   8430579619                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    447628804                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    624653553                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3182608268                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  33466180071                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  37721070696                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    447628804                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    624653553                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3182608268                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  33466180071                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  74439584886                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 112160655582                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2157592792                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5219457542                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2114914551                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2114914551                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4272507343                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7334372093                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.051970                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.076298                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.029376                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.265898                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.126212                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.557951                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.557951                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.825803                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.825803                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.198807                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.198807                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.051970                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.076298                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.029376                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.250201                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.134182                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.051970                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.076298                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.029376                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.250201                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.379230                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21091.262702                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25156.730107                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25036.918858                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29174.283567                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      12709886                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9530898                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        15163                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        15163                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      3048439                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      3732092                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1679869                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       887570                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       380241                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       351950                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       457079                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           47                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           80                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1289201                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1150842                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     10359832                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     15601688                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       325277                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       566209                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         26853006                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    328927124                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    571100341                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1168576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1949568                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         903145609                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    8562261                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     23134597                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.358060                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.479430                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5          14851033     64.19%     64.19% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6           8283564     35.81%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      23134597                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   11405856452                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    183601993                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7759954717                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   8048372726                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    179758799                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    322845049                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    81769828                       # DTB read hits
system.cpu1.dtb.read_misses                     79673                       # DTB read misses
system.cpu1.dtb.write_hits                   74311746                       # DTB write hits
system.cpu1.dtb.write_misses                    27355                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   41105                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4547                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10770                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                81849501                       # DTB read accesses
system.cpu1.dtb.write_accesses               74339101                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        156081574                       # DTB hits
system.cpu1.dtb.misses                         107028                       # DTB misses
system.cpu1.dtb.accesses                    156188602                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                   434473512                       # ITB inst hits
system.cpu1.itb.inst_misses                     57336                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              41884                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1051                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   28749                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               434530848                       # ITB inst accesses
system.cpu1.itb.hits                        434473512                       # DTB hits
system.cpu1.itb.misses                          57336                       # DTB misses
system.cpu1.itb.accesses                    434530848                       # DTB accesses
system.cpu1.numCycles                     95132031696                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  434160856                       # Number of instructions committed
system.cpu1.committedOps                    511722288                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            470175639                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                456535                       # Number of float alu accesses
system.cpu1.num_func_calls                   26230713                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     66122636                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   470175639                       # number of integer instructions
system.cpu1.num_fp_insts                       456535                       # number of float instructions
system.cpu1.num_int_register_reads          688104482                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         373632663                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              726332                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             408756                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           113709240                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          113476936                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    156073929                       # number of memory refs
system.cpu1.num_load_insts                   81768358                       # Number of load instructions
system.cpu1.num_store_insts                  74305571                       # Number of store instructions
system.cpu1.num_idle_cycles              94082707842.004028                       # Number of idle cycles
system.cpu1.num_busy_cycles              1049323853.995978                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011030                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988970                       # Percentage of idle cycles
system.cpu1.Branches                         96877428                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                354755827     69.28%     69.28% # Class of executed instruction
system.cpu1.op_class::IntMult                 1081291      0.21%     69.49% # Class of executed instruction
system.cpu1.op_class::IntDiv                    57437      0.01%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             66526      0.01%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
system.cpu1.op_class::MemRead                81768358     15.97%     85.49% # Class of executed instruction
system.cpu1.op_class::MemWrite               74305571     14.51%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 512035053                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13728                       # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements          5229569                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          446.555743                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          150635340                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5230081                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.801722                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8374220312000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   446.555743                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.872179                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.872179                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          408                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        317363377                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       317363377                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     76086699                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       76086699                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     70396756                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      70396756                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       188905                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       188905                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       685307                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total       685307                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1701097                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1701097                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1676869                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1676869                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    146483455                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       146483455                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    146672360                       # number of overall hits
system.cpu1.dcache.overall_hits::total      146672360                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      2949268                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      2949268                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1324938                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1324938                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       648778                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       648778                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       170596                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       170596                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       193531                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       193531                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4274206                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4274206                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      4922984                       # number of overall misses
system.cpu1.dcache.overall_misses::total      4922984                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  43925732439                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  43925732439                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  22816644952                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  22816644952                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2487645065                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2487645065                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4103865813                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4103865813                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1896000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1896000                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  66742377391                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  66742377391                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  66742377391                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  66742377391                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     79035967                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     79035967                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     71721694                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     71721694                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       837683                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       837683                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       685307                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       685307                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1871693                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1871693                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1870400                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1870400                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    150757661                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    150757661                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    151595344                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    151595344                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037316                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037316                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018473                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018473                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.774491                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.774491                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091145                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091145                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103470                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103470                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028352                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.028352                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032475                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.032475                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                 685307                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      2978181                       # number of writebacks
system.cpu1.dcache.writebacks::total          2978181                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        23865                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        23865                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          515                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          515                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        45192                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        45192                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        24380                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        24380                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        24380                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        24380                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2925403                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      2925403                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1324423                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1324423                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       648778                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       648778                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       125404                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       125404                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       193531                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       193531                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4249826                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4249826                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      4898604                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      4898604                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  36900792539                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  36900792539                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20082419307                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20082419307                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13833136236                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13833136236                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  30583171682                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  30583171682                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1453819204                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1453819204                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3706136187                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3706136187                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1808000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1808000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  56983211846                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  56983211846                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  70816348082                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  70816348082                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4114514480                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4114514480                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3994198470                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3994198470                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8108712950                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8108712950                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.037014                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.037014                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018466                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018466                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.774491                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.774491                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067000                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067000                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103470                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103470                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028190                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028190                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032314                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032314                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements          4838786                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.335132                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          429634209                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4839298                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            88.780275                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8374030789000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.335132                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969405                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969405                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        873786327                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       873786327                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    429634209                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      429634209                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    429634209                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       429634209                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    429634209                       # number of overall hits
system.cpu1.icache.overall_hits::total      429634209                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4839303                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4839303                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4839303                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4839303                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4839303                       # number of overall misses
system.cpu1.icache.overall_misses::total      4839303                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  42201450669                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  42201450669                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  42201450669                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  42201450669                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  42201450669                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  42201450669                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    434473512                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    434473512                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    434473512                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    434473512                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    434473512                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    434473512                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011138                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011138                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011138                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011138                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011138                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011138                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8720.563823                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8720.563823                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8720.563823                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8720.563823                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8720.563823                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8720.563823                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4839303                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      4839303                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      4839303                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      4839303                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      4839303                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      4839303                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  34939638885                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  34939638885                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  34939638885                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  34939638885                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  34939638885                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  34939638885                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8745500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8745500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8745500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8745500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011138                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011138                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011138                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011138                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011138                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011138                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7219.973390                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7219.973390                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7219.973390                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7219.973390                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7219.973390                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7219.973390                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     45129085                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       818764                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     41906843                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8141                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          514                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2394823                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3842139                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements         3029134                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13674.379805                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          10606046                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         3045261                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            3.482804                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10454752865000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  4179.016177                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    54.517433                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    70.326677                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   591.513668                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3188.927208                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  5590.078642                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.255067                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003327                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004292                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.036103                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.194637                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.341191                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.834618                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         8556                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           61                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         7510                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0           76                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1          438                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         3359                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4072                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          611                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           24                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           28                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          492                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         2836                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3841                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          307                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.522217                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003723                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.458374                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       230495604                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      230495604                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       221576                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       129888                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4667071                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2714218                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       7732753                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      2978176                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      2978176                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        79936                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        79936                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        35720                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        35720                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       908771                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       908771                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       221576                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       129888                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4667071                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3622989                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8641524                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       221576                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       129888                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4667071                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3622989                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8641524                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12665                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        11221                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       172232                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data       985367                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1181485                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       109801                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       109801                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       157805                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       157805                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       226147                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       226147                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12665                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        11221                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       172232                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1211514                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1407632                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12665                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        11221                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       172232                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1211514                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1407632                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    578928201                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    733432437                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   4494366580                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  32191641510                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  37998368728                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2189702140                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2189702140                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3225705678                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3225705678                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1763999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1763999                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10153420884                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10153420884                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    578928201                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    733432437                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   4494366580                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  42345062394                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  48151789612                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    578928201                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    733432437                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   4494366580                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  42345062394                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  48151789612                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       234241                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       141109                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      4839303                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3699585                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      8914238                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      2978176                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      2978176                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       189737                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       189737                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       193525                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       193525                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1134918                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1134918                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       234241                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       141109                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4839303                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4834503                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10049156                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       234241                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       141109                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4839303                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4834503                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10049156                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.054068                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.079520                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.035590                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.266345                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.132539                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.578701                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.578701                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.815424                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.815424                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.199263                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.199263                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.054068                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.079520                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.035590                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.250597                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.140075                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.054068                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.079520                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.035590                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.250597                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.140075                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 45710.872562                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 65362.484360                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26094.840564                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32669.697189                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32161.532925                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19942.460815                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19942.460815                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20441.086645                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20441.086645                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 293999.833333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 293999.833333                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44897.437879                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44897.437879                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 45710.872562                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 65362.484360                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26094.840564                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34952.185773                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34207.654850                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 45710.872562                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 65362.484360                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26094.840564                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34952.185773                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34207.654850                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         6147                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             166                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    37.030120                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks       960563                       # number of writebacks
system.cpu1.l2cache.writebacks::total          960563                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        26607                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data          912                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total        27519                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6089                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         6089                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        26607                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7001                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        33608                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        26607                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7001                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        33608                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12665                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        11221                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       145625                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data       984455                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1153966                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      2394712                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total      2394712                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       109801                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       109801                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       157805                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       157805                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       220058                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       220058                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12665                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        11221                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       145625                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1204513                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1374024                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12665                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        11221                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       145625                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1204513                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      2394712                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      3768736                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    489322313                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    653538067                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   3045903499                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  25194010676                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  29382774555                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  71059948043                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  71059948043                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  25441892262                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total  25441892262                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   1899234087                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   1899234087                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2195015270                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2195015270                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1455999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1455999                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   7950904534                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   7950904534                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    489322313                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    653538067                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   3045903499                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  33144915210                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  37333679089                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    489322313                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    653538067                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   3045903499                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  33144915210                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  71059948043                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 108393627132                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7884500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3918463269                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3926347769                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3819021030                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3819021030                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7884500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7737484299                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7745368799                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.054068                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.079520                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.030092                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.266099                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.129452                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.578701                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.578701                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.815424                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.815424                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.193898                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.193898                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.054068                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.079520                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.030092                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.249149                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.136730                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.054068                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.079520                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.030092                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.249149                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.375030                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      12427806                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9137324                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        23353                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        23353                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      2978176                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      3478890                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1679869                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       685307                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       370922                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       353849                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       446809                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           80                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1290596                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1141918                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      9678826                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15042396                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       312565                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       544877                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         25578664                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    309715832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    550341480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1128872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1873928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         863060112                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    8621982                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     22555543                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.370325                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.482892                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5          14202655     62.97%     62.97% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6           8352888     37.03%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      22555543                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   10801104660                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    179932994                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7260511142                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7881710673                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    172097315                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    311084554                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40536                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40536                       # Transaction distribution
system.iobus.trans_dist::WriteReq              137093                       # Transaction distribution
system.iobus.trans_dist::WriteResp             137147                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           54                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48328                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123470                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231816                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231816                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  355366                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48348                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156485                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7355616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7514187                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36745000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            22142000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           984235192                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93310000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179557795                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115889                       # number of replacements
system.iocache.tags.tagsinuse               11.315870                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115905                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9130394779000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.824342                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.491528                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.239021                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.468221                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.707242                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1043961                       # Number of tag accesses
system.iocache.tags.data_accesses             1043961                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide       106984                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total       106984                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8924                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8961                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           54                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           54                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8924                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8964                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8924                       # number of overall misses
system.iocache.overall_misses::total             8964                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1957100855                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1962807855                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      6064000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1957100855                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1963164855                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      6064000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1957100855                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1963164855                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8924                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8961                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       107038                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       107038                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8924                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8964                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8924                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8964                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000504                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000504                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 219307.581242                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 219038.930365                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 219307.581242                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 219005.450134                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 219307.581242                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 219005.450134                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         53861                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.810747                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                     106984                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8924                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8961                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8924                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8964                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8924                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8964                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1492924359                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1496707359                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6628374628                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6628374628                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1492924359                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1496908359                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1492924359                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1496908359                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167293.182317                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 167024.590894                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 167293.182317                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 166991.115462                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 167293.182317                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 166991.115462                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1086855                       # number of replacements
system.l2c.tags.tagsinuse                64099.647179                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6672114                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1148598                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     5.808920                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    9469.927163                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    51.211523                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    68.031290                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      696.373428                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3179.738420                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17944.005062                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   291.904824                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   401.470147                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      563.131009                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    10017.603756                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 21416.250557                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.144500                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000781                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.001038                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.010626                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.048519                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.273804                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004454                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006126                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.008593                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.152857                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.326786                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.978083                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        31587                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          309                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        29847                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0            9                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1          114                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2         1585                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         4136                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        25743                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1            9                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2           33                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3           47                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          219                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          163                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1360                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         9152                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        19154                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.481979                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004715                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.455429                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 80637866                       # Number of tag accesses
system.l2c.tags.data_accesses                80637866                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         6250                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         4321                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             142068                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             620262                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1618371                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6096                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4059                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             137369                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             611754                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1545913                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                4696463                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         1994497                       # number of Writeback hits
system.l2c.Writeback_hits::total              1994497                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           23769                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           27954                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               51723                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          7971                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          7653                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             15624                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            52432                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            49853                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               102285                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          6250                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4321                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              142068                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              672694                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher      1618371                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6096                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4059                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              137369                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              661607                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher      1545913                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 4798748                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         6250                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4321                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             142068                       # number of overall hits
system.l2c.overall_hits::cpu0.data             672694                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher      1618371                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6096                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4059                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             137369                       # number of overall hits
system.l2c.overall_hits::cpu1.data             661607                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher      1545913                       # number of overall hits
system.l2c.overall_hits::total                4798748                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         3647                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         6386                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             8946                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           136148                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       441016                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         4242                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         6837                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             8364                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           140626                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       418325                       # number of ReadReq misses
system.l2c.ReadReq_misses::total              1174537                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         34627                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         36381                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             71008                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10699                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        11055                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           21754                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          78297                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          72282                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             150579                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3647                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         6386                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8946                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            214445                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       441016                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         4242                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         6837                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              8364                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            212908                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       418325                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1325116                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3647                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         6386                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8946                       # number of overall misses
system.l2c.overall_misses::cpu0.data           214445                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       441016                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         4242                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         6837                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             8364                       # number of overall misses
system.l2c.overall_misses::cpu1.data           212908                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       418325                       # number of overall misses
system.l2c.overall_misses::total              1325116                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    290095498                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    510585994                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    795450996                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  11077065870                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  46140706698                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    335992750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    542306996                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    742040494                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  11432821383                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  44423863626                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total   116290930305                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    147041544                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    142085765                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    289127309                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     51916806                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     56203152                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    108119958                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5726616061                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5297244481                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11023860542                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    290095498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    510585994                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    795450996                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  16803681931                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  46140706698                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    335992750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    542306996                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    742040494                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16730065864                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  44423863626                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    127314790847                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    290095498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    510585994                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    795450996                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  16803681931                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  46140706698                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    335992750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    542306996                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    742040494                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16730065864                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  44423863626                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   127314790847                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         9897                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10707                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         151014                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         756410                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      2059387                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        10338                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        10896                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         145733                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         752380                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      1964238                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            5871000                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1994497                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1994497                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        58396                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        64335                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          122731                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        18670                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        18708                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         37378                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       130729                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       122135                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           252864                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9897                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10707                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          151014                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          887139                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher      2059387                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        10338                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        10896                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          145733                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          874515                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher      1964238                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             6123864                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9897                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10707                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         151014                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         887139                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher      2059387                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        10338                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        10896                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         145733                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         874515                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher      1964238                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            6123864                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.368496                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.596432                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.059240                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.179992                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.214149                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.410331                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.627478                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.057393                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.186908                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.212971                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.200057                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.592969                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.565493                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.578566                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.573058                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590924                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.582000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.598926                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.591821                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.595494                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.368496                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.596432                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.059240                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.241726                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.214149                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.410331                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.627478                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.057393                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.243458                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.212971                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.216386                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.368496                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.596432                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.059240                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.241726                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.214149                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.410331                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.627478                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.057393                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.243458                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.212971                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.216386                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79543.596929                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79953.960852                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 88916.945674                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 81360.474410                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79206.211693                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 79319.437765                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88718.375658                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 81299.485038                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 99010.018675                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4246.441909                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3905.493664                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4071.756830                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4852.491448                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5083.957666                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4970.118507                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73139.661302                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73285.803948                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73209.813732                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79543.596929                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79953.960852                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 88916.945674                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 78358.935536                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79206.211693                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 79319.437765                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 88718.375658                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78578.850320                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 96078.223225                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79543.596929                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79953.960852                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 88916.945674                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78358.935536                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 104623.656960                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79206.211693                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 79319.437765                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 88718.375658                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78578.850320                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106194.618122                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 96078.223225                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              2524                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       54                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     46.740741                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              686491                       # number of writebacks
system.l2c.writebacks::total                   686491                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst            30                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          289                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            14                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          182                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               551                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             30                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          289                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          182                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                551                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            30                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          289                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          182                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               551                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         3647                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         6386                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         8916                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       136124                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       440727                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         4242                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         6837                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         8350                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       140614                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       418143                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total         1173986                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        34627                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        36381                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        71008                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10699                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11055                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        21754                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        78297                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        72282                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        150579                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3647                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         6386                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8916                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       214421                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       440727                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         4242                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         6837                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         8350                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       212896                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       418143                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1324565                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3647                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         6386                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8916                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       214421                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       440727                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         4242                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         6837                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         8350                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       212896                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       418143                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1324565                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    244781998                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    431307994                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    682060496                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   9367961184                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  40693405448                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    283137750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    457339496                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    636822998                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data   9667271945                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  39253909640                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 101717998949                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  17785049779                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data  13763550872                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  31548600651                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    351208941                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    368943627                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    720152568                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    109133556                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    113272386                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    222405942                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4739079365                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4385575961                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9124655326                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    244781998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    431307994                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    682060496                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  14107040549                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  40693405448                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    283137750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    457339496                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    636822998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  14052847906                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  39253909640                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 110842654275                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    244781998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    431307994                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    682060496                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  14107040549                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  40693405448                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    283137750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    457339496                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    636822998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  14052847906                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  39253909640                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 110842654275                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1903247752                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5835000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3476254750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7631534752                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1855610501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3420953000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5276563501                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3758858253                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5835000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6897207750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12908098253                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.368496                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.596432                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.059041                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.179961                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.214009                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.410331                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.627478                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.057297                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.186892                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.212878                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.199964                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.592969                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.565493                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.578566                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.573058                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590924                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.582000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.598926                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.591821                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.595494                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.368496                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.596432                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.059041                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.241699                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.214009                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.410331                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.627478                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.057297                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.243445                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.212878                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.216296                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.368496                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.596432                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.059041                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.241699                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.214009                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.410331                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.627478                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.057297                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.243445                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.212878                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.216296                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 76498.485419                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68819.320502                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76266.227305                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68750.422753                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 86643.281052                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10142.632657                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10141.107364                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10141.851172                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10200.351061                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.258345                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10223.680335                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60526.959717                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60673.140768                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60597.130583                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76498.485419                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65791.319642                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76266.227305                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66008.041044                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 83682.306474                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76498.485419                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65791.319642                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76266.227305                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66008.041044                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 83682.306474                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq             1264717                       # Transaction distribution
system.membus.trans_dist::ReadResp            1264717                       # Transaction distribution
system.membus.trans_dist::WriteReq              38516                       # Transaction distribution
system.membus.trans_dist::WriteResp             38516                       # Transaction distribution
system.membus.trans_dist::Writeback            686491                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq      1679861                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp      1679861                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           316703                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         302467                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           96183                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
system.membus.trans_dist::ReadExReq            163141                       # Transaction distribution
system.membus.trans_dist::ReadExResp           147161                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123470                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25330                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      7297543                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      7446435                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       230140                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       230140                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                7676575                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156485                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50660                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    229346740                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    229554089                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7308288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7308288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               236862377                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           540732                       # Total snoops (count)
system.membus.snoop_fanout::samples           4331622                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4331622    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4331622                       # Request fanout histogram
system.membus.reqLayer0.occupancy           101146499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            22031996                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         23154905719                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy        14237686781                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          187996205                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             162                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              162                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            6727338                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           6719778                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38516                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38516                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1994497                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq      1679869                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp      1572877                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          365008                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        318091                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         683099                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq           80                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp           80                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           301724                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          301724                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10020344                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9267363                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              19287707                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    322818441                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    297911776                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              620730217                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1454894                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         11304872                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.010257                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.100757                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               11188916     98.97%     98.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115956      1.03%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           11304872                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        19960086799                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          6306000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       16653624789                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       15972471023                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------