path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.438275                       # Number of seconds simulated
sim_ticks                                47438274662000                       # Number of ticks simulated
final_tick                               47438274662000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 649244                       # Simulator instruction rate (inst/s)
host_op_rate                                   763603                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            34889420828                       # Simulator tick rate (ticks/s)
host_mem_usage                                 811016                       # Number of bytes of host memory used
host_seconds                                  1359.68                       # Real time elapsed on the host
sim_insts                                   882760938                       # Number of instructions simulated
sim_ops                                    1038251286                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.ide        477376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker       221952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       405952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           701748                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         13046680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     27196672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       278976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       430208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           568824                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         13928160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     27822464                       # Number of bytes read from this memory
system.physmem.bytes_read::total             85079012                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       701748                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       568824                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1270572                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     44376640                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      6830592                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data      54965772                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data      45117316                       # Number of bytes written to this memory
system.physmem.bytes_written::total         151290320                       # Number of bytes written to this memory
system.physmem.num_reads::realview.ide           7459                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker         3468                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         6343                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             51372                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            203876                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       424948                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         4359                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         6722                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              8976                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            217642                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       434726                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1369891                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          693385                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide        106728                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           861117                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           704959                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              2366189                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide            10063                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker          4679                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          8557                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               14793                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              275024                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       573307                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          5881                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          9069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               11991                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              293606                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       586498                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1793468                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          14793                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          11991                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              26784                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            935461                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          143989                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data            1158680                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             951074                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3189204                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            935461                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          154052                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4679                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         8557                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              14793                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1433704                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       573307                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         5881                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         9069                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              11991                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data            1244680                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       586498                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4982671                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1369891                       # Number of read requests accepted
system.physmem.writeReqs                      2366189                       # Number of write requests accepted
system.physmem.readBursts                     1369891                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    2366189                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 87382976                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    290048                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 145690880                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  85079012                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              151290320                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     4532                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   89741                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          95337                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               80179                       # Per bank write bursts
system.physmem.perBankRdBursts::1               81898                       # Per bank write bursts
system.physmem.perBankRdBursts::2               76695                       # Per bank write bursts
system.physmem.perBankRdBursts::3               88857                       # Per bank write bursts
system.physmem.perBankRdBursts::4               82614                       # Per bank write bursts
system.physmem.perBankRdBursts::5               89869                       # Per bank write bursts
system.physmem.perBankRdBursts::6               79228                       # Per bank write bursts
system.physmem.perBankRdBursts::7               87605                       # Per bank write bursts
system.physmem.perBankRdBursts::8               77754                       # Per bank write bursts
system.physmem.perBankRdBursts::9              127975                       # Per bank write bursts
system.physmem.perBankRdBursts::10              81231                       # Per bank write bursts
system.physmem.perBankRdBursts::11              85621                       # Per bank write bursts
system.physmem.perBankRdBursts::12              74411                       # Per bank write bursts
system.physmem.perBankRdBursts::13              85967                       # Per bank write bursts
system.physmem.perBankRdBursts::14              83368                       # Per bank write bursts
system.physmem.perBankRdBursts::15              82087                       # Per bank write bursts
system.physmem.perBankWrBursts::0              134695                       # Per bank write bursts
system.physmem.perBankWrBursts::1              125793                       # Per bank write bursts
system.physmem.perBankWrBursts::2              142260                       # Per bank write bursts
system.physmem.perBankWrBursts::3              126417                       # Per bank write bursts
system.physmem.perBankWrBursts::4              155026                       # Per bank write bursts
system.physmem.perBankWrBursts::5              152020                       # Per bank write bursts
system.physmem.perBankWrBursts::6              183109                       # Per bank write bursts
system.physmem.perBankWrBursts::7              140837                       # Per bank write bursts
system.physmem.perBankWrBursts::8              128222                       # Per bank write bursts
system.physmem.perBankWrBursts::9              141420                       # Per bank write bursts
system.physmem.perBankWrBursts::10             135722                       # Per bank write bursts
system.physmem.perBankWrBursts::11             146309                       # Per bank write bursts
system.physmem.perBankWrBursts::12             139215                       # Per bank write bursts
system.physmem.perBankWrBursts::13             127398                       # Per bank write bursts
system.physmem.perBankWrBursts::14             153454                       # Per bank write bursts
system.physmem.perBankWrBursts::15             144523                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    47438271681000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
system.physmem.readPktSize::3                      37                       # Read request sizes (log2)
system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1326654                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2601                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                2363586                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    850336                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    158236                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     84690                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     68857                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     51684                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     44428                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     38277                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     32108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     25287                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1980                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1021                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      801                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      610                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      432                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      239                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      120                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    89049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    97576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   118285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   123036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   124126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   148935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   133751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   128713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   131381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   133864                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   133437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   132728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   131540                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   133641                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   128245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                   124149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                   123411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                   120132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     4141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1716                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      855                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      390                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      178                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       831449                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      280.321107                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     152.348246                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     337.173071                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         412387     49.60%     49.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       160013     19.25%     68.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        57469      6.91%     75.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        29190      3.51%     79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        24961      3.00%     82.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        16130      1.94%     84.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        12424      1.49%     85.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        12438      1.50%     87.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151       106437     12.80%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         831449                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples        117879                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        11.582360                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      193.016425                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047         117876    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-22527            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-26623            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-59391            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total          117879                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples        117879                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.311497                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.988433                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        4.874271                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           75351     63.92%     63.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23           36700     31.13%     95.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            3007      2.55%     97.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             902      0.77%     98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             786      0.67%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             199      0.17%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             149      0.13%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              77      0.07%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              81      0.07%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              16      0.01%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              14      0.01%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.01%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             396      0.34%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              29      0.02%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              39      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              22      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              47      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99              10      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             6      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            15      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             4      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total          117879                       # Writes before turning the bus around for reads
system.physmem.totQLat                    39355914512                       # Total ticks spent queuing
system.physmem.totMemAccLat               64956395762                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6826795000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28824.59                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47574.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.84                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           3.07                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.79                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        3.19                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.35                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.79                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1064531                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1745793                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   77.97                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.69                       # Row buffer hit rate for writes
system.physmem.avgGap                     12697338.30                       # Average gap between requests
system.physmem.pageHitRate                      77.17                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     45390521349500                       # Time in different power states
system.physmem.memoryStateTime::REF      1584068200000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      463683887500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                3148966800                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                3136780080                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1718186250                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1711536750                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               5202085200                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               5447566800                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              7517817360                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              7233384240                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3098437399200                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3098437399200                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1260445205745                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1262996298315                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          27357310364250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          27355072563750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            31733780024805                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            31734035529135                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.948883                       # Core power per rank (mW)
system.physmem.averagePower::1             668.954269                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq             1262651                       # Transaction distribution
system.membus.trans_dist::ReadResp            1262651                       # Transaction distribution
system.membus.trans_dist::WriteReq              38160                       # Transaction distribution
system.membus.trans_dist::WriteResp             38160                       # Transaction distribution
system.membus.trans_dist::Writeback            693385                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq      1670201                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp      1670201                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           307572                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         298715                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           95343                       # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
system.membus.trans_dist::ReadExReq            162530                       # Transaction distribution
system.membus.trans_dist::ReadExResp           146943                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123084                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24300                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      7267614                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      7415090                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229896                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       229896                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                7644986                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156191                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        48600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    229061364                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    229266359                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7307968                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7307968                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               236574327                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           528061                       # Total snoops (count)
system.membus.snoop_fanout::samples           4313648                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 4313648    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4313648                       # Request fanout histogram
system.membus.reqLayer0.occupancy           100869991                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               55000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            21144997                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         23127462719                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy        14206266380                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          187834022                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                  1088949                       # number of replacements
system.l2c.tags.tagsinuse                64239.358232                       # Cycle average of tags in use
system.l2c.tags.total_refs                    6591556                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1149786                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     5.732855                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks    9309.879147                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    38.225449                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    41.200627                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst      627.976202                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     3676.898634                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16318.952466                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   311.035795                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   436.956601                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      693.970644                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9626.822610                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 23157.440058                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.142057                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000583                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000629                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.009582                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.056105                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.249007                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004746                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006667                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.010589                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.146894                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.353354                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.980215                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        32295                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          314                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        28228                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0           21                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1          137                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2          836                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3         1678                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4        29623                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2           11                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3           31                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          268                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1122                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4068                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        22816                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.492783                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.004791                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.430725                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 79894517                       # Number of tag accesses
system.l2c.tags.data_accesses                79894517                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         5969                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         3906                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst             130836                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data             569496                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher      1489116                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         6350                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker         4630                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst             144360                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             647503                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher      1630669                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                4632835                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         1982686                       # number of Writeback hits
system.l2c.Writeback_hits::total              1982686                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data           22177                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           28734                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               50911                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          6966                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          8106                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             15072                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            48437                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            51237                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                99674                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker          5969                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          3906                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              130836                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              617933                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher      1489116                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          6350                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4630                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              144360                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              698740                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher      1630669                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 4732509                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         5969                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         3906                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             130836                       # number of overall hits
system.l2c.overall_hits::cpu0.data             617933                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher      1489116                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         6350                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4630                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             144360                       # number of overall hits
system.l2c.overall_hits::cpu1.data             698740                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher      1630669                       # number of overall hits
system.l2c.overall_hits::total                4732509                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         3468                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         6343                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst             8294                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           128231                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher       425212                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         4359                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         6722                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             8893                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           146336                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher       434855                       # number of ReadReq misses
system.l2c.ReadReq_misses::total              1172713                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         33912                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         36287                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             70199                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data        10020                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data        11790                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total           21810                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          77130                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          73144                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             150274                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3468                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         6343                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              8294                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            205361                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       425212                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         4359                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         6722                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              8893                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            219480                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       434855                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1322987                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3468                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         6343                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             8294                       # number of overall misses
system.l2c.overall_misses::cpu0.data           205361                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       425212                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         4359                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         6722                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             8893                       # number of overall misses
system.l2c.overall_misses::cpu1.data           219480                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       434855                       # number of overall misses
system.l2c.overall_misses::total              1322987                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    277093747                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    508086991                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst    728511746                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  10412911614                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher  44677211677                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    344069994                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    530104242                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    794513741                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  11896672640                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher  46121255625                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total   116290432017                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    136371763                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    151914842                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    288286605                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data     46986513                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data     56444140                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total    103430653                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data   5663882239                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5345531625                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  11009413864                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    277093747                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    508086991                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst    728511746                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  16076793853                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  44677211677                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    344069994                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    530104242                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    794513741                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  17242204265                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  46121255625                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    127299845881                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    277093747                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    508086991                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst    728511746                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  16076793853                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  44677211677                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    344069994                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    530104242                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    794513741                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  17242204265                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  46121255625                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   127299845881                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         9437                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker        10249                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst         139130                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data         697727                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher      1914328                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        10709                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        11352                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst         153253                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data         793839                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher      2065524                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            5805548                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1982686                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1982686                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        56089                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        65021                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          121110                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        16986                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        19896                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         36882                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       125567                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       124381                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           249948                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         9437                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker        10249                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          139130                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          823294                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher      1914328                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        10709                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        11352                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          153253                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          918220                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher      2065524                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             6055496                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         9437                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker        10249                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         139130                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         823294                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher      1914328                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        10709                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        11352                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         153253                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         918220                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher      2065524                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            6055496                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.367490                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.618890                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.059613                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.183784                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher     0.222121                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.407041                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.592142                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.058028                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.184340                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher     0.210530                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.201999                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.604611                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.558081                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.579630                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.589898                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.592581                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.591345                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.614254                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.588064                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.601221                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.367490                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.618890                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.059613                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.249438                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.222121                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.407041                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.592142                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.058028                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.239028                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.210530                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.218477                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.367490                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.618890                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.059613                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.249438                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.222121                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.407041                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.592142                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.058028                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.239028                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.210530                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.218477                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79900.157728                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80102.000788                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87835.995418                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 81204.323557                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78933.240193                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78861.089259                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 89341.475430                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 81296.964793                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 99163.590765                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  4021.342386                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4186.481164                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  4106.705295                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4689.272754                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4787.458863                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total  4742.349977                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73432.934513                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73082.298275                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73262.266686                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79900.157728                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80102.000788                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 87835.995418                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 78285.525747                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78933.240193                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78861.089259                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 89341.475430                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78559.341466                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 96221.539502                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79900.157728                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80102.000788                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 87835.995418                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 78285.525747                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 105070.439397                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78933.240193                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78861.089259                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 89341.475430                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78559.341466                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106061.228743                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 96221.539502                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              1844                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       53                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs     34.792453                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              693385                       # number of writebacks
system.l2c.writebacks::total                   693385                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst            23                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data            14                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher          264                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data            17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher          129                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               458                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher          264                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher          129                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                458                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher          264                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher          129                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               458                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         3468                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         6343                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst         8271                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       128217                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher       424948                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         4359                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         6722                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         8882                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       146319                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher       434726                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total         1172255                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        33912                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        36287                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        70199                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10020                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11790                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total        21810                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        77130                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        73144                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        150274                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3468                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         6343                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst         8271                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       205347                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       424948                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         4359                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         6722                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         8882                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       219463                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       434726                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1322529                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3468                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         6343                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst         8271                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       205347                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       424948                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         4359                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         6722                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         8882                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       219463                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       434726                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1322529                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    234005247                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    429405991                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    623644746                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8803657420                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher  39426586681                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    289785494                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    446560742                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    682991749                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data  10059247700                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher  40752439135                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 101748324905                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data  17202577789                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data  14155732856                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  31358310645                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    344397419                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    367876069                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    712273488                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    102095388                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    120655634                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total    222751022                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4691101701                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4422988801                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   9114090502                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    234005247                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    429405991                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst    623644746                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  13494759121                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  39426586681                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    289785494                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    446560742                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    682991749                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  14482236501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  40752439135                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 110862415407                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    234005247                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    429405991                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst    623644746                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  13494759121                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  39426586681                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    289785494                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    446560742                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    682991749                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  14482236501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  40752439135                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 110862415407                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1998253750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5835000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3361097750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7611383750                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2007075001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3246096000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5253171001                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2246197250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4005328751                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5835000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6607193750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12864554751                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.367490                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.618890                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.059448                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.183764                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.221983                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.407041                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.592142                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.057956                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.184318                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.210468                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.201920                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.604611                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.558081                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.579630                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.589898                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.592581                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.591345                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.614254                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.588064                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.601221                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.367490                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.618890                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.059448                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.249421                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.221983                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.407041                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.592142                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.057956                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.239009                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.210468                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.218401                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.367490                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.618890                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.059448                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.249421                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.221983                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.407041                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.592142                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.057956                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.239009                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.210468                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.218401                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 75401.371781                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68662.169759                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76896.166291                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68748.745549                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 86797.091849                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10155.620990                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10137.957643                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10146.490520                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10189.160479                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10233.726378                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10213.251811                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60820.714391                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60469.605176                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 60649.816349                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75401.371781                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65716.855474                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76896.166291                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65989.421912                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 83826.075199                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75401.371781                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65716.855474                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76896.166291                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65989.421912                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 83826.075199                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq            6645186                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           6637629                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38160                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38160                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          1982686                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq      1670210                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp      1563473                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          355152                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        313787                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         668939                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          102                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           297718                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          297718                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9432330                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      9652916                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              19085246                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    302653655                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    312342176                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              614995831                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1425200                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         11183456                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.010347                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.101194                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               11067738     98.97%     98.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 115718      1.03%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           11183456                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        19814172733                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          6396000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       15605521398                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       16621378743                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40465                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40465                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136732                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136786                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           54                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48150                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123084                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231338                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231338                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354502                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48170                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156191                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339368                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339368                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7497645                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36603000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21986000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           981958721                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93029000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179341978                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    81279666                       # DTB read hits
system.cpu0.dtb.read_misses                     78948                       # DTB read misses
system.cpu0.dtb.write_hits                   73742535                       # DTB write hits
system.cpu0.dtb.write_misses                    27290                       # DTB write misses
system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              41415                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1036                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   31886                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3595                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     8523                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                81358614                       # DTB read accesses
system.cpu0.dtb.write_accesses               73769825                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        155022201                       # DTB hits
system.cpu0.dtb.misses                         106238                       # DTB misses
system.cpu0.dtb.accesses                    155128439                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   432012599                       # ITB inst hits
system.cpu0.itb.inst_misses                     54786                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              41415                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1036                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   22623                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               432067385                       # ITB inst accesses
system.cpu0.itb.hits                        432012599                       # DTB hits
system.cpu0.itb.misses                          54786                       # DTB misses
system.cpu0.itb.accesses                    432067385                       # DTB accesses
system.cpu0.numCycles                     94876549324                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  431769250                       # Number of instructions committed
system.cpu0.committedOps                    507110651                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            465722099                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                423380                       # Number of float alu accesses
system.cpu0.num_func_calls                   25579239                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     65525116                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   465722099                       # number of integer instructions
system.cpu0.num_fp_insts                       423380                       # number of float instructions
system.cpu0.num_int_register_reads          674979358                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         369311745                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              705560                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             308536                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           112703400                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          112387692                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    155012297                       # number of memory refs
system.cpu0.num_load_insts                   81273219                       # Number of load instructions
system.cpu0.num_store_insts                  73739078                       # Number of store instructions
system.cpu0.num_idle_cycles              93821929037.552032                       # Number of idle cycles
system.cpu0.num_busy_cycles              1054620286.447978                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.011116                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.988884                       # Percentage of idle cycles
system.cpu0.Branches                         96363585                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                351187949     69.21%     69.21% # Class of executed instruction
system.cpu0.op_class::IntMult                 1094457      0.22%     69.43% # Class of executed instruction
system.cpu0.op_class::IntDiv                    58568      0.01%     69.44% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.44% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             43852      0.01%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::MemRead                81273219     16.02%     85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite               73739078     14.53%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 507397124                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5117                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements          4835795                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.921057                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          427176292                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          4836307                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.326959                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      24248022750                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.921057                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        868861505                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       868861505                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    427176292                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      427176292                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    427176292                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       427176292                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    427176292                       # number of overall hits
system.cpu0.icache.overall_hits::total      427176292                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      4836307                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      4836307                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      4836307                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       4836307                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      4836307                       # number of overall misses
system.cpu0.icache.overall_misses::total      4836307                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  42021880066                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  42021880066                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  42021880066                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  42021880066                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  42021880066                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  42021880066                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    432012599                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    432012599                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    432012599                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    432012599                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    432012599                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    432012599                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011195                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011195                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011195                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011195                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011195                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011195                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst  8688.836351                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8688.836351                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst  8688.836351                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8688.836351                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst  8688.836351                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8688.836351                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4836307                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      4836307                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      4836307                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      4836307                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      4836307                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      4836307                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  34764760966                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  34764760966                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  34764760966                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  34764760966                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  34764760966                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  34764760966                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3405609750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   3405609750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3405609750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011195                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011195                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011195                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.011195                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011195                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.011195                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  7188.286634                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  7188.286634                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  7188.286634                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total  7188.286634                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  7188.286634                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total  7188.286634                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified     44883381                       # number of hwpf identified
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       769766                       # number of hwpf that were already in mshr
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     41733922                       # number of hwpf that were already in the cache
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         7731                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          460                       # number of hwpf removed because MSHR allocated
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued      2371502                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page      3699891                       # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2cache.tags.replacements         2933552                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16178.968525                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          10401290                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2949711                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.526206                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle     20647851500                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks  3715.452521                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    41.338628                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    40.195819                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst   822.456727                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3056.932991                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  8502.591837                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.226773                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002523                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002453                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.050199                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.186580                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.518957                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.987486                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022         8877                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           49                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024         7233                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0           49                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          502                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2         2719                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3         3687                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4         1920                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            8                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           22                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          393                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         2913                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         2975                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4          925                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.541809                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002991                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.441467                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       228304892                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      228304892                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       221810                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       122090                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst      4672690                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data      2607787                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total       7624377                       # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks      2894821                       # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total      2894821                       # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data        81724                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total        81724                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data        31053                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total        31053                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       866415                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       866415                       # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       221810                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       122090                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4672690                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3474202                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8490792                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       221810                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       122090                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4672690                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3474202                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8490792                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12355                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10686                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst       163617                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data       944935                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total      1131593                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       105877                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       105877                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       154791                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       154791                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            6                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       220288                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       220288                       # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        12355                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10686                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       163617                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1165223                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      1351881                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        12355                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10686                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       163617                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1165223                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      1351881                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    518388959                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    691109452                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst   4288633088                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data  30316279776                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total  35814411275                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   2067273148                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total   2067273148                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   3132681305                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   3132681305                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1841998                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1841998                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  10252738120                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  10252738120                       # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    518388959                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    691109452                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4288633088                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  40569017896                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  46067149395                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    518388959                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    691109452                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4288633088                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  40569017896                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  46067149395                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       234165                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       132776                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      4836307                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data      3552722                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total      8755970                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks      2894821                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total      2894821                       # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       187601                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       187601                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       185844                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       185844                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1086703                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1086703                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       234165                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       132776                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      4836307                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      4639425                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      9842673                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       234165                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       132776                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      4836307                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      4639425                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      9842673                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.052762                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.080481                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.033831                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.265975                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.129237                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.564373                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.564373                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.832908                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.832908                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.202712                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.202712                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.052762                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.080481                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.033831                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.251157                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.137349                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.052762                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.080481                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.033831                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.251157                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.137349                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41957.827519                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 64674.288976                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26211.415000                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32082.926102                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31649.551804                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 19525.233507                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19525.233507                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20238.135970                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20238.135970                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 306999.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 306999.666667                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46542.426823                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46542.426823                       # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41957.827519                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 64674.288976                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 26211.415000                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34816.526876                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 34076.334674                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41957.827519                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 64674.288976                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 26211.415000                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34816.526876                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 34076.334674                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         9451                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs             232                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    40.737069                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks       969387                       # number of writebacks
system.cpu0.l2cache.writebacks::total          969387                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst        24596                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data         5208                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total        29804                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5052                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total         5052                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst        24596                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        10260                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        34856                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst        24596                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        10260                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        34856                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12355                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        10686                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst       139021                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data       939727                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total      1101789                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher      2371413                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total      2371413                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       105877                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       105877                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       154791                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       154791                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       215236                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       215236                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12355                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        10686                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       139021                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1154963                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1317025                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        12355                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        10686                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       139021                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1154963                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher      2371413                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      3688438                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    431221053                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    615215054                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst   2925869007                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data  23536761675                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total  27509066789                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  70751604946                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  70751604946                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  31819773244                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total  31819773244                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1812194258                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1812194258                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   2134733797                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   2134733797                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1512998                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1512998                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   8195268769                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   8195268769                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    431221053                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    615215054                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   2925869007                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  31732030444                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  35704335558                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    431221053                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    615215054                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   2925869007                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  31732030444                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  70751604946                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 106455940504                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2263304784                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   5325169534                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   2282603541                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2282603541                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   3061864750                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   4545908325                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   7607773075                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.052762                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.080481                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst     0.028745                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data     0.264509                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.125833                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.564373                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.564373                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.832908                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.832908                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.198063                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.198063                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.052762                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.080481                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.028745                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.248945                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.133808                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.052762                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.080481                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.028745                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.248945                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.374739                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 21046.237669                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25046.382274                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24967.636080                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 29835.210040                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17116.033303                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17116.033303                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13791.071813                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13791.071813                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 252166.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 252166.333333                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38075.734399                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38075.734399                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21046.237669                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27474.499568                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27109.838885                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21046.237669                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27474.499568                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28862.065867                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements          5282593                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          478.557100                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          149517101                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          5283105                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.300990                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3644536500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   478.557100                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.934682                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.934682                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          411                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        315346998                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       315346998                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     75666916                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       75666916                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     69634196                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      69634196                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       181888                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       181888                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       858515                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       858515                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1792597                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1792597                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1751129                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1751129                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    145301112                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       145301112                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    145483000                       # number of overall hits
system.cpu0.dcache.overall_hits::total      145483000                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2868190                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      2868190                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1290634                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1290634                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       609921                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       609921                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       145533                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       145533                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       185941                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       185941                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4158824                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       4158824                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4768745                       # number of overall misses
system.cpu0.dcache.overall_misses::total      4768745                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41686378389                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  41686378389                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  22767469365                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  22767469365                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2114986821                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   2114986821                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   3970270831                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   3970270831                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1983000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1983000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  64453847754                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  64453847754                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  64453847754                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  64453847754                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     78535106                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     78535106                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     70924830                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     70924830                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       791809                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       791809                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       858515                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total       858515                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1938130                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      1938130                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1937070                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      1937070                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    149459936                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    149459936                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    150251745                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    150251745                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036521                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.036521                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018197                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018197                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.770288                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.770288                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075089                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.075089                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095991                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095991                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027826                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.027826                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.031738                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.031738                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14534.036584                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14534.036584                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17640.531216                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 17640.531216                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14532.695822                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14532.695822                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21352.315148                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21352.315148                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15498.094595                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15498.094595                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13515.893124                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13515.893124                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                 858515                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      2894821                       # number of writebacks
system.cpu0.dcache.writebacks::total          2894821                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        28163                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        28163                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21327                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21327                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41518                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41518                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        49490                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        49490                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        49490                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        49490                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2840027                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2840027                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1269307                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1269307                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       608681                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       608681                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       104015                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       104015                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       185850                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       185850                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4109334                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4109334                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4718015                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4718015                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  34673571058                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  34673571058                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  19854321886                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  19854321886                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13611528726                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13611528726                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  38259906745                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  38259906745                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1241876461                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1241876461                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   3588911169                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   3588911169                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1889000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1889000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  54527892944                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  54527892944                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  68139421670                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  68139421670                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2380477468                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2380477468                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2403593708                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2403593708                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4784071176                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4784071176                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036163                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036163                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017897                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017897                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.768722                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.768722                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.053668                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.053668                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095944                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095944                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027495                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.027495                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031401                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031401                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12208.887823                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12208.887823                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15641.859602                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15641.859602                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22362.335486                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22362.335486                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11939.397789                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11939.397789                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19310.794560                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19310.794560                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13269.277441                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13269.277441                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14442.391911                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14442.391911                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq      12330313                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      9009509                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        16126                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        16126                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback      2894821                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      3465295                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq      1670210                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp       858515                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       371533                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       344881                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       439023                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           61                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1234519                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1094177                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      9758864                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     14862906                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       296442                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       542592                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         25460804                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    309696148                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    543504195                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1062208                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1873320                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         856135871                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    8448176                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples     22253887                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       5.367543                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.482136                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5          14074632     63.25%     63.25% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6           8179255     36.75%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      22253887                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   10836211781                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    180026995                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   7309068550                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   7654516797                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    164187799                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    308745047                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    85169560                       # DTB read hits
system.cpu1.dtb.read_misses                     81568                       # DTB read misses
system.cpu1.dtb.write_hits                   77252621                       # DTB write hits
system.cpu1.dtb.write_misses                    28177                       # DTB write misses
system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              41415                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1036                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   42405                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4822                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11145                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                85251128                       # DTB read accesses
system.cpu1.dtb.write_accesses               77280798                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        162422181                       # DTB hits
system.cpu1.dtb.misses                         109745                       # DTB misses
system.cpu1.dtb.accesses                    162531926                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                   451299133                       # ITB inst hits
system.cpu1.itb.inst_misses                     60868                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              41415                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1036                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   29689                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               451360001                       # ITB inst accesses
system.cpu1.itb.hits                        451299133                       # DTB hits
system.cpu1.itb.misses                          60868                       # DTB misses
system.cpu1.itb.accesses                    451360001                       # DTB accesses
system.cpu1.numCycles                     94876549324                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  450991688                       # Number of instructions committed
system.cpu1.committedOps                    531140635                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            488008709                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                470535                       # Number of float alu accesses
system.cpu1.num_func_calls                   27052635                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     68722135                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   488008709                       # number of integer instructions
system.cpu1.num_fp_insts                       470535                       # number of float instructions
system.cpu1.num_int_register_reads          711965253                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         387496587                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              748074                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             424948                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           118082190                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          117761356                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    162414438                       # number of memory refs
system.cpu1.num_load_insts                   85168501                       # Number of load instructions
system.cpu1.num_store_insts                  77245937                       # Number of store instructions
system.cpu1.num_idle_cycles              93789094629.720032                       # Number of idle cycles
system.cpu1.num_busy_cycles              1087454694.279977                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011462                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988538                       # Percentage of idle cycles
system.cpu1.Branches                        100614893                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                367777606     69.20%     69.20% # Class of executed instruction
system.cpu1.op_class::IntMult                 1128259      0.21%     69.42% # Class of executed instruction
system.cpu1.op_class::IntDiv                    59926      0.01%     69.43% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             67918      0.01%     69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.44% # Class of executed instruction
system.cpu1.op_class::MemRead                85168501     16.03%     85.47% # Class of executed instruction
system.cpu1.op_class::MemWrite               77245937     14.53%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 531448189                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13727                       # number of quiesce instructions executed
system.cpu1.icache.tags.replacements          5018265                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.292950                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          446280351                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5018777                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            88.922132                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8374030789000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.292950                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969322                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969322                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          272                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        907617048                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       907617048                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst    446280351                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      446280351                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    446280351                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       446280351                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    446280351                       # number of overall hits
system.cpu1.icache.overall_hits::total      446280351                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      5018782                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      5018782                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      5018782                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       5018782                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      5018782                       # number of overall misses
system.cpu1.icache.overall_misses::total      5018782                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  43828213410                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  43828213410                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  43828213410                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  43828213410                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  43828213410                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  43828213410                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    451299133                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    451299133                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    451299133                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    451299133                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    451299133                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    451299133                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011121                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.011121                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011121                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.011121                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011121                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.011121                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8732.838647                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total  8732.838647                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8732.838647                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total  8732.838647                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8732.838647                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total  8732.838647                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5018782                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5018782                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5018782                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5018782                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5018782                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5018782                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  36297023628                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  36297023628                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  36297023628                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  36297023628                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  36297023628                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  36297023628                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8745500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8745500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8745500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      8745500                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011121                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011121                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011121                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.011121                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011121                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.011121                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  7232.237548                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  7232.237548                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  7232.237548                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total  7232.237548                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  7232.237548                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total  7232.237548                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified     46849798                       # number of hwpf identified
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       849083                       # number of hwpf that were already in mshr
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     43478767                       # number of hwpf that were already in the cache
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher         8509                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit          498                       # number of hwpf removed because MSHR allocated
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued      2512941                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4003522                       # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2cache.tags.replacements         3186327                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13749.059276                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          10995274                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         3202540                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            3.433298                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle    10289671385000                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks  3719.678025                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    60.787845                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    70.255948                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst   738.115958                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data  2404.101650                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher  6756.119849                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.227031                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003710                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004288                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.045051                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.146735                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.412361                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.839176                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022         9826                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023          113                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024         6274                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0          142                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1         1008                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2         2026                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3         4347                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4         2303                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            5                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1           31                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           61                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          496                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         1278                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3095                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1333                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.599731                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006897                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.382935                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       238490090                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      238490090                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       228775                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       138969                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst      4837723                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data      2811594                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total       8017061                       # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks      3078590                       # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total      3078590                       # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data        84508                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total        84508                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data        36910                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total        36910                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       942789                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       942789                       # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       228775                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       138969                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4837723                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3754383                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8959850                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       228775                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       138969                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4837723                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3754383                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8959850                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12809                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        11666                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst       181059                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data      1016624                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total      1222158                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       110012                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       110012                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       159084                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       159084                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            8                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       227840                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       227840                       # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12809                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        11666                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       181059                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1244464                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1449998                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12809                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        11666                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       181059                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1244464                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1449998                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    589793966                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    732581953                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst   4736583796                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data  33373068876                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total  39432028591                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   2203650350                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total   2203650350                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   3257454308                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   3257454308                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2221500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2221500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  10235414817                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  10235414817                       # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    589793966                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    732581953                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst   4736583796                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  43608483693                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  49667443408                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    589793966                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    732581953                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst   4736583796                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  43608483693                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  49667443408                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       241584                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       150635                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst      5018782                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data      3828218                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total      9239219                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks      3078590                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total      3078590                       # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       194520                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       194520                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       195994                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       195994                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            8                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1170629                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1170629                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       241584                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       150635                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5018782                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4998847                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     10409848                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       241584                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       150635                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5018782                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4998847                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     10409848                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.053021                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.077445                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.036076                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.265561                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.132279                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.565556                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.565556                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.811678                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.811678                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.194630                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.194630                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.053021                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.077445                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.036076                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.248950                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.139291                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.053021                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.077445                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.036076                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.248950                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.139291                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 46045.278008                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62796.327190                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 26160.443811                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32827.347058                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32264.264188                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20030.999800                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20030.999800                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20476.316336                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20476.316336                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 277687.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 277687.500000                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44923.695650                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44923.695650                       # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 46045.278008                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62796.327190                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26160.443811                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35041.980879                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 34253.456493                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 46045.278008                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62796.327190                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26160.443811                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35041.980879                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 34253.456493                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs         7768                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs             221                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    35.149321                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks      1013300                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1013300                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst        27917                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data         1038                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total        28955                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         6115                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total         6115                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst        27917                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7153                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        35070                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst        27917                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7153                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        35070                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12809                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker        11666                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst       153142                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data      1015586                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total      1193203                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher      2512812                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total      2512812                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       110012                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       110012                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       159084                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       159084                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            8                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       221725                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       221725                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        12809                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker        11666                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       153142                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1237311                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1414928                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        12809                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker        11666                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       153142                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1237311                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher      2512812                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      3927740                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    499166550                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    649598551                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst   3217080793                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data  26145933834                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total  30511779728                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  74093026830                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  74093026830                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  26166697651                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total  26166697651                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   1898740270                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   1898740270                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2221301592                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2221301592                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1836500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1836500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8021601600                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8021601600                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    499166550                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    649598551                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst   3217080793                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34167535434                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  38533381328                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    499166550                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    649598551                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst   3217080793                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34167535434                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  74093026830                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 112626408158                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7884500                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3785923263                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3793807763                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3621697529                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3621697529                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      7884500                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7407620792                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7415505292                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.053021                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.077445                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst     0.030514                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data     0.265289                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.129145                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.565556                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.565556                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.811678                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.811678                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.189407                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.189407                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.053021                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.077445                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.030514                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.247519                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.135922                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.053021                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.077445                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.030514                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.247519                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.377310                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21007.174994                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25744.677294                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25571.323344                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29486.100365                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17259.392339                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17259.392339                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13963.073546                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13963.073546                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 229562.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 229562.500000                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36178.155824                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36178.155824                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21007.174994                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27614.347108                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27233.457341                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21007.174994                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27614.347108                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28674.608848                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements          5412769                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          455.628997                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          156797756                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5413278                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.965399                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8374220312000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   455.628997                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.889900                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.889900                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           81                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        330228848                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       330228848                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     79329783                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       79329783                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     73242746                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      73242746                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       190572                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       190572                       # number of SoftPFReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data       704958                       # number of WriteInvalidateReq hits
system.cpu1.dcache.WriteInvalidateReq_hits::total       704958                       # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1728485                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1728485                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1710118                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1710118                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    152572529                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       152572529                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    152763101                       # number of overall hits
system.cpu1.dcache.overall_hits::total      152763101                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3054941                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3054941                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1365411                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1365411                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       663261                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       663261                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       178994                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       178994                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       196091                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       196091                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      4420352                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       4420352                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      5083613                       # number of overall misses
system.cpu1.dcache.overall_misses::total      5083613                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  45633904603                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  45633904603                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  23251947701                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total  23251947701                       # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2574333319                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   2574333319                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4154245626                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4154245626                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      2386500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      2386500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data  68885852304                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total  68885852304                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data  68885852304                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total  68885852304                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     82384724                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     82384724                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     74608157                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     74608157                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       853833                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       853833                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data       704958                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.WriteInvalidateReq_accesses::total       704958                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1907479                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      1907479                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1906209                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      1906209                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    156992881                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    156992881                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    157846714                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    157846714                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.037081                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.037081                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018301                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018301                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.776804                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.776804                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.093838                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.093838                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.102870                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.102870                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.028156                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.028156                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.032206                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.032206                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14937.736802                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14937.736802                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17029.266427                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17029.266427                       # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14382.232471                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14382.232471                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21185.294715                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21185.294715                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15583.793396                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 15583.793396                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13550.569704                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 13550.569704                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes                 704958                       # number of fast writes performed
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks      3078594                       # number of writebacks
system.cpu1.dcache.writebacks::total          3078594                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        23839                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total        23839                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          436                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total          436                       # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        45139                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total        45139                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data        24275                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total        24275                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data        24275                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total        24275                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3031102                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3031102                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1364975                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1364975                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       663261                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       663261                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       133855                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       133855                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       196002                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       196002                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4396077                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4396077                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5059338                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5059338                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38375786357                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38375786357                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  20437608309                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  20437608309                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14184435008                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14184435008                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  31455228300                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total  31455228300                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1522508206                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1522508206                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   3750879374                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   3750879374                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2276500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2276500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  58813394666                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  58813394666                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  72997829674                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  72997829674                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3974280487                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3974280487                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3786981721                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3786981721                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7761262208                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7761262208                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036792                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036792                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018295                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018295                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.776804                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.776804                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.070174                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.070174                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.102823                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.102823                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.028002                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.028002                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.032052                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.032052                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12660.671385                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12660.671385                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14972.881048                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14972.881048                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21385.902394                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21385.902394                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11374.309559                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11374.309559                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19136.944388                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19136.944388                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13378.608852                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13378.608852                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14428.336212                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14428.336212                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq      12531191                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9460246                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        22034                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        22034                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback      3078590                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq      3649719                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq      1670210                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp       704958                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       365743                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       350744                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       452026                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           55                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          102                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1320531                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1177447                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     10037784                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15516501                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       332477                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       559655                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         26446417                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    321202488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    568398888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1205080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1932672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total         892739128                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    8517318                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples     22943145                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       5.359651                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.479898                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4                 0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5          14691626     64.03%     64.03% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6           8251519     35.97%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      22943145                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   11163844442                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    175587993                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   7529809391                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   8141370258                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    182479297                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    318532791                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115665                       # number of replacements
system.iocache.tags.tagsinuse               11.304646                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115681                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9130394779000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.406620                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.898026                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.462914                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.243627                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.706540                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041810                       # Number of tag accesses
system.iocache.tags.data_accesses             1041810                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide       106728                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total       106728                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8941                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8978                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           54                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           54                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8941                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8981                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8941                       # number of overall misses
system.iocache.overall_misses::total             8981                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5707000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1994628595                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   2000335595                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       357000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       357000                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      6064000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1994628595                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   2000692595                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      6064000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1994628595                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   2000692595                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8941                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8978                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106782                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106782                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8941                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8981                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8941                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8981                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000506                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000506                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 223087.864333                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 222804.142905                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       119000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       119000                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 223087.864333                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 222769.468322                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       151600                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 223087.864333                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 222769.468322                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         55195                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 5490                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.053734                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                     106728                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8941                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8978                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8941                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8981                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8941                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8981                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3783000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1529539613                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1533322613                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   6584739086                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6584739086                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3984000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1529539613                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1533523613                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3984000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1529539613                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1533523613                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171070.306789                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 170786.657719                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 171070.306789                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 170751.988977                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        99600                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 171070.306789                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 170751.988977                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------