path: root/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.821157                       # Number of seconds simulated
sim_ticks                                51821157171000                       # Number of ticks simulated
final_tick                               51821157171000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 734878                       # Simulator instruction rate (inst/s)
host_op_rate                                   863519                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            42416153440                       # Simulator tick rate (ticks/s)
host_mem_usage                                 712380                       # Number of bytes of host memory used
host_seconds                                  1221.73                       # Real time elapsed on the host
sim_insts                                   897823750                       # Number of instructions simulated
sim_ops                                    1054987960                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       267456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       270528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5250612                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          52674824                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        383808                       # Number of bytes read from this memory
system.physmem.bytes_read::total             58847228                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5250612                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5250612                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     79637568                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          79658148                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         4179                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         4227                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             122448                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             823057                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           5997                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                959908                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1244337                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1246910                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           5161                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           5220                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               101322                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1016473                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7406                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1135583                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          101322                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             101322                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1536777                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1537174                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1536777                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          5161                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          5220                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              101322                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1016870                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7406                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2672757                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        959908                       # Number of read requests accepted
system.physmem.writeReqs                      1865455                       # Number of write requests accepted
system.physmem.readBursts                      959908                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1865455                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 61382336                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     51776                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 118954432                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  58847228                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              119245028                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      809                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    6774                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          36275                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               56974                       # Per bank write bursts
system.physmem.perBankRdBursts::1               60608                       # Per bank write bursts
system.physmem.perBankRdBursts::2               56247                       # Per bank write bursts
system.physmem.perBankRdBursts::3               58787                       # Per bank write bursts
system.physmem.perBankRdBursts::4               55621                       # Per bank write bursts
system.physmem.perBankRdBursts::5               61105                       # Per bank write bursts
system.physmem.perBankRdBursts::6               53454                       # Per bank write bursts
system.physmem.perBankRdBursts::7               55202                       # Per bank write bursts
system.physmem.perBankRdBursts::8               54549                       # Per bank write bursts
system.physmem.perBankRdBursts::9              101006                       # Per bank write bursts
system.physmem.perBankRdBursts::10              57136                       # Per bank write bursts
system.physmem.perBankRdBursts::11              59250                       # Per bank write bursts
system.physmem.perBankRdBursts::12              54470                       # Per bank write bursts
system.physmem.perBankRdBursts::13              61564                       # Per bank write bursts
system.physmem.perBankRdBursts::14              57688                       # Per bank write bursts
system.physmem.perBankRdBursts::15              55438                       # Per bank write bursts
system.physmem.perBankWrBursts::0              113578                       # Per bank write bursts
system.physmem.perBankWrBursts::1              118177                       # Per bank write bursts
system.physmem.perBankWrBursts::2              119014                       # Per bank write bursts
system.physmem.perBankWrBursts::3              122732                       # Per bank write bursts
system.physmem.perBankWrBursts::4              115108                       # Per bank write bursts
system.physmem.perBankWrBursts::5              118421                       # Per bank write bursts
system.physmem.perBankWrBursts::6              110433                       # Per bank write bursts
system.physmem.perBankWrBursts::7              110649                       # Per bank write bursts
system.physmem.perBankWrBursts::8              111009                       # Per bank write bursts
system.physmem.perBankWrBursts::9              115530                       # Per bank write bursts
system.physmem.perBankWrBursts::10             116272                       # Per bank write bursts
system.physmem.perBankWrBursts::11             116171                       # Per bank write bursts
system.physmem.perBankWrBursts::12             116950                       # Per bank write bursts
system.physmem.perBankWrBursts::13             121923                       # Per bank write bursts
system.physmem.perBankWrBursts::14             117171                       # Per bank write bursts
system.physmem.perBankWrBursts::15             115525                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
system.physmem.totGap                    51821154615000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  916792                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1862882                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    923488                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     30071                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2080                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       548                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       693                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       382                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       338                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       197                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       132                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      103                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       84                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       78                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       45                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    58678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    72148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                   102041                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   104846                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   108153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   122813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   127000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                   113028                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   114051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                   111714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                   109570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                   106267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                   103051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                   101586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    96822                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    95736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    95578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    94283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2079                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1788                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      637                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      502                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       618930                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      291.368084                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     166.608476                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.498173                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         256436     41.43%     41.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       152224     24.59%     66.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        51996      8.40%     74.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        28892      4.67%     79.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        20098      3.25%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13547      2.19%     84.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10018      1.62%     86.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9306      1.50%     87.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        76413     12.35%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         618930                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         92468                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        10.372118                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      105.903641                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          92466    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           92468                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         92468                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.100608                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.118632                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       10.444453                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           55053     59.54%     59.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23           30512     33.00%     92.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            2134      2.31%     94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            1149      1.24%     96.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             862      0.93%     97.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             455      0.49%     97.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             271      0.29%     97.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             154      0.17%     97.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             523      0.57%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              85      0.09%     98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              63      0.07%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              90      0.10%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             138      0.15%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              53      0.06%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              45      0.05%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              77      0.08%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             126      0.14%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              47      0.05%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91              24      0.03%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              42      0.05%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             157      0.17%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             6      0.01%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107            21      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            16      0.02%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            59      0.06%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             9      0.01%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            28      0.03%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127            35      0.04%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131           128      0.14%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135            15      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             6      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            16      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151            15      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             7      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163            10      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             3      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             5      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             4      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           92468                       # Writes before turning the bus around for reads
system.physmem.totQLat                    12424177254                       # Total ticks spent queuing
system.physmem.totMemAccLat               30407283504                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4795495000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12954.01                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31704.01                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.18                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.30                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.14                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.30                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.29                       # Average write queue length when enqueuing
system.physmem.readRowHits                     722238                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1476593                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.30                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.44                       # Row buffer hit rate for writes
system.physmem.avgGap                     18341414.75                       # Average gap between requests
system.physmem.pageHitRate                      78.03                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2336584320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1274922000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3572345400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               6014165760                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3384705823200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1308692927565                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29944715868000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34651312636245                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.671195                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49815023694250                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730422200000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    275710901250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2342526480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1278164250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3908587800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               6029970480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3384705823200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1310912306640                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29942769044250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34651946423100                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.683425                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49811721549250                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730422200000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    279009798250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    215397                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                215397                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16603                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       166513                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       215383                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean     0.157858                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev    54.935133                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047       215381    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::22528-24575            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       215383                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       183130                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767       181175     98.93%     98.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535            4      0.00%     98.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-98303         1496      0.82%     99.75% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-131071          183      0.10%     99.85% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839           74      0.04%     99.89% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::163840-196607           58      0.03%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-229375           49      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::229376-262143           36      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911           18      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::294912-327679           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-360447            8      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::360448-393215           11      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       183130                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples    800972760                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     2.488036                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0     -1191876296   -148.80%   -148.80% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1      1992849056    248.80%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total    800972760                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        166514     90.93%     90.93% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         16603      9.07%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       183117                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       215397                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       215397                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       183117                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       183117                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       398514                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    168647599                       # DTB read hits
system.cpu.dtb.read_misses                     158984                       # DTB read misses
system.cpu.dtb.write_hits                   153347297                       # DTB write hits
system.cpu.dtb.write_misses                     56413                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               43021                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    74349                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   8039                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     19949                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                168806583                       # DTB read accesses
system.cpu.dtb.write_accesses               153403710                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         321994896                       # DTB hits
system.cpu.dtb.misses                          215397                       # DTB misses
system.cpu.dtb.accesses                     322210293                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    123370                       # Table walker walks requested
system.cpu.itb.walker.walksLong                123370                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1120                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       111048                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       123370                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          123370    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       123370                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       112168                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 24898.509379                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       109848     97.93%     97.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         2031      1.81%     99.74% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607          132      0.12%     99.86% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143          101      0.09%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           23      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       112168                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples  -1257598296                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     -1257598296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total  -1257598296                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        111048     99.00%     99.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1120      1.00%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       112168                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       123370                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       123370                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       112168                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       112168                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       235538                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    898375907                       # ITB inst hits
system.cpu.itb.inst_misses                     123370                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               43021                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1067                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    52826                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                898499277                       # ITB inst accesses
system.cpu.itb.hits                         898375907                       # DTB hits
system.cpu.itb.misses                          123370                       # DTB misses
system.cpu.itb.accesses                     898499277                       # DTB accesses
system.cpu.numCycles                     103642314342                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   897823750                       # Number of instructions committed
system.cpu.committedOps                    1054987960                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             968534129                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 900653                       # Number of float alu accesses
system.cpu.num_func_calls                    53156799                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    137185420                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    968534129                       # number of integer instructions
system.cpu.num_fp_insts                        900653                       # number of float instructions
system.cpu.num_int_register_reads          1413400107                       # number of times the integer registers were read
system.cpu.num_int_register_writes          768429309                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              1451290                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              764324                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            236274909                       # number of times the CC registers were read
system.cpu.num_cc_register_writes           235673566                       # number of times the CC registers were written
system.cpu.num_mem_refs                     321978685                       # number of memory refs
system.cpu.num_load_insts                   168640749                       # Number of load instructions
system.cpu.num_store_insts                  153337936                       # Number of store instructions
system.cpu.num_idle_cycles               100474351324.032059                       # Number of idle cycles
system.cpu.num_busy_cycles               3167963017.967939                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.030566                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.969434                       # Percentage of idle cycles
system.cpu.Branches                         200551202                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 731167173     69.27%     69.27% # Class of executed instruction
system.cpu.op_class::IntMult                  2227672      0.21%     69.48% # Class of executed instruction
system.cpu.op_class::IntDiv                     99245      0.01%     69.49% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc             110423      0.01%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.50% # Class of executed instruction
system.cpu.op_class::MemRead                168640749     15.98%     85.47% # Class of executed instruction
system.cpu.op_class::MemWrite               153337936     14.53%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 1055583241                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16365                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements          10281150                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.969700                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           311526777                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs          10281662                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             30.299263                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        3093156250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.969700                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999941                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999941                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          401                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           64                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1297920552                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1297920552                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    157560037                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       157560037                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    145486469                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      145486469                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       397138                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        397138                       # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data       335387                       # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total       335387                       # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3699332                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3699332                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      4002690                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      4002690                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     303046506                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        303046506                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    303443644                       # number of overall hits
system.cpu.dcache.overall_hits::total       303443644                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      5342305                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       5342305                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2238545                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2238545                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1309963                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1309963                       # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data      1232790                       # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total      1232790                       # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       305057                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       305057                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      7580850                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7580850                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      8890813                       # number of overall misses
system.cpu.dcache.overall_misses::total       8890813                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  83595802503                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  83595802503                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  64185055523                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  64185055523                       # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data  27578524507                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total  27578524507                       # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4441396750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4441396750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       150000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       150000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 147780858026                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 147780858026                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 147780858026                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 147780858026                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    162902342                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    162902342                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    147725014                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    147725014                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1707101                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1707101                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data      1568177                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total      1568177                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4004389                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      4004389                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      4002692                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      4002692                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    310627356                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    310627356                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    312334457                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    312334457                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032795                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.032795                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015153                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.015153                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.767361                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.767361                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data     0.786129                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total     0.786129                       # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.076181                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.076181                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.024405                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.024405                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.028466                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.028466                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15647.890284                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15647.890284                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28672.667077                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28672.667077                       # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22370.821070                       # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22370.821070                       # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14559.235651                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14559.235651                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        75000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19493.969413                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19493.969413                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16621.748543                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16621.748543                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7913457                       # number of writebacks
system.cpu.dcache.writebacks::total           7913457                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7211                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         7211                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21165                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        21165                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        71123                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        71123                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        28376                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        28376                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        28376                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        28376                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5335094                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5335094                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2217380                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2217380                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1308216                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1308216                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data      1232790                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total      1232790                       # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       233934                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       233934                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7552474                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7552474                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8860690                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8860690                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  72364530247                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  72364530247                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  58930269477                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  58930269477                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  19541293498                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  19541293498                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data  25112944493                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total  25112944493                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2872283000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2872283000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       146000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131294799724                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 131294799724                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150836093222                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 150836093222                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5727964499                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5727964499                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5573385250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5573385250                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11301349749                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  11301349749                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032750                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032750                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015010                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015010                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.766338                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.766338                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.786129                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786129                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058419                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058419                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024314                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.024314                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028369                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.028369                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13563.871648                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13563.871648                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26576.531527                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26576.531527                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14937.360113                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14937.360113                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20370.821059                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20370.821059                       # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12278.176751                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12278.176751                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        73000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17384.343160                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17384.343160                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17023.064030                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17023.064030                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          13791662                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.892960                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           884583728                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          13792174                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             64.136642                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       31822438250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.892960                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999791                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999791                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          193                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         912168086                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        912168086                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    884583728                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       884583728                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     884583728                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        884583728                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    884583728                       # number of overall hits
system.cpu.icache.overall_hits::total       884583728                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     13792179                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      13792179                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     13792179                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       13792179                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     13792179                       # number of overall misses
system.cpu.icache.overall_misses::total      13792179                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 184446403226                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 184446403226                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 184446403226                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 184446403226                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 184446403226                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 184446403226                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    898375907                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    898375907                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    898375907                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    898375907                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    898375907                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    898375907                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015352                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015352                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015352                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015352                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015352                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015352                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13373.260543                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13373.260543                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13373.260543                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13373.260543                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13373.260543                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13373.260543                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13792179                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     13792179                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     13792179                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     13792179                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     13792179                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     13792179                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 156833610274                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 156833610274                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 156833610274                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 156833610274                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 156833610274                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 156833610274                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2831639000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2831639000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2831639000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   2831639000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015352                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015352                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015352                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.015352                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015352                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.015352                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.198871                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.198871                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.198871                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.198871                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.198871                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.198871                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1330655                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65236.148872                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           27755474                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1393687                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            19.915142                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6373825000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 38814.158351                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   314.572055                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   427.557921                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  6384.961919                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19294.898626                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.592257                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004800                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006524                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.097427                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.294417                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995425                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          245                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        62787                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          245                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          411                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2448                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5435                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54454                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003738                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.958054                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        265729281                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       265729281                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       380608                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       251172                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst     13712819                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      6587464                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total       20932063                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      7913457                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      7913457                       # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data       720904                       # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total       720904                       # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        10014                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        10014                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1637190                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1637190                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       380608                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       251172                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     13712819                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      8224654                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        22569253                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       380608                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       251172                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     13712819                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      8224654                       # number of overall hits
system.cpu.l2cache.overall_hits::total       22569253                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         4179                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         4227                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        79360                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       289780                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       377546                       # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data       511886                       # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total       511886                       # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        35708                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        35708                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       534468                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       534468                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         4179                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         4227                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        79360                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       824248                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        912014                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         4179                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         4227                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        79360                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       824248                       # number of overall misses
system.cpu.l2cache.overall_misses::total       912014                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    326739750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    334789750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   5912719487                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  22025051995                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  28599300982                       # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data       117495                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total       117495                       # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data    415763234                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total    415763234                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       144000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       144000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  39424784684                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  39424784684                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    326739750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    334789750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   5912719487                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  61449836679                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  68024085666                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    326739750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    334789750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   5912719487                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  61449836679                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  68024085666                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       384787                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       255399                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst     13792179                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      6877244                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total     21309609                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      7913457                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      7913457                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data      1232790                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total      1232790                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        45722                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        45722                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2171658                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2171658                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       384787                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       255399                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     13792179                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9048902                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     23481267                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       384787                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       255399                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     13792179                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9048902                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     23481267                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.010861                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.016551                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.005754                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.042136                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.017717                       # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data     0.415226                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total     0.415226                       # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.780981                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.780981                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.246111                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.246111                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.010861                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.016551                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005754                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.091088                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.038840                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.010861                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.016551                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005754                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.091088                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.038840                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78186.109117                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79202.685119                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74505.033858                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76006.114967                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75750.507175                       # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data     0.229534                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total     0.229534                       # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11643.419794                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11643.419794                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        72000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        72000                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73764.537230                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73764.537230                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78186.109117                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79202.685119                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74505.033858                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74552.606350                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74586.668259                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78186.109117                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79202.685119                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74505.033858                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74552.606350                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74586.668259                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1137707                       # number of writebacks
system.cpu.l2cache.writebacks::total          1137707                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         4179                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4227                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        79360                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       289780                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       377546                       # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data       511886                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total       511886                       # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        35708                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        35708                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       534468                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       534468                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         4179                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4227                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        79360                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       824248                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       912014                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         4179                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4227                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        79360                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       824248                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       912014                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    274533250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    281888250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   4919274513                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  18395024005                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  23870720018                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data  11039301007                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total  11039301007                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    357176707                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    357176707                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  32752998316                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  32752998316                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    274533250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    281888250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   4919274513                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  51148022321                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  56623718334                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    274533250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    281888250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   4919274513                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  51148022321                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  56623718334                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2248902500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5288010501                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   7536913001                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5166015500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5166015500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2248902500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10454026001                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  12702928501                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.010861                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.016551                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.005754                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.042136                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.017717                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data     0.415226                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total     0.415226                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.780981                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.780981                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.246111                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.246111                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.010861                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.016551                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005754                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.091088                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.038840                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.010861                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.016551                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005754                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.091088                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.038840                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053                       # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570                       # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60000                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       21752331                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      21744344                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      7913457                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq      1339455                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp      1232790                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        45725                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        45727                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2171658                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2171658                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     27670608                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28704497                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       624113                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1013195                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          58012413                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    882871956                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1164737260                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2043192                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      3078296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2052730704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      473368                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     33145716                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.003486                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.058938                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5           33030174     99.65%     99.65% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6             115542      0.35%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       33145716                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    25733748000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1332000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   20755677476                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   14427270036                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     369197500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     628893000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40403                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40403                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231002                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231002                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354272                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334440                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334440                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492846                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1042395169                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179037771                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115482                       # number of replacements
system.iocache.tags.tagsinuse               10.457347                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115498                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13153920852000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510781                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946566                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219424                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434160                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653584                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039866                       # Number of tag accesses
system.iocache.tags.data_accesses             1039866                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8837                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8874                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8837                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8877                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8837                       # number of overall misses
system.iocache.overall_misses::total             8877                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5479000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1901914612                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1907393612                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28843036786                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28843036786                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5818000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1901914612                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1907732612                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5818000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1901914612                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1907732612                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8837                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8874                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8837                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8877                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8837                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8877                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 214941.808880                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 215221.750820                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 214907.357441                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 215221.750820                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 214907.357441                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        223600                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27526                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.123229                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8837                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8874                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8837                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8877                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8837                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8877                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3555000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1442304112                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1445859112                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23296466828                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23296466828                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3738000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1442304112                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1446042112                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3738000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1442304112                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1446042112                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 162897.613158                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 162897.613158                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              463332                       # Transaction distribution
system.membus.trans_dist::ReadResp             463332                       # Transaction distribution
system.membus.trans_dist::WriteReq              33872                       # Transaction distribution
system.membus.trans_dist::WriteResp             33872                       # Transaction distribution
system.membus.trans_dist::Writeback           1244337                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       618545                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       618545                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36281                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36283                       # Transaction distribution
system.membus.trans_dist::ReadExReq            533903                       # Transaction distribution
system.membus.trans_dist::ReadExResp           533903                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4147646                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4277836                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       334832                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       334832                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4612668                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    164057632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    164227968                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14034624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14034624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               178262592                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3539                       # Total snoops (count)
system.membus.snoop_fanout::samples           2819489                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2819489    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2819489                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106085000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5679999                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         17900056737                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         9260714451                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          186597229                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped

---------- End Simulation Statistics   ----------