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---------- Begin Simulation Statistics ----------
sim_seconds 5.112126 # Number of seconds simulated
sim_ticks 5112126311000 # Number of ticks simulated
final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1020096 # Simulator instruction rate (inst/s)
host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 26083435490 # Simulator tick rate (ticks/s)
host_mem_usage 587152 # Number of bytes of host memory used
host_seconds 195.99 # Real time elapsed on the host
sim_insts 199929810 # Number of instructions simulated
sim_ops 409343980 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory
system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory
system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory
system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory
system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 0 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 0 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.totBankLat 0 # Total cycles spent in bank access
system.physmem.avgQLat nan # Average queueing delay per request
system.physmem.avgBankLat nan # Average bank access latency per request
system.physmem.avgBusLat nan # Average bus latency per request
system.physmem.avgMemAccLat nan # Average memory access latency
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 0 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
system.membus.throughput 9634332 # Throughput (bytes/s)
system.membus.data_through_bus 49251923 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.tags.replacements 47569 # number of replacements
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
system.iocache.overall_misses::total 47624 # number of overall misses
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.throughput 2555207 # Throughput (bytes/s)
system.iobus.data_through_bus 13062542 # Total data (bytes)
system.cpu.numCycles 10224252644 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 199929810 # Number of instructions committed
system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 2307717 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls
system.cpu.num_int_insts 374506599 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read
system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 35660913 # number of memory refs
system.cpu.num_load_insts 27238816 # Number of load instructions
system.cpu.num_store_insts 8422097 # Number of store instructions
system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles
system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles
system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 790541 # number of replacements
system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits
system.cpu.icache.overall_hits::total 243525798 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses
system.cpu.icache.overall_misses::total 791060 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1622093 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits
system.cpu.dcache.overall_hits::total 20172913 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses
system.cpu.dcache.overall_misses::total 1624891 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks
system.cpu.dcache.writebacks::total 1535822 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s)
system.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)
system.cpu.l2cache.tags.replacements 105999 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits
system.cpu.l2cache.overall_hits::total 2242310 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks
system.cpu.l2cache.writebacks::total 98156 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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