path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.194921                       # Number of seconds simulated
sim_ticks                                5194921252500                       # Number of ticks simulated
final_tick                               5194921252500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 862150                       # Simulator instruction rate (inst/s)
host_op_rate                                  1661827                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            34815163679                       # Simulator tick rate (ticks/s)
host_mem_usage                                 660376                       # Number of bytes of host memory used
host_seconds                                   149.21                       # Real time elapsed on the host
sim_insts                                   128645146                       # Number of instructions simulated
sim_ops                                     247968367                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            824576                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8975232                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9828480                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       824576                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          824576                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8074432                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8074432                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12884                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140238                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                153570                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126163                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               126163                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158727                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1727694                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5458                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1891940                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158727                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158727                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1554293                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1554293                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1554293                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158727                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1727694                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5458                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3446234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        153570                       # Number of read requests accepted
system.physmem.writeReqs                       126163                       # Number of write requests accepted
system.physmem.readBursts                      153570                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     126163                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9818304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8073216                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9828480                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8074432                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          48373                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9606                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9083                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10021                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9578                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9425                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9133                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9428                       # Per bank write bursts
system.physmem.perBankRdBursts::7                9379                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9296                       # Per bank write bursts
system.physmem.perBankRdBursts::9                9532                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9485                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9788                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9982                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10070                       # Per bank write bursts
system.physmem.perBankRdBursts::14               9926                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9679                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8208                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7344                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8031                       # Per bank write bursts
system.physmem.perBankWrBursts::3                7623                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7645                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7565                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7708                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7791                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7759                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7930                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7732                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7853                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8038                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8512                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8378                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8027                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
system.physmem.totGap                    5194921069000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  153570                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 126163                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    150128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2870                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        47                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6776                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     8103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    10321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6846                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6403                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        55967                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      319.678668                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     191.248377                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.031309                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          19371     34.61%     34.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        13720     24.51%     59.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6335     11.32%     70.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3428      6.13%     76.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2404      4.30%     80.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1641      2.93%     83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1130      2.02%     85.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          964      1.72%     87.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6974     12.46%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          55967                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5838                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        26.276465                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      626.709863                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           5837     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5838                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5838                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        21.607400                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.425561                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       14.518520                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            4794     82.12%     82.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             110      1.88%     84.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              38      0.65%     84.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             229      3.92%     88.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              28      0.48%     89.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             201      3.44%     92.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              72      1.23%     93.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               6      0.10%     93.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              12      0.21%     94.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              30      0.51%     94.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               7      0.12%     94.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.10%     94.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             233      3.99%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.09%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.07%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              31      0.53%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.02%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.02%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.02%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.05%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            16      0.27%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.02%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.05%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5838                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1519267484                       # Total ticks spent queuing
system.physmem.totMemAccLat                4395723734                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    767055000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9903.25                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28653.25                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.55                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.23                       # Average write queue length when enqueuing
system.physmem.readRowHits                     125316                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     98271                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.69                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.89                       # Row buffer hit rate for writes
system.physmem.avgGap                     18570998.31                       # Average gap between requests
system.physmem.pageHitRate                      79.97                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  205775640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  112278375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 590093400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                401209200                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           339306654960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           136710410535                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2997028289250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3474354711360                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.798995                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4985717898976                       # Time in different power states
system.physmem_0.memoryStateTime::REF    173469660000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     35728624774                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  217334880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  118585500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 606504600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                416203920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           339306654960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           137303657415                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2996507897250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3474476838525                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.822504                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4984854152228                       # Time in different power states
system.physmem_1.memoryStateTime::REF    173469660000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     36597268272                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                      10389842505                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128645146                       # Number of instructions committed
system.cpu.committedOps                     247968367                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             232546073                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
system.cpu.num_func_calls                     2315361                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23194066                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    232546073                       # number of integer instructions
system.cpu.num_fp_insts                            48                       # number of float instructions
system.cpu.num_int_register_reads           435625867                       # number of times the integer registers were read
system.cpu.num_int_register_writes          198317571                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            133116487                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            95666128                       # number of times the CC registers were written
system.cpu.num_mem_refs                      22339099                       # number of memory refs
system.cpu.num_load_insts                    13935933                       # Number of load instructions
system.cpu.num_store_insts                    8403166                       # Number of store instructions
system.cpu.num_idle_cycles               9774871363.998119                       # Number of idle cycles
system.cpu.num_busy_cycles               614971141.001882                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.059190                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.940810                       # Percentage of idle cycles
system.cpu.Branches                          26367781                       # Number of branches fetched
system.cpu.op_class::No_OpClass                172241      0.07%      0.07% # Class of executed instruction
system.cpu.op_class::IntAlu                 225200251     90.82%     90.89% # Class of executed instruction
system.cpu.op_class::IntMult                   140056      0.06%     90.94% # Class of executed instruction
system.cpu.op_class::IntDiv                    123237      0.05%     90.99% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatCvt                      16      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     90.99% # Class of executed instruction
system.cpu.op_class::MemRead                 13930961      5.62%     96.61% # Class of executed instruction
system.cpu.op_class::MemWrite                 8403166      3.39%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  247969928                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements           1623328                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.995361                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            20131143                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1623840                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.397245                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          81561500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.995361                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          123                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88683234                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88683234                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     12000893                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        12000893                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8069415                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8069415                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        58662                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         58662                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      20070308                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20070308                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20128970                       # number of overall hits
system.cpu.dcache.overall_hits::total        20128970                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       906883                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        906883                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       325772                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       325772                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       403210                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       403210                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1232655                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1232655                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1635865                       # number of overall misses
system.cpu.dcache.overall_misses::total       1635865                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  13550557000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  13550557000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18295357977                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18295357977                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  31845914977                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  31845914977                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  31845914977                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  31845914977                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12907776                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12907776                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8395187                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8395187                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       461872                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       461872                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21302963                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21302963                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21764835                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21764835                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070259                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.070259                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038805                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.038805                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872991                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.872991                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.057863                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.057863                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.075161                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.075161                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.902098                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.902098                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56160.007542                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 56160.007542                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25835.221515                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25835.221515                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19467.324612                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19467.324612                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        15094                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               441                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    34.226757                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1540461                       # number of writebacks
system.cpu.dcache.writebacks::total           1540461                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          292                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          292                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9470                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         9470                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         9762                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         9762                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         9762                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         9762                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906591                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       906591                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       316302                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       316302                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403174                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       403174                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1222893                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1222893                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1626067                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1626067                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       572954                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       572954                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       586874                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       586874                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12641489000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12641489000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17000944477                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17000944477                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6508610000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6508610000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29642433477                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29642433477                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36151043477                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  36151043477                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94684331000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94684331000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2622740500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2622740500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97307071500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  97307071500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070236                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070236                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037677                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037677                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.872913                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.872913                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057405                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.057405                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074711                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074711                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements         7724                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse     5.052199                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        13169                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs         7738                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.701861                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052199                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315762                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315762                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses        53153                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses        53153                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13186                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        13186                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13186                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        13186                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13186                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        13186                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8927                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         8927                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8927                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         8927                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8927                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         8927                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     97243000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     97243000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     97243000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     97243000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     97243000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     97243000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22113                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        22113                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22113                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        22113                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22113                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        22113                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.403699                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.403699                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.403699                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.403699                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.403699                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.403699                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         2877                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         2877                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8927                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8927                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8927                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         8927                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8927                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         8927                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     88316000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     88316000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     88316000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     88316000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     88316000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     88316000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.403699                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.403699                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.403699                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.403699                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.403699                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.403699                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9893.133191                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9893.133191                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9893.133191                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9893.133191                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9893.133191                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9893.133191                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            789867                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.214824                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           144930127                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            790379                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            183.367887                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      164495636500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.214824                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996513                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996513                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          150                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         146510899                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        146510899                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    144930127                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144930127                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144930127                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144930127                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144930127                       # number of overall hits
system.cpu.icache.overall_hits::total       144930127                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       790386                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        790386                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       790386                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         790386                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       790386                       # number of overall misses
system.cpu.icache.overall_misses::total        790386                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11833714500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11833714500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11833714500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11833714500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11833714500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11833714500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145720513                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145720513                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145720513                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145720513                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145720513                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145720513                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005424                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005424                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005424                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005424                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005424                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005424                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14972.069976                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14972.069976                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14972.069976                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14972.069976                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       790386                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       790386                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       790386                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       790386                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       790386                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       790386                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11043328500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11043328500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11043328500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11043328500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11043328500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11043328500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005424                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005424                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005424                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005424                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005424                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005424                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13972.069976                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13972.069976                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13972.069976                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13972.069976                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13972.069976                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13972.069976                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         3784                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     3.071212                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs         7587                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         3797                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.998156                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5168596607500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.071212                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191951                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.191951                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        29077                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        29077                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7587                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7587                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7589                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7589                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7589                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7589                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4633                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4633                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4633                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4633                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4633                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4633                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     48911500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     48911500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     48911500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     48911500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     48911500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     48911500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12220                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12220                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12222                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12222                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12222                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12222                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.379133                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.379133                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.379071                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.379071                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.379071                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.379071                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10557.198360                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10557.198360                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10557.198360                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10557.198360                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10557.198360                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10557.198360                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          721                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          721                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4633                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4633                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4633                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4633                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4633                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4633                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     44278500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     44278500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     44278500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     44278500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     44278500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     44278500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.379133                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.379133                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.379071                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.379071                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.379071                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.379071                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9557.198360                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9557.198360                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9557.198360                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9557.198360                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9557.198360                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9557.198360                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            86240                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64592.333945                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4367637                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           150989                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            28.926856                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50133.527739                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.146857                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3457.643805                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11001.015544                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.764977                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052759                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.167862                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.985601                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64749                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2897                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5100                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56598                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987991                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         39213781                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        39213781                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1544059                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1544059                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          298                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          298                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       201469                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       201469                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       777488                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       777488                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6514                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         3101                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1280565                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1290180                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6514                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3101                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       777488                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1482034                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2269137                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6514                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3101                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       777488                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1482034                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2269137                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1394                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1394                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       112654                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       112654                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        12885                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        12885                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        28510                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        28515                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12885                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141164                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154054                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12885                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141164                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154054                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     55378500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     55378500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14292640000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  14292640000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1690999500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1690999500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       637500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3736922500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3737560000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       637500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1690999500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  18029562500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  19721199500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       637500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1690999500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  18029562500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  19721199500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1544059                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1544059                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1692                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1692                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       314123                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       314123                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       790373                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       790373                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6514                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         3106                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1309075                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1318695                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6514                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3106                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       790373                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1623198                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2423191                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6514                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3106                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       790373                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1623198                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2423191                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.823877                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823877                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358630                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.358630                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016302                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016302                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.001610                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.021779                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.021624                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001610                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016302                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.086967                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063575                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001610                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016302                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.086967                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063575                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39726.327116                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39726.327116                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126872.015197                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126872.015197                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131237.834692                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131237.834692                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       127500                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131074.096808                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131073.470103                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131237.834692                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127720.683035                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 128014.848689                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131237.834692                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127720.683035                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 128014.848689                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        79496                       # number of writebacks
system.cpu.l2cache.writebacks::total            79496                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           19                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total           19                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1394                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1394                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       112654                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       112654                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        12885                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        12885                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        28510                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        28515                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12885                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141164                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154054                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12885                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141164                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154054                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       572954                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       572954                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       586874                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       586874                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     99511500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     99511500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13166100000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13166100000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1562149500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1562149500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       587500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3451822500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3452410000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       587500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1562149500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16617922500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  18180659500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       587500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1562149500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16617922500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  18180659500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  87522404000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  87522404000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2462660500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2462660500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89985064500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89985064500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823877                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823877                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358630                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.358630                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016302                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016302                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.001610                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.021779                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.021624                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001610                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016302                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.086967                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063575                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001610                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016302                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.086967                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063575                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71385.581062                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71385.581062                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 116872.015197                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 116872.015197                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      4854729                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2424193                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        12092                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1088                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1088                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         572954                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2686987                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1670227                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       881786                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2186                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2186                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       314129                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       314129                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       790386                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1324171                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1654                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2370613                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6047740                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         9205                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19678                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8447236                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50583872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204138427                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       244928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       601024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          255568251                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      188441                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5624579                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.004514                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.080591                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            5604820     99.65%     99.65% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              14130      0.25%     99.90% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2               5629      0.10%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5624579                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4271820500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       588787                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1185579000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3016848998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       6949500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      13390500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               226550                       # Transaction distribution
system.iobus.trans_dist::ReadResp              226550                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1654                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1654                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       429188                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       473420                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95132                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95132                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  571860                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       214594                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       242990                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027312                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3276918                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3944816                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8813000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                77000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            214595000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           240989862                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           462414000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50044000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1654000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47511                       # number of replacements
system.iocache.tags.tagsinuse                0.108299                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47527                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5048321264000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.108299                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006769                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006769                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428094                       # Number of tag accesses
system.iocache.tags.data_accesses              428094                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          846                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              846                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          846                       # number of demand (read+write) misses
system.iocache.demand_misses::total               846                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          846                       # number of overall misses
system.iocache.overall_misses::total              846                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144199688                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    144199688                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6059543174                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   6059543174                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    144199688                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    144199688                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    144199688                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    144199688                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          846                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            846                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          846                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             846                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          846                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            846                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 170448.803783                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 170448.803783                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 170448.803783                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           693                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   36                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    19.250000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          846                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          846                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          846                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          846                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          846                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          846                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    101899688                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    101899688                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3723543174                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3723543174                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    101899688                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    101899688                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    101899688                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    101899688                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 120448.803783                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 120448.803783                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              572954                       # Transaction distribution
system.membus.trans_dist::ReadResp             615200                       # Transaction distribution
system.membus.trans_dist::WriteReq              13920                       # Transaction distribution
system.membus.trans_dist::WriteResp             13920                       # Transaction distribution
system.membus.trans_dist::Writeback            126163                       # Transaction distribution
system.membus.trans_dist::CleanEvict             7113                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2165                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1671                       # Transaction distribution
system.membus.trans_dist::ReadExReq            112377                       # Transaction distribution
system.membus.trans_dist::ReadExResp           112377                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         42246                       # Transaction distribution
system.membus.trans_dist::MessageReq             1654                       # Transaction distribution
system.membus.trans_dist::MessageResp            1654                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3308                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3308                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       473420                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       700328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       396961                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1570709                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141766                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141766                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1715783                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       242990                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1400653                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14887872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16531515                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19553171                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1565                       # Total snoops (count)
system.membus.snoop_fanout::samples            925791                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001787                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.042230                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  924137     99.82%     99.82% # Request fanout histogram
system.membus.snoop_fanout::2                    1654      0.18%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total              925791                       # Request fanout histogram
system.membus.reqLayer0.occupancy           359890000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           527983500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3308000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy           843164843                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1654000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2152042345                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           85908558                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.

---------- End Simulation Statistics   ----------