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|
---------- Begin Simulation Statistics ----------
sim_seconds 5.196145 # Number of seconds simulated
sim_ticks 5196144770000 # Number of ticks simulated
final_tick 5196144770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 471788 # Simulator instruction rate (inst/s)
host_op_rate 909467 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 19106715414 # Simulator tick rate (ticks/s)
host_mem_usage 586268 # Number of bytes of host memory used
host_seconds 271.95 # Real time elapsed on the host
sim_insts 128304418 # Number of instructions simulated
sim_ops 247333117 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2891776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8961408 # Number of bytes read from this memory
system.physmem.bytes_read::total 12677312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8105792 # Number of bytes written to this memory
system.physmem.bytes_written::total 8105792 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 45184 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140022 # Number of read requests responded to by this memory
system.physmem.num_reads::total 198083 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 126653 # Number of write requests responded to by this memory
system.physmem.num_writes::total 126653 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 556523 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 158530 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1724626 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2439753 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 158530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 158530 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1559963 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1559963 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1559963 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 556523 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 158530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1724626 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3999716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198083 # Total number of read requests seen
system.physmem.writeReqs 126653 # Total number of write requests seen
system.physmem.cpureqs 326336 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 12677312 # Total number of bytes read from memory
system.physmem.bytesWritten 8105792 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 12677312 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 8105792 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1597 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 12388 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 12465 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 13064 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 12742 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 12822 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 12061 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 12170 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 12418 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 11780 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 11808 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 12169 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 12505 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 12558 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 12789 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 12227 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 12047 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7920 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 8110 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 8533 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 8387 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 8388 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7744 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7664 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7959 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7196 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7383 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7714 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 8157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 8159 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7876 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
system.physmem.totGap 5196144706500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 198083 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 126653 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 154572 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 13375 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 7517 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3048 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2915 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2517 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1489 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1265 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1181 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1032 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1095 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1162 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1135 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 924 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 350 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 220 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4658 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5500 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5506 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 849 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 45242 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 458.910923 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 168.789921 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1568.289191 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 18577 41.06% 41.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 7110 15.72% 56.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 4218 9.32% 66.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 2889 6.39% 72.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 2001 4.42% 76.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 1601 3.54% 80.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 1275 2.82% 83.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 961 2.12% 85.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 799 1.77% 87.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 633 1.40% 88.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 499 1.10% 89.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 460 1.02% 90.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 337 0.74% 91.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 345 0.76% 92.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 215 0.48% 92.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 170 0.38% 93.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 159 0.35% 94.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 128 0.28% 94.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 109 0.24% 94.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 88 0.19% 94.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 127 0.28% 95.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 644 1.42% 96.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 160 0.35% 97.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 109 0.24% 97.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 90 0.20% 97.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 61 0.13% 97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 44 0.10% 97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 17 0.04% 97.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 21 0.05% 97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 12 0.03% 97.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 37 0.08% 97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 16 0.04% 97.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 11 0.02% 97.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 9 0.02% 98.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 9 0.02% 98.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 6 0.01% 98.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 3 0.01% 98.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 5 0.01% 98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 2 0.00% 98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 3 0.01% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 1 0.00% 98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 14 0.03% 98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 3 0.01% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 1 0.00% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 4 0.01% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 12 0.03% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 2 0.00% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 7 0.02% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 7 0.02% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 8 0.02% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 237 0.52% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451 13 0.03% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515 17 0.04% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17280-17283 2 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17600-17603 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 45242 # Bytes accessed per row activation
system.physmem.totQLat 3435518998 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7067756498 # Sum of mem lat for all requests
system.physmem.totBusLat 990065000 # Total cycles spent in databus access
system.physmem.totBankLat 2642172500 # Total cycles spent in bank access
system.physmem.avgQLat 17349.97 # Average queueing delay per request
system.physmem.avgBankLat 13343.43 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 35693.40 # Average memory access latency
system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 9.35 # Average write queue length over time
system.physmem.readRowHits 181015 # Number of row buffer hits during reads
system.physmem.writeRowHits 98394 # Number of row buffer hits during writes
system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 77.69 # Row buffer hit rate for writes
system.physmem.avgGap 16001135.40 # Average gap between requests
system.membus.throughput 4358895 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 623371 # Transaction distribution
system.membus.trans_dist::ReadResp 623371 # Transaction distribution
system.membus.trans_dist::WriteReq 13727 # Transaction distribution
system.membus.trans_dist::WriteResp 13727 # Transaction distribution
system.membus.trans_dist::Writeback 126653 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2147 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1615 # Transaction distribution
system.membus.trans_dist::ReadExReq 159120 # Transaction distribution
system.membus.trans_dist::ReadExResp 159120 # Transaction distribution
system.membus.trans_dist::MessageReq 1656 # Transaction distribution
system.membus.trans_dist::MessageResp 1656 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390174 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480118 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580408 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139407 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 139407 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 529581 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 480118 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1723127 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14904512 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571083 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5878592 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5878592 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 20783104 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 22456299 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 22456299 # Total data (bytes)
system.membus.snoop_data_through_bus 193152 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1348670998 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 256617500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 359320000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 3312000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 2607874799 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer4.occupancy 428809000 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.replacements 47501 # number of replacements
system.iocache.tagsinuse 0.169264 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47517 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 5049524013000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.169264 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.010579 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.010579 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 834 # number of ReadReq misses
system.iocache.ReadReq_misses::total 834 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47554 # number of demand (read+write) misses
system.iocache.demand_misses::total 47554 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47554 # number of overall misses
system.iocache.overall_misses::total 47554 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142703185 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 142703185 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10862337325 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10862337325 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 11005040510 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 11005040510 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 11005040510 # number of overall miss cycles
system.iocache.overall_miss_latency::total 11005040510 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 834 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47554 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47554 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47554 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47554 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171106.936451 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 171106.936451 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232498.658497 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 232498.658497 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 231421.973125 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 231421.973125 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 174194 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16040 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.859975 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46669 # number of writebacks
system.iocache.writebacks::total 46669 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 834 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47554 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47554 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47554 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47554 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99319185 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 99319185 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8432090325 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8432090325 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8531409510 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8531409510 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119087.751799 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 119087.751799 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180481.385381 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 180481.385381 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.throughput 631272 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 230083 # Transaction distribution
system.iobus.trans_dist::ReadResp 230083 # Transaction distribution
system.iobus.trans_dist::WriteReq 57530 # Transaction distribution
system.iobus.trans_dist::WriteResp 57530 # Transaction distribution
system.iobus.trans_dist::MessageReq 1656 # Transaction distribution
system.iobus.trans_dist::MessageResp 1656 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 480118 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95108 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 578538 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 246342 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027216 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 3280182 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3280182 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3949664 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 424330510 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 469308000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 52196000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.numCycles 10392289540 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 128304418 # Number of instructions committed
system.cpu.committedOps 247333117 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 232067207 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 2300061 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23160261 # number of instructions that are conditional controls
system.cpu.num_int_insts 232067207 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 567198543 # number of times the integer registers were read
system.cpu.num_int_register_writes 293301890 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 22245318 # number of memory refs
system.cpu.num_load_insts 13878816 # Number of load instructions
system.cpu.num_store_insts 8366502 # Number of store instructions
system.cpu.num_idle_cycles 9785692797.998116 # Number of idle cycles
system.cpu.num_busy_cycles 606596742.001883 # Number of busy cycles
system.cpu.not_idle_fraction 0.058370 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.941630 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.replacements 791404 # number of replacements
system.cpu.icache.tagsinuse 510.366672 # Cycle average of tags in use
system.cpu.icache.total_refs 144533937 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 791916 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 182.511702 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 161113577000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.366672 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996810 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996810 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 144533937 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144533937 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144533937 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144533937 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144533937 # number of overall hits
system.cpu.icache.overall_hits::total 144533937 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791923 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791923 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791923 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791923 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791923 # number of overall misses
system.cpu.icache.overall_misses::total 791923 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11177158500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11177158500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11177158500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11177158500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11177158500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11177158500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145325860 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145325860 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145325860 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145325860 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145325860 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145325860 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14113.946053 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14113.946053 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14113.946053 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14113.946053 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791923 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 791923 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 791923 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 791923 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 791923 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 791923 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9593312500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9593312500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9593312500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9593312500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9593312500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9593312500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.946053 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.946053 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 3530 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 3.075423 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 7811 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3541 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.205874 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5166918586000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.075423 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192214 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.192214 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7833 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7833 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7835 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7835 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7835 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7835 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4388 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4388 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4388 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4388 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4388 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4388 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43163000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43163000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43163000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 43163000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43163000 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 43163000 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.359054 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.359054 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358995 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.358995 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358995 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.358995 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9836.599818 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9836.599818 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9836.599818 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9836.599818 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 619 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 619 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4388 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4388 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4388 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 4388 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4388 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 4388 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34387000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34387000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34387000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34387000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34387000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34387000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.359054 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.359054 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358995 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358995 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7836.599818 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 7412 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.056524 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 13351 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7427 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.797630 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5162997491000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.056524 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316033 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.316033 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13351 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13351 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13351 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13351 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13351 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13351 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8618 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8618 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8618 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8618 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8618 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8618 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90576000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90576000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90576000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 90576000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90576000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 90576000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21969 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21969 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21969 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21969 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21969 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21969 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392280 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392280 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392280 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392280 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392280 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392280 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10510.095150 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10510.095150 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10510.095150 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10510.095150 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 2749 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2749 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8618 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8618 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8618 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8618 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8618 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8618 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 73340000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 73340000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 73340000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 73340000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 73340000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 73340000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392280 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392280 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392280 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8510.095150 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1622441 # number of replacements
system.cpu.dcache.tagsinuse 511.992388 # Cycle average of tags in use
system.cpu.dcache.total_refs 20034872 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1622953 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.344703 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 48929000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.992388 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 11992680 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11992680 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8039994 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8039994 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20032674 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20032674 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20032674 # number of overall hits
system.cpu.dcache.overall_hits::total 20032674 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308966 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308966 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 316237 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 316237 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1625203 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1625203 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1625203 # number of overall misses
system.cpu.dcache.overall_misses::total 1625203 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18848048000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18848048000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10644655000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10644655000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 29492703000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 29492703000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 29492703000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 29492703000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13301646 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13301646 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8356231 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8356231 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21657877 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21657877 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21657877 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21657877 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098406 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098406 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037844 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037844 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.075040 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.075040 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.075040 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.075040 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.188367 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.188367 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33660.371810 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33660.371810 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18147.088702 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18147.088702 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1539801 # number of writebacks
system.cpu.dcache.writebacks::total 1539801 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308966 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1308966 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316237 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 316237 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1625203 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1625203 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1625203 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1625203 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16230116000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16230116000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10012181000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10012181000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26242297000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26242297000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26242297000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26242297000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94201595500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94201595500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2525692000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2525692000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96727287500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96727287500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098406 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098406 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.075040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.075040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12399.188367 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12399.188367 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31660.371810 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31660.371810 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 49236259 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2696119 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2695598 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13727 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13727 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1543169 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2198 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 360759 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 314063 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1583833 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5979450 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 7815 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 17592 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 7588690 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50682240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 204056779 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 219328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 574336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 255532683 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 255511115 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 327616 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3834241500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 505500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1187884500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3023860000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 6582000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 12927000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.replacements 86618 # number of replacements
system.cpu.l2cache.tagsinuse 64735.286295 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3491811 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 151264 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 23.084217 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 49971.529408 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.027392 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.141401 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3486.795305 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 11276.792789 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.762505 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.053204 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.172070 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.987782 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6224 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2803 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 779038 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1279905 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2067970 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1543169 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1543169 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 201356 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 201356 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6224 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2803 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 779038 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1481261 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2269326 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6224 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2803 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 779038 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1481261 # number of overall hits
system.cpu.l2cache.overall_hits::total 2269326 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 28269 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 41147 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1336 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1336 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 112679 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 112679 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 12872 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 140948 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153826 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 12872 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 140948 # number of overall misses
system.cpu.l2cache.overall_misses::total 153826 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1010996500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2121306500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3132781000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15904000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 15904000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7647596500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7647596500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1010996500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9768903000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10780377500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1010996500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9768903000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10780377500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6225 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2808 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791910 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308174 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2109117 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1543169 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1543169 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1666 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1666 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314035 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314035 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6225 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2808 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791910 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1622209 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2423152 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6225 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2808 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791910 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1622209 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2423152 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000161 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021610 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.019509 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.801921 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.801921 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358810 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.358810 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000161 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.086886 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063482 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000161 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.086886 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063482 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77800 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78542.301119 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75040.026177 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76136.316135 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11904.191617 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11904.191617 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67870.645817 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67870.645817 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77800 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78542.301119 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69308.560604 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70081.634444 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77800 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78542.301119 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69308.560604 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70081.634444 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 79984 # number of writebacks
system.cpu.l2cache.writebacks::total 79984 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28269 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 41147 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1336 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1336 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112679 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 112679 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12872 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 140948 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 153826 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 140948 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 153826 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851715758 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1771468289 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2623586547 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14290818 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14290818 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6265697836 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6265697836 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851715758 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8037166125 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8889284383 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851715758 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8037166125 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8889284383 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86643520000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86643520000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2359628500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2359628500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89003148500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89003148500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021610 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.801921 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.801921 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358810 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358810 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063482 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063482 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66168.098042 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62664.695921 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63761.308163 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10696.720060 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10696.720060 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55606.615572 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55606.615572 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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