path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.196390                       # Number of seconds simulated
sim_ticks                                5196390180000                       # Number of ticks simulated
final_tick                               5196390180000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 893068                       # Simulator instruction rate (inst/s)
host_op_rate                                  1721530                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36161085452                       # Simulator tick rate (ticks/s)
host_mem_usage                                 586592                       # Number of bytes of host memory used
host_seconds                                   143.70                       # Real time elapsed on the host
sim_insts                                   128334813                       # Number of instructions simulated
sim_ops                                     247385808                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2883712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            824512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           8989184                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12697856                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       824512                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          824512                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8110912                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8110912                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        45058                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12883                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140456                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198404                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126733                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               126733                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       554945                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker             25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158670                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1729890                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2443592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158670                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158670                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1560874                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1560874                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1560874                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       554945                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158670                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1729890                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4004466                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198404                       # Number of read requests accepted
system.physmem.writeReqs                       126733                       # Number of write requests accepted
system.physmem.readBursts                      198404                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     126733                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 12694144                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      3712                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   8109888                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  12697856                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                8110912                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       58                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1616                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12580                       # Per bank write bursts
system.physmem.perBankRdBursts::1               12146                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12820                       # Per bank write bursts
system.physmem.perBankRdBursts::3               12639                       # Per bank write bursts
system.physmem.perBankRdBursts::4               12420                       # Per bank write bursts
system.physmem.perBankRdBursts::5               12033                       # Per bank write bursts
system.physmem.perBankRdBursts::6               12032                       # Per bank write bursts
system.physmem.perBankRdBursts::7               12154                       # Per bank write bursts
system.physmem.perBankRdBursts::8               12328                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11842                       # Per bank write bursts
system.physmem.perBankRdBursts::10              12289                       # Per bank write bursts
system.physmem.perBankRdBursts::11              12385                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12618                       # Per bank write bursts
system.physmem.perBankRdBursts::13              13039                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12508                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12513                       # Per bank write bursts
system.physmem.perBankWrBursts::0                8180                       # Per bank write bursts
system.physmem.perBankWrBursts::1                7837                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8283                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8150                       # Per bank write bursts
system.physmem.perBankWrBursts::4                7961                       # Per bank write bursts
system.physmem.perBankWrBursts::5                7589                       # Per bank write bursts
system.physmem.perBankWrBursts::6                7480                       # Per bank write bursts
system.physmem.perBankWrBursts::7                7728                       # Per bank write bursts
system.physmem.perBankWrBursts::8                7696                       # Per bank write bursts
system.physmem.perBankWrBursts::9                7447                       # Per bank write bursts
system.physmem.perBankWrBursts::10               7846                       # Per bank write bursts
system.physmem.perBankWrBursts::11               7788                       # Per bank write bursts
system.physmem.perBankWrBursts::12               8080                       # Per bank write bursts
system.physmem.perBankWrBursts::13               8539                       # Per bank write bursts
system.physmem.perBankWrBursts::14               8032                       # Per bank write bursts
system.physmem.perBankWrBursts::15               8081                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
system.physmem.totGap                    5196390116500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  198404                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 126733                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    155323                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     13571                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6905                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2932                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2604                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1783                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1802                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1789                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      932                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      826                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      797                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      790                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      755                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      733                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      712                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      712                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      711                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       52                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5609                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6715                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5154                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                      305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      234                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       20                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        53708                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      387.265063                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     159.541838                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1283.636288                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          22377     41.66%     41.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         8801     16.39%     58.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         5780     10.76%     68.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         3435      6.40%     75.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         2322      4.32%     79.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         1859      3.46%     82.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451         1339      2.49%     85.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515         1034      1.93%     87.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          806      1.50%     88.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          663      1.23%     90.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          546      1.02%     91.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          427      0.80%     91.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          325      0.61%     92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          307      0.57%     93.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          277      0.52%     93.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          550      1.02%     94.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          185      0.34%     95.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          190      0.35%     95.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          112      0.21%     95.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          109      0.20%     95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          125      0.23%     96.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          422      0.79%     96.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          149      0.28%     97.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539           87      0.16%     97.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603           55      0.10%     97.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           85      0.16%     97.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           52      0.10%     97.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           36      0.07%     97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           25      0.05%     97.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           24      0.04%     97.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           18      0.03%     97.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           26      0.05%     97.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           25      0.05%     97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179           20      0.04%     97.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           14      0.03%     97.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307           13      0.02%     97.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371            9      0.02%     97.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435           14      0.03%     98.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499           11      0.02%     98.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563           11      0.02%     98.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627           14      0.03%     98.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691           11      0.02%     98.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755            9      0.02%     98.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819           10      0.02%     98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883           13      0.02%     98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947           10      0.02%     98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            8      0.01%     98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075           26      0.05%     98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139           12      0.02%     98.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203            9      0.02%     98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267           19      0.04%     98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331           10      0.02%     98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395            9      0.02%     98.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459           12      0.02%     98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            7      0.01%     98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587           12      0.02%     98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651           15      0.03%     98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715           10      0.02%     98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779           20      0.04%     98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843           13      0.02%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907           24      0.04%     98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971           13      0.02%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035           11      0.02%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099           19      0.04%     98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163           10      0.02%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227           13      0.02%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291            7      0.01%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355            9      0.02%     98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419           11      0.02%     98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483            7      0.01%     98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547            9      0.02%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611            9      0.02%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            4      0.01%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739           10      0.02%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803            9      0.02%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867            7      0.01%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            9      0.02%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995            7      0.01%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059            5      0.01%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123           13      0.02%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187            8      0.01%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251            7      0.01%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315            8      0.01%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379           10      0.02%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443            5      0.01%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507            9      0.02%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571          151      0.28%     99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699            1      0.00%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763            1      0.00%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827            2      0.00%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147            1      0.00%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211            3      0.01%     99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275            2      0.00%     99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403            1      0.00%     99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531            2      0.00%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595            4      0.01%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787            1      0.00%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            5      0.01%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915            4      0.01%     99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043            2      0.00%     99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107            1      0.00%     99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171           19      0.04%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            4      0.01%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427            1      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            2      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            1      0.00%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875            4      0.01%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067            3      0.01%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131            2      0.00%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195           14      0.03%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259            2      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387            1      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8515            3      0.01%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771            2      0.00%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155            2      0.00%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            4      0.01%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9280-9283            1      0.00%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539            2      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667            1      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795            1      0.00%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10115            1      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10176-10179            2      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10627            1      0.00%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11139            3      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11203            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267            4      0.01%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11904-11907            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12163            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12227            4      0.01%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419            2      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12483            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12547            2      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12803            1      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12867            2      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13123            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251            4      0.01%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315            6      0.01%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13760-13763            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13827            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13891            2      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14083            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14851            3      0.01%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915            7      0.01%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979            2      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171            2      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235            3      0.01%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363           32      0.06%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683            1      0.00%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875            3      0.01%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003            1      0.00%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259            1      0.00%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387          178      0.33%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          53708                       # Bytes accessed per row activation
system.physmem.totQLat                     5080719250                       # Total ticks spent queuing
system.physmem.totMemAccLat                8752324250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    991730000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  2679875000                       # Total ticks spent accessing banks
system.physmem.avgQLat                       25615.44                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    13511.11                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44126.55                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.44                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         8.98                       # Average write queue length when enqueuing
system.physmem.readRowHits                     173438                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     97917                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.26                       # Row buffer hit rate for writes
system.physmem.avgGap                     15982155.57                       # Average gap between requests
system.physmem.pageHitRate                      83.47                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.27                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                      4365247                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              623514                       # Transaction distribution
system.membus.trans_dist::ReadResp             623514                       # Transaction distribution
system.membus.trans_dist::WriteReq              13775                       # Transaction distribution
system.membus.trans_dist::WriteResp             13775                       # Transaction distribution
system.membus.trans_dist::Writeback            126733                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2150                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1634                       # Transaction distribution
system.membus.trans_dist::ReadExReq            159484                       # Transaction distribution
system.membus.trans_dist::ReadExResp           159484                       # Transaction distribution
system.membus.trans_dist::MessageReq             1655                       # Transaction distribution
system.membus.trans_dist::MessageResp            1655                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3310                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3310                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710114                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       391174                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1581616                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139281                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       139281                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1724207                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6620                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246444                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420225                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14938368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16605037                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5870400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5870400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            22482057                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               22482057                       # Total data (bytes)
system.membus.snoop_data_through_bus           201472                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           256796500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           359316000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3310000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1352149000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1655000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2612327754                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          428873750                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47501                       # number of replacements
system.iocache.tags.tagsinuse                0.113099                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47517                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5049776837000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.113099                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007069                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007069                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47556                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47556                       # number of overall misses
system.iocache.overall_misses::total            47556                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144134686                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    144134686                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12487439330                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  12487439330                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  12631574016                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  12631574016                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  12631574016                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  12631574016                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          836                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            836                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47556                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47556                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47556                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47556                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 172409.911483                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 267282.519906                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 265614.728236                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 265614.728236                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        216457                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11594                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    18.669743                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          836                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          836                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47556                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47556                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47556                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100637686                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    100637686                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide  10056284830                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total  10056284830                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide  10156922516                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total  10156922516                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide  10156922516                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total  10156922516                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 213578.150307                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 213578.150307                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        631264                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               230141                       # Transaction distribution
system.iobus.trans_dist::ReadResp              230141                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57579                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57579                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1655                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1655                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       436684                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       480328                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95112                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95112                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3310                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3310                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  578750                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       218342                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       246444                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6620                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3280296                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3280296                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3948164                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8813000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                77000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            218343000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           424033266                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           469469000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            52989250                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1655000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu.numCycles                      10392780360                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128334813                       # Number of instructions committed
system.cpu.committedOps                     247385808                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             231978567                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                     2299773                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23169265                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    231978567                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           434513747                       # number of times the integer registers were read
system.cpu.num_int_register_writes          197852200                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            132813019                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            95534921                       # number of times the CC registers were written
system.cpu.num_mem_refs                      22245363                       # number of memory refs
system.cpu.num_load_insts                    13878746                       # Number of load instructions
system.cpu.num_store_insts                    8366617                       # Number of store instructions
system.cpu.num_idle_cycles               9785238216.998117                       # Number of idle cycles
system.cpu.num_busy_cycles               607542143.001883                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.058458                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.941542                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.icache.tags.replacements            788090                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.351939                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           144584753                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            788602                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            183.343122                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      161436066250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.351939                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996781                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996781                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    144584753                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144584753                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144584753                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144584753                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144584753                       # number of overall hits
system.cpu.icache.overall_hits::total       144584753                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       788609                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        788609                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       788609                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         788609                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       788609                       # number of overall misses
system.cpu.icache.overall_misses::total        788609                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11107362758                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11107362758                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11107362758                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11107362758                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11107362758                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11107362758                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145373362                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145373362                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145373362                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145373362                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145373362                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145373362                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005425                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005425                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005425                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005425                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005425                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005425                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14084.752720                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14084.752720                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       788609                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       788609                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       788609                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       788609                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       788609                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       788609                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9525299242                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9525299242                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9525299242                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9525299242                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9525299242                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9525299242                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005425                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005425                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005425                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005425                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005425                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005425                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         3741                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     3.069761                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs         7617                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         3752                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.030117                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069761                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191860                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.191860                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7617                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7617                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7619                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7619                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7619                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7619                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4604                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4604                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4604                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4604                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4604                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4604                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     44886750                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     44886750                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     44886750                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     44886750                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     44886750                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     44886750                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12221                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12221                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12223                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12223                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12223                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.376729                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.376729                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.376667                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.376667                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.376667                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.376667                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9749.511295                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9749.511295                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9749.511295                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9749.511295                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9749.511295                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9749.511295                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          621                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          621                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4604                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4604                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4604                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4604                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4604                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4604                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     35677750                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     35677750                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     35677750                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     35677750                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     35677750                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     35677750                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.376729                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.376729                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.376667                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.376667                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.376667                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.376667                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7749.294092                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7749.294092                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7749.294092                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7749.294092                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7749.294092                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7749.294092                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements         7948                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse     5.052475                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        12793                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs         7961                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.606959                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052475                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315780                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315780                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12806                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        12806                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12806                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        12806                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12806                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        12806                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9138                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         9138                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9138                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         9138                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9138                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         9138                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     97347500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     97347500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     97347500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     97347500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     97347500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     97347500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21944                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        21944                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21944                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        21944                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21944                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        21944                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.416424                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.416424                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.416424                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.416424                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.416424                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.416424                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         3106                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         3106                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9138                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9138                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9138                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         9138                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9138                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         9138                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     79071000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     79071000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     79071000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     79071000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     79071000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     79071000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.416424                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.416424                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.416424                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.416424                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.416424                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.416424                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8652.987525                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8652.987525                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8652.987525                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8652.987525                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8652.987525                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8652.987525                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1621547                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.997026                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            20035701                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1622059                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.352017                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          50992250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.997026                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     11993197                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11993197                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8040328                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8040328                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      20033525                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20033525                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20033525                       # number of overall hits
system.cpu.dcache.overall_hits::total        20033525                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1308312                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1308312                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315974                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315974                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1624286                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1624286                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1624286                       # number of overall misses
system.cpu.dcache.overall_misses::total       1624286                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18913909300                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18913909300                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  11002078938                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  11002078938                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  29915988238                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  29915988238                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  29915988238                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  29915988238                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13301509                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13301509                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8356302                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8356302                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21657811                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21657811                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21657811                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21657811                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098358                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098358                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037813                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037813                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074998                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074998                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074998                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074998                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18417.931471                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18417.931471                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1538973                       # number of writebacks
system.cpu.dcache.writebacks::total           1538973                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308312                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1308312                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315974                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       315974                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1624286                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1624286                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1624286                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1624286                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16288101700                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  16288101700                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10316379062                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10316379062                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26604480762                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26604480762                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26604480762                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26604480762                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214673000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214673000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537491500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537491500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752164500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752164500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098358                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098358                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037813                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037813                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074998                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.074998                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074998                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074998                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput                49185341                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        2692945                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2692419                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13775                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13775                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1542700                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2176                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2176                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       360518                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       313820                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1577205                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5977035                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8133                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18986                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7581359                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50470144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203948077                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       225856                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       630272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      255274349                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         255253101                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       333120                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     3831866500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       498000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1185336258                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3054054238                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       6906500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      13707250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.l2cache.tags.replacements            86910                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64731.196890                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3488433                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           151626                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            23.006826                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.033461                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141258                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3445.447212                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.764778                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000001                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052573                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.170366                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.987720                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6740                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2903                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       775712                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1279207                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2064562                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1542700                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1542700                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          304                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          304                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       200752                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       200752                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6740                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2903                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       775712                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1479959                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2265314                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6740                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2903                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       775712                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1479959                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2265314                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12884                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28341                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        41232                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1356                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1356                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113042                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113042                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12884                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141383                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154274                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12884                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141383                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154274                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       136750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       347500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    979557242                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2186954200                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3166995692                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16260363                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16260363                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7957275400                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7957275400                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       136750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       347500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    979557242                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10144229600                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11124271092                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       136750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       347500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    979557242                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10144229600                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11124271092                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6742                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2908                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       788596                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1307548                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2105794                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1542700                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1542700                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1660                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1660                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       313794                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       313794                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6742                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2908                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       788596                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1621342                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2419588                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6742                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2908                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       788596                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1621342                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2419588                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000297                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001719                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016338                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021675                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019580                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.816867                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.816867                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.360243                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.360243                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000297                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001719                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016338                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087201                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063760                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000297                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001719                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016338                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087201                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063760                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        68375                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76028.969419                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77165.738682                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76809.169868                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11991.418142                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11991.418142                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70392.202898                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70392.202898                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        68375                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76028.969419                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71749.995403                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72107.231886                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        68375                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76028.969419                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71749.995403                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72107.231886                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        80066                       # number of writebacks
system.cpu.l2cache.writebacks::total            80066                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12884                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28341                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        41232                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1356                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1356                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113042                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113042                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12884                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141383                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154274                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12884                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141383                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154274                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       111250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       285000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    818022758                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1831787800                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2650206808                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14478338                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14478338                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6543285600                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6543285600                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       111250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       285000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    818022758                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8375073400                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9193492408                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       111250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       285000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    818022758                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8375073400                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9193492408                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86655869500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86655869500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370854000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370854000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026723500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026723500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000297                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001719                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016338                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021675                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019580                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.816867                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.816867                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360243                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360243                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000297                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001719                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016338                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087201                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063760                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000297                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001719                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016338                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087201                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063760                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63491.365880                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64633.844960                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64275.485254                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10677.240413                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10677.240413                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.668017                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.668017                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63491.365880                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59236.778113                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59591.975369                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63491.365880                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59236.778113                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59591.975369                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------