path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.192453                       # Number of seconds simulated
sim_ticks                                5192452884000                       # Number of ticks simulated
final_tick                               5192452884000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 836744                       # Simulator instruction rate (inst/s)
host_op_rate                                  1613002                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            33830425760                       # Simulator tick rate (ticks/s)
host_mem_usage                                 654168                       # Number of bytes of host memory used
host_seconds                                   153.48                       # Real time elapsed on the host
sim_insts                                   128427413                       # Number of instructions simulated
sim_ops                                     247571076                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            827456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9039104                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9895360                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       827456                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          827456                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8137984                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8137984                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12929                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141236                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                154615                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          127156                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               127156                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker             25                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               159357                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1740816                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5460                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1905720                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          159357                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             159357                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1567272                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1567272                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1567272                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              159357                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1740816                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5460                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3472991                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        154615                       # Number of read requests accepted
system.physmem.writeReqs                       173876                       # Number of write requests accepted
system.physmem.readBursts                      154615                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     173876                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9886592                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8768                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10962560                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9895360                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               11128064                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      137                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2557                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1589                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               10281                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9591                       # Per bank write bursts
system.physmem.perBankRdBursts::2               10028                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9674                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9945                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9558                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9523                       # Per bank write bursts
system.physmem.perBankRdBursts::7                9498                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9124                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8990                       # Per bank write bursts
system.physmem.perBankRdBursts::10               9390                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9205                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9557                       # Per bank write bursts
system.physmem.perBankRdBursts::13              10069                       # Per bank write bursts
system.physmem.perBankRdBursts::14              10020                       # Per bank write bursts
system.physmem.perBankRdBursts::15              10025                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10769                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10634                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10541                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10043                       # Per bank write bursts
system.physmem.perBankWrBursts::4               11026                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9713                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10229                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10822                       # Per bank write bursts
system.physmem.perBankWrBursts::8               11151                       # Per bank write bursts
system.physmem.perBankWrBursts::9               11218                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10861                       # Per bank write bursts
system.physmem.perBankWrBursts::11              10308                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10862                       # Per bank write bursts
system.physmem.perBankWrBursts::13              11716                       # Per bank write bursts
system.physmem.perBankWrBursts::14              11104                       # Per bank write bursts
system.physmem.perBankWrBursts::15              10293                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5192452820500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  154615                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 173876                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    151192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2858                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        51                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5087                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     8567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     9777                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    10086                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    11162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    11557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    12608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    12143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    12879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    11627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    11021                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     7506                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      310                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      271                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        60024                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      347.345862                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     200.231116                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     357.371422                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          21054     35.08%     35.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        13721     22.86%     57.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5818      9.69%     67.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3428      5.71%     73.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2258      3.76%     77.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1594      2.66%     79.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1149      1.91%     81.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          996      1.66%     83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10006     16.67%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          60024                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6317                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.452430                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      602.471336                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6316     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6317                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6317                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        27.115719                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       21.572083                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       27.245873                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23            4954     78.42%     78.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             303      4.80%     83.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             227      3.59%     86.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47              68      1.08%     87.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             174      2.75%     90.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              37      0.59%     91.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71              45      0.71%     91.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              56      0.89%     92.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              90      1.42%     94.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              19      0.30%     94.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            157      2.49%     97.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            22      0.35%     97.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            27      0.43%     97.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            21      0.33%     98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            36      0.57%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            11      0.17%     98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            22      0.35%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             8      0.13%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            14      0.22%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             6      0.09%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             5      0.08%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             1      0.02%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             1      0.02%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             4      0.06%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             3      0.05%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             3      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6317                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1525176500                       # Total ticks spent queuing
system.physmem.totMemAccLat                4421639000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    772390000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9873.10                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28623.10                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.91                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.14                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.96                       # Average write queue length when enqueuing
system.physmem.readRowHits                     125716                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    140027                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.38                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  81.73                       # Row buffer hit rate for writes
system.physmem.avgGap                     15806986.56                       # Average gap between requests
system.physmem.pageHitRate                      81.57                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  224879760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  122702250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 609164400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                542874960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           339145441440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           134202799845                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2997747003000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3472594865655                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.777986                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4986908920500                       # Time in different power states
system.physmem_0.memoryStateTime::REF    173387240000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32151782000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  228901680                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  124896750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 595756200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                567084240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           339145441440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           134282501235                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2997677089500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3472621671045                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.783148                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4986802992250                       # Time in different power states
system.physmem_1.memoryStateTime::REF    173387240000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     32262536750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                      10384905768                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128427413                       # Number of instructions committed
system.cpu.committedOps                     247571076                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             232151918                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                     2302537                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23180236                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    232151918                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           434861886                       # number of times the integer registers were read
system.cpu.num_int_register_writes          198003963                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            132886732                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            95589498                       # number of times the CC registers were written
system.cpu.num_mem_refs                      22270580                       # number of memory refs
system.cpu.num_load_insts                    13896035                       # Number of load instructions
system.cpu.num_store_insts                    8374545                       # Number of store instructions
system.cpu.num_idle_cycles               9787798534.998116                       # Number of idle cycles
system.cpu.num_busy_cycles               597107233.001885                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.057498                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.942502                       # Percentage of idle cycles
system.cpu.Branches                          26321851                       # Number of branches fetched
system.cpu.op_class::No_OpClass                175044      0.07%      0.07% # Class of executed instruction
system.cpu.op_class::IntAlu                 224863247     90.83%     90.90% # Class of executed instruction
system.cpu.op_class::IntMult                   140296      0.06%     90.95% # Class of executed instruction
system.cpu.op_class::IntDiv                    123429      0.05%     91.00% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.00% # Class of executed instruction
system.cpu.op_class::MemRead                 13896035      5.61%     96.62% # Class of executed instruction
system.cpu.op_class::MemWrite                 8374545      3.38%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  247572596                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements           1622236                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.996968                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            20050453                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1622748                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.355864                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          51171250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.996968                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          320                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88354150                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88354150                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     11949885                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11949885                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8039029                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8039029                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        59358                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         59358                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      19988914                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19988914                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20048272                       # number of overall hits
system.cpu.dcache.overall_hits::total        20048272                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       907019                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        907019                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       325091                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       325091                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       402457                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       402457                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1232110                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1232110                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1634567                       # number of overall misses
system.cpu.dcache.overall_misses::total       1634567                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  12730749000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  12730749000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  11380492066                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  11380492066                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  24111241066                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  24111241066                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  24111241066                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  24111241066                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12856904                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12856904                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8364120                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8364120                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       461815                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       461815                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21221024                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21221024                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21682839                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21682839                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070547                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.070547                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038867                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.038867                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.871468                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.871468                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.058061                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.058061                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.075385                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.075385                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14035.812921                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14035.812921                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35007.096678                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35007.096678                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19569.065316                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19569.065316                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14750.842924                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14750.842924                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         6388                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                73                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    87.506849                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1539114                       # number of writebacks
system.cpu.dcache.writebacks::total           1539114                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          287                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          287                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9270                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         9270                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         9557                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         9557                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         9557                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         9557                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       906732                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       906732                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315821                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       315821                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402422                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402422                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1222553                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1222553                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1624975                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1624975                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10909979000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  10909979000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10244477888                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10244477888                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5364351750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5364351750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  21154456888                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  21154456888                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26518808638                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26518808638                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94240373000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94240373000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2561567000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2561567000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96801940000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96801940000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070525                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070525                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037759                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037759                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.871392                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.871392                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057610                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.057610                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074943                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074943                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.198047                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.198047                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.608291                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.608291                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13330.165225                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13330.165225                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17303.509041                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17303.509041                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16319.517924                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16319.517924                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements         7361                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse     5.061574                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        13446                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs         7376                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.822939                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5159721667000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.061574                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316348                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316348                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses        52616                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses        52616                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13447                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        13447                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13447                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        13447                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13447                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        13447                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8574                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         8574                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8574                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         8574                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8574                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         8574                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     90024000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     90024000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     90024000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     90024000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     90024000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     90024000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22021                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        22021                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22021                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        22021                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22021                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        22021                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.389356                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.389356                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.389356                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.389356                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.389356                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.389356                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10499.650105                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10499.650105                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10499.650105                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10499.650105                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10499.650105                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10499.650105                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         2787                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         2787                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8574                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8574                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8574                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         8574                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8574                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         8574                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     72875500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     72875500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     72875500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     72875500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     72875500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     72875500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.389356                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.389356                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.389356                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.389356                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.389356                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.389356                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8499.591789                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8499.591789                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8499.591789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8499.591789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8499.591789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8499.591789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            793260                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.348682                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           144679610                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            793772                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            182.268473                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      161114367250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.348682                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996775                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996775                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          298                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         146267168                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        146267168                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    144679610                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144679610                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144679610                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144679610                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144679610                       # number of overall hits
system.cpu.icache.overall_hits::total       144679610                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       793779                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        793779                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       793779                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         793779                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       793779                       # number of overall misses
system.cpu.icache.overall_misses::total        793779                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11142507120                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11142507120                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11142507120                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11142507120                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11142507120                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11142507120                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145473389                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145473389                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145473389                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145473389                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145473389                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145473389                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005457                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005457                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005457                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005457                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005457                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005457                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14037.291387                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14037.291387                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14037.291387                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14037.291387                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14037.291387                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14037.291387                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       793779                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       793779                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       793779                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       793779                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       793779                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       793779                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9550046380                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9550046380                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9550046380                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9550046380                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9550046380                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9550046380                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005457                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005457                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005457                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005457                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005457                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005457                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.114932                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.114932                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.114932                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.114932                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.114932                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.114932                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         3392                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     3.080377                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs         8023                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         3405                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.356241                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5161936228000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.080377                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.192524                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.192524                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        28882                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        28882                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         8043                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         8043                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         8045                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         8045                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         8045                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         8045                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4264                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4264                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4264                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4264                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4264                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4264                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     41583500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     41583500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     41583500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     41583500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     41583500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     41583500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12307                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12307                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12309                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12309                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12309                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12309                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.346469                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.346469                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.346413                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.346413                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.346413                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.346413                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9752.227955                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9752.227955                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9752.227955                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9752.227955                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9752.227955                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9752.227955                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          713                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          713                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4264                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4264                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4264                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4264                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4264                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4264                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     33053500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     33053500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     33053500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     33053500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     33053500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     33053500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.346469                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.346469                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.346413                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.346413                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.346413                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.346413                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7751.758912                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7751.758912                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7751.758912                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7751.758912                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7751.758912                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7751.758912                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            87367                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64711.001958                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3492751                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           152091                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            22.964876                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50199.140845                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.014318                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141821                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3238.410068                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11273.294906                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.765978                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049414                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.172017                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.987412                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64724                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2777                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4943                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56808                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987610                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         32220272                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        32220272                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6177                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2685                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       780836                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1279767                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2069465                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1542614                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1542614                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          313                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          313                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       200061                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       200061                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6177                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2685                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       780836                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1479828                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2269526                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6177                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2685                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       780836                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1479828                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2269526                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            2                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12930                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28590                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        41527                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1330                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1330                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113574                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113574                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            2                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12930                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       142164                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        155101                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            2                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12930                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       142164                       # number of overall misses
system.cpu.l2cache.overall_misses::total       155101                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       136250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       365000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    947782000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2166641250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3114924500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16195366                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16195366                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7892320723                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7892320723                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       136250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       365000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    947782000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10058961973                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11007245223                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       136250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       365000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    947782000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10058961973                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11007245223                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6179                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2690                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       793766                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1308357                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2110992                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1542614                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1542614                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1643                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1643                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       313635                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       313635                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6179                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2690                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       793766                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1621992                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2424627                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6179                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2690                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       793766                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1621992                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2424627                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000324                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001859                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016289                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021852                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019672                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.809495                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.809495                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.362122                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.362122                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000324                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001859                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016289                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087648                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063969                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000324                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001859                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016289                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087648                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063969                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        68125                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        73000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73301.005414                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75783.184680                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75009.620247                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12176.966917                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12176.966917                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69490.558781                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69490.558781                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        68125                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        73000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73301.005414                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70756.042127                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70968.241488                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        68125                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        73000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73301.005414                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70756.042127                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70968.241488                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        80489                       # number of writebacks
system.cpu.l2cache.writebacks::total            80489                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            2                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12930                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28590                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        41527                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1330                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1330                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113574                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113574                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            2                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12930                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       142164                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       155101                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            2                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12930                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       142164                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       155101                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       111250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       301500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    785787500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1808339250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2594539500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14221312                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14221312                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6472690277                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6472690277                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       111250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       301500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    785787500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8281029527                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9067229777                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       111250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       301500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    785787500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8281029527                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9067229777                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86680074500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86680074500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2394785000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2394785000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89074859500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89074859500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000324                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001859                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016289                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021852                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019672                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.809495                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.809495                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362122                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362122                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000324                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001859                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016289                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087648                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063969                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000324                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001859                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016289                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087648                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063969                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60772.428461                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63250.760756                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62478.375515                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10692.715789                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10692.715789                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56990.951072                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56990.951072                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60772.428461                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58249.834888                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.163229                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        60300                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60772.428461                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58249.834888                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.163229                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        2698168                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2697644                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13888                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13888                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1542614                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2194                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2194                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       313640                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       313640                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1587545                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5978947                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7667                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        17540                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7591699                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50801024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203997643                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       217792                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       573824                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          255590283                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       53203                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4021775                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.011825                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.108096                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            3974219     98.82%     98.82% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              47556      1.18%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4021775                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     3834392000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       468000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1193119870                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3054097839                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy       6397000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy      12861250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               230256                       # Transaction distribution
system.iobus.trans_dist::ReadResp              230256                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57694                       # Transaction distribution
system.iobus.trans_dist::WriteResp              10974                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1654                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1654                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       436684                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       480788                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95112                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95112                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  579208                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       218342                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       246674                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3280522                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3944816                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8813000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                77000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            218343000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20719000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           448430581                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           469814000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            52212002                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1654000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47501                       # number of replacements
system.iocache.tags.tagsinuse                0.119711                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47517                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         5045856556000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.119711                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007482                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007482                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428004                       # Number of tag accesses
system.iocache.tags.data_accesses              428004                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          836                       # number of demand (read+write) misses
system.iocache.demand_misses::total               836                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          836                       # number of overall misses
system.iocache.overall_misses::total              836                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    143698686                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    143698686                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12361223893                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  12361223893                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    143698686                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    143698686                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    143698686                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    143698686                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          836                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            836                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          836                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             836                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          836                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            836                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171888.380383                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 171888.380383                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264580.990860                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 264580.990860                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 171888.380383                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 171888.380383                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 171888.380383                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 171888.380383                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         70511                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 9153                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.703594                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          836                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          836                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          836                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          836                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          836                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          836                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100200686                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    100200686                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9931779897                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9931779897                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    100200686                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    100200686                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    100200686                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    100200686                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 119857.279904                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212580.905330                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212580.905330                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 119857.279904                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 119857.279904                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              623924                       # Transaction distribution
system.membus.trans_dist::ReadResp             623924                       # Transaction distribution
system.membus.trans_dist::WriteReq              13888                       # Transaction distribution
system.membus.trans_dist::WriteResp             13888                       # Transaction distribution
system.membus.trans_dist::Writeback            127156                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2158                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1607                       # Transaction distribution
system.membus.trans_dist::ReadExReq            113297                       # Transaction distribution
system.membus.trans_dist::ReadExResp           113297                       # Transaction distribution
system.membus.trans_dist::MessageReq             1654                       # Transaction distribution
system.membus.trans_dist::MessageResp            1654                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3308                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3308                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480788                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710110                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393232                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1584130                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141386                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141386                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1728824                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6616                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246674                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420217                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15018304                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16685195                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22696931                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1614                       # Total snoops (count)
system.membus.snoop_fanout::samples            331694                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  331694    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              331694                       # Request fanout histogram
system.membus.reqLayer0.occupancy           257197500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           358100500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3308000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1731913000                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1654000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2619410411                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy           54258998                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.

---------- End Simulation Statistics   ----------