path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.191816                       # Number of seconds simulated
sim_ticks                                5191816279000                       # Number of ticks simulated
final_tick                               5191816279000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 631596                       # Simulator instruction rate (inst/s)
host_op_rate                                  1217489                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            25553396248                       # Simulator tick rate (ticks/s)
host_mem_usage                                 629228                       # Number of bytes of host memory used
host_seconds                                   203.18                       # Real time elapsed on the host
sim_insts                                   128324646                       # Number of instructions simulated
sim_ops                                     247363464                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2859648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            823360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9009408                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12692736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       823360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          823360                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8106432                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8106432                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        44682                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12865                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             140772                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198324                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126663                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               126663                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       550799                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158588                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1735309                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2444758                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158588                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158588                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1561387                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1561387                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1561387                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       550799                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158588                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1735309                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4006145                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198324                       # Total number of read requests seen
system.physmem.writeReqs                       126663                       # Total number of write requests seen
system.physmem.cpureqs                         326610                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     12692736                       # Total number of bytes read from memory
system.physmem.bytesWritten                   8106432                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               12692736                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                8106432                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       80                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               1618                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 12615                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 12250                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 12267                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 12575                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 12362                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 12187                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 12619                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 12562                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 12247                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 11965                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                12423                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                12610                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                12268                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12172                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                12546                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                12576                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  8002                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7779                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7802                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  8120                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7982                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7804                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8130                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  8156                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  7749                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7475                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7958                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 8068                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7819                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7741                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7995                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 8083                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           5                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5191816215500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  198324                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 126663                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    155046                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      8732                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6675                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3394                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2806                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2216                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2153                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2094                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2013                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1298                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1034                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      959                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      975                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1097                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      541                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      344                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5497                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5502                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5507                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        5                       # What write queue length does an incoming req see
system.physmem.totQLat                     4084993999                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                7884046499                       # Sum of mem lat for all requests
system.physmem.totBusLat                    991220000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2807832500                       # Total cycles spent in bank access
system.physmem.avgQLat                       20605.89                       # Average queueing delay per request
system.physmem.avgBankLat                    14163.52                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  39769.41                       # Average memory access latency
system.physmem.avgRdBW                           2.44                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.44                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.56                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         8.79                       # Average write queue length over time
system.physmem.readRowHits                     175346                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94626                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   88.45                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.71                       # Row buffer hit rate for writes
system.physmem.avgGap                     15975458.14                       # Average gap between requests
system.iocache.replacements                     47501                       # number of replacements
system.iocache.tagsinuse                     0.114811                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47517                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              5044702860000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.114811                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.007176                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.007176                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47556                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47556                       # number of overall misses
system.iocache.overall_misses::total            47556                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    136123397                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    136123397                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10718582907                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10718582907                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10854706304                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10854706304                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10854706304                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10854706304                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          836                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            836                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47556                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47556                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47556                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47556                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162827.029904                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162827.029904                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229421.723181                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 229421.723181                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228251.036757                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 228251.036757                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228251.036757                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 228251.036757                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        175533                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16256                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.798044                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          836                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          836                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47556                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47556                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47556                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     92629177                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     92629177                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8287786786                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8287786786                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8380415963                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8380415963                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8380415963                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8380415963                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110800.450957                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 110800.450957                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177392.696618                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 177392.696618                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176222.053221                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176222.053221                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                      10383632558                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128324646                       # Number of instructions committed
system.cpu.committedOps                     247363464                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             232097683                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23165556                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    232097683                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           567280399                       # number of times the integer registers were read
system.cpu.num_int_register_writes          293347970                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                      22249385                       # number of memory refs
system.cpu.num_load_insts                    13880834                       # Number of load instructions
system.cpu.num_store_insts                    8368551                       # Number of store instructions
system.cpu.num_idle_cycles               9782435662.998116                       # Number of idle cycles
system.cpu.num_busy_cycles               601196895.001884                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.057899                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.942101                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.icache.replacements                 795387                       # number of replacements
system.cpu.icache.tagsinuse                510.410338                       # Cycle average of tags in use
system.cpu.icache.total_refs                144562130                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 795899                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 181.633763                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle           160005789000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.410338                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996895                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996895                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    144562130                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144562130                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144562130                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144562130                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144562130                       # number of overall hits
system.cpu.icache.overall_hits::total       144562130                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       795906                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        795906                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       795906                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         795906                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       795906                       # number of overall misses
system.cpu.icache.overall_misses::total        795906                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  11017856500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  11017856500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  11017856500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  11017856500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  11017856500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  11017856500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145358036                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145358036                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145358036                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145358036                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145358036                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145358036                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005475                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005475                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005475                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005475                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005475                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005475                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13843.163012                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13843.163012                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13843.163012                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13843.163012                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13843.163012                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13843.163012                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       795906                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       795906                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       795906                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       795906                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       795906                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       795906                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9426044500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9426044500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9426044500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9426044500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9426044500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9426044500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005475                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005475                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005475                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005475                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005475                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005475                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11843.163012                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11843.163012                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11843.163012                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11843.163012                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11843.163012                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11843.163012                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         3694                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        3.067610                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs           7642                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         3706                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.062062                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5165748244000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.067610                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191726                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.191726                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7663                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7663                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7665                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7665                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7665                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7665                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4553                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4553                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4553                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4553                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4553                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4553                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     46128000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     46128000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     46128000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     46128000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     46128000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     46128000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12216                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12216                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12218                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12218                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12218                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12218                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.372708                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.372708                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.372647                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.372647                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.372647                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.372647                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10131.341972                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10131.341972                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10131.341972                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10131.341972                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10131.341972                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10131.341972                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          782                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          782                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4553                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4553                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4553                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4553                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4553                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4553                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     37022000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     37022000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     37022000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37022000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37022000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37022000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.372708                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.372708                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.372647                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.372647                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.372647                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.372647                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8131.341972                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8131.341972                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8131.341972                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8131.341972                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8131.341972                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8131.341972                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements         8348                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse        5.050573                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs          12635                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs         8361                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.511183                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5162441732000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.050573                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315661                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.315661                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12638                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        12638                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12638                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        12638                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12638                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        12638                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9544                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         9544                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9544                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         9544                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9544                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         9544                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    102265000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    102265000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    102265000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    102265000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    102265000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    102265000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22182                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        22182                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22182                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        22182                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22182                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        22182                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.430259                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.430259                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.430259                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.430259                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.430259                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.430259                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10715.108969                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10715.108969                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10715.108969                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10715.108969                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10715.108969                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10715.108969                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         3309                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         3309                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9544                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9544                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9544                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         9544                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9544                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         9544                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     83177000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     83177000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     83177000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     83177000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     83177000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     83177000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.430259                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.430259                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.430259                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.430259                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.430259                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.430259                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8715.108969                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8715.108969                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8715.108969                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8715.108969                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8715.108969                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8715.108969                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1620219                       # number of replacements
system.cpu.dcache.tagsinuse                511.997551                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 20041204                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1620731                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  12.365534                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               39012000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997551                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     11996661                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11996661                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8042358                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8042358                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      20039019                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20039019                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20039019                       # number of overall hits
system.cpu.dcache.overall_hits::total        20039019                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1307017                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1307017                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315944                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315944                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1622961                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1622961                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1622961                       # number of overall misses
system.cpu.dcache.overall_misses::total       1622961                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18338475500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18338475500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   8568992000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   8568992000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  26907467500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  26907467500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  26907467500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  26907467500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13303678                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13303678                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8358302                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8358302                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21661980                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21661980                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21661980                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21661980                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098245                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098245                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037800                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037800                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074922                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074922                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074922                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074922                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14030.785751                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14030.785751                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27121.869698                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27121.869698                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16579.244665                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16579.244665                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16579.244665                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16579.244665                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1537528                       # number of writebacks
system.cpu.dcache.writebacks::total           1537528                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1307017                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1307017                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315944                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       315944                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1622961                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1622961                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1622961                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1622961                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15724441500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  15724441500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7937104000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   7937104000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23661545500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23661545500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23661545500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23661545500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94200592000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94200592000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2523051000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2523051000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96723643000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96723643000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098245                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037800                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037800                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074922                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.074922                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074922                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074922                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.785751                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.785751                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25121.869698                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25121.869698                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14579.244665                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14579.244665                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14579.244665                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14579.244665                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 86848                       # number of replacements
system.cpu.l2cache.tagsinuse             64773.888762                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3493567                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                151551                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 23.052088                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50389.259334                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.140563                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3365.987776                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11018.501089                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.768879                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.051361                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.168129                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.988371                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7121                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3064                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       783027                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1277919                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2071131                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1541619                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1541619                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          322                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          322                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       200393                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       200393                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         7121                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3064                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       783027                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1478312                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2271524                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         7121                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3064                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       783027                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1478312                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2271524                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12866                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28339                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        41210                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1357                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1357                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113361                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113361                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12866                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141700                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154571                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12866                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141700                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154571                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       345000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    799855500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1637474000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2437674500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16426500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16426500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5582026000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5582026000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       345000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    799855500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7219500000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8019700500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       345000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    799855500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7219500000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8019700500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7121                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3069                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       795893                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1306258                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2112341                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1541619                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1541619                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1679                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1679                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       313754                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       313754                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7121                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3069                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       795893                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1620012                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2426095                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7121                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3069                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       795893                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1620012                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2426095                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001629                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016165                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021695                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019509                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.808219                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.808219                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361305                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.361305                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001629                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016165                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087468                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063712                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001629                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016165                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087468                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063712                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62168.156381                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57781.643671                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 59152.499393                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12105.011054                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12105.011054                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49241.149955                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49241.149955                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62168.156381                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50949.188426                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51883.603651                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62168.156381                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50949.188426                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51883.603651                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        79996                       # number of writebacks
system.cpu.l2cache.writebacks::total            79996                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12866                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28339                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        41210                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1357                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1357                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113361                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113361                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12866                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141700                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154571                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12866                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141700                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154571                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       281255                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    639995855                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1285411156                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1925688266                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14543837                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14543837                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4189000523                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4189000523                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       281255                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    639995855                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5474411679                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6114688789                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       281255                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    639995855                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5474411679                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6114688789                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86642607500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86642607500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2357207000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2357207000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88999814500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88999814500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001629                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016165                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021695                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019509                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808219                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808219                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361305                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361305                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001629                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016165                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087468                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063712                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001629                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016165                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087468                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063712                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49743.187859                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45358.380889                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46728.664547                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10717.639646                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10717.639646                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36952.748503                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36952.748503                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49743.187859                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38633.815660                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39559.094455                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49743.187859                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38633.815660                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39559.094455                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------