path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.191113                       # Number of seconds simulated
sim_ticks                                5191112864000                       # Number of ticks simulated
final_tick                               5191112864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1076481                       # Simulator instruction rate (inst/s)
host_op_rate                                  2075111                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            43574012985                       # Simulator tick rate (ticks/s)
host_mem_usage                                 651144                       # Number of bytes of host memory used
host_seconds                                   119.13                       # Real time elapsed on the host
sim_insts                                   128244620                       # Number of instructions simulated
sim_ops                                     247214608                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2852352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            825984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9026368                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12705024                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       825984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          825984                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8129280                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8129280                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        44568                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12906                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141037                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198516                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          127020                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               127020                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       549468                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               159115                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1738812                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2447457                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          159115                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             159115                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1565999                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1565999                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1565999                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       549468                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              159115                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1738812                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4013456                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198516                       # Total number of read requests seen
system.physmem.writeReqs                       127020                       # Total number of write requests seen
system.physmem.cpureqs                         331314                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     12705024                       # Total number of bytes read from memory
system.physmem.bytesWritten                   8129280                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               12705024                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                8129280                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       88                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               1599                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 12028                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 12411                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 11776                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 12503                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 12483                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 12755                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 12240                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 12788                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 12663                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 12687                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                12141                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                12548                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                12236                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12474                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                11907                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                12788                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7431                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7966                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7373                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  8083                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7981                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8219                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7719                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  8332                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8225                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8161                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7712                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 8125                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7893                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7991                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 7528                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 8281                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5191112800500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  198516                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 127020                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 1599                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    158090                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11440                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7599                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2597                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3245                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2511                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1497                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1744                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1556                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1514                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1392                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1291                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1281                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1081                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      569                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      355                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      264                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      183                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                      898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     2876225269                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                6438451269                       # Sum of mem lat for all requests
system.physmem.totBusLat                    793712000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2768514000                       # Total cycles spent in bank access
system.physmem.avgQLat                       14495.06                       # Average queueing delay per request
system.physmem.avgBankLat                    13952.23                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  32447.29                       # Average memory access latency
system.physmem.avgRdBW                           2.45                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.45                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.57                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         9.06                       # Average write queue length over time
system.physmem.readRowHits                     179831                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     78085                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   90.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  61.47                       # Row buffer hit rate for writes
system.physmem.avgGap                     15946355.55                       # Average gap between requests
system.iocache.replacements                     47506                       # number of replacements
system.iocache.tagsinuse                     0.117830                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47522                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              5044498925000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.117830                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.007364                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.007364                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          841                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              841                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47561                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47561                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47561                       # number of overall misses
system.iocache.overall_misses::total            47561                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    133668932                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    133668932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   9598301160                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   9598301160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   9731970092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   9731970092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   9731970092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   9731970092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          841                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            841                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47561                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47561                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47561                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47561                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158940.466112                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 158940.466112                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 205443.089897                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 205443.089897                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 204620.804693                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 204620.804693                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 204620.804693                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 204620.804693                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         78425                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                10368                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.564140                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          841                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          841                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47561                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47561                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47561                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47561                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89906992                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     89906992                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7166703132                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7166703132                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7256610124                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7256610124                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7256610124                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7256610124                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106904.865636                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 106904.865636                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 153396.899229                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 153396.899229                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 152574.801287                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 152574.801287                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 152574.801287                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                      10382225728                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128244620                       # Number of instructions committed
system.cpu.committedOps                     247214608                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             231949869                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23149723                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    231949869                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           566905534                       # number of times the integer registers were read
system.cpu.num_int_register_writes          293156476                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                      22227095                       # number of memory refs
system.cpu.num_load_insts                    13866667                       # Number of load instructions
system.cpu.num_store_insts                    8360428                       # Number of store instructions
system.cpu.num_idle_cycles               9781583060.998116                       # Number of idle cycles
system.cpu.num_busy_cycles               600642667.001884                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.057853                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.942147                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.icache.replacements                 790930                       # number of replacements
system.cpu.icache.tagsinuse                510.376048                       # Cycle average of tags in use
system.cpu.icache.total_refs                144455345                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 791442                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 182.521707                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle           159759301000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.376048                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996828                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996828                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    144455345                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144455345                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144455345                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144455345                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144455345                       # number of overall hits
system.cpu.icache.overall_hits::total       144455345                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       791449                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        791449                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       791449                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         791449                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       791449                       # number of overall misses
system.cpu.icache.overall_misses::total        791449                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  10871281000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  10871281000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  10871281000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  10871281000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  10871281000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  10871281000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145246794                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145246794                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145246794                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145246794                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145246794                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145246794                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005449                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005449                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005449                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005449                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005449                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005449                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.921076                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13735.921076                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.921076                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13735.921076                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791449                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       791449                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       791449                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       791449                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       791449                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       791449                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9288383000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9288383000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9288383000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9288383000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9288383000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9288383000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005449                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005449                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005449                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005449                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005449                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005449                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11735.921076                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11735.921076                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11735.921076                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11735.921076                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11735.921076                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11735.921076                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         3663                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        3.069768                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs           7696                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         3675                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.094150                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5164936292000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.069768                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191861                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.191861                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7696                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7696                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7698                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7698                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7698                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7698                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4528                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4528                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4528                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4528                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4528                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4528                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     46136000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     46136000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     46136000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     46136000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     46136000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     46136000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12224                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12224                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12226                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12226                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12226                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12226                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.370419                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.370419                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.370358                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.370358                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.370358                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.370358                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10189.045936                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10189.045936                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10189.045936                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10189.045936                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10189.045936                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10189.045936                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          884                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          884                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4528                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4528                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4528                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4528                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4528                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4528                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     37080000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     37080000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     37080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37080000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37080000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37080000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.370419                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.370419                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.370358                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.370358                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.370358                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.370358                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8189.045936                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8189.045936                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8189.045936                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8189.045936                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8189.045936                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8189.045936                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements         8012                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse        5.053256                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs          13052                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs         8025                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.626417                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5162707625000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.053256                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315829                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.315829                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13068                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        13068                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13068                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        13068                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13068                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        13068                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9194                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         9194                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9194                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         9194                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9194                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         9194                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     98984000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     98984000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     98984000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     98984000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     98984000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     98984000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22262                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        22262                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22262                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        22262                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22262                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        22262                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.412991                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.412991                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.412991                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.412991                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.412991                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.412991                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10766.151838                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10766.151838                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10766.151838                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10766.151838                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10766.151838                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10766.151838                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         3347                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         3347                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9194                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9194                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9194                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         9194                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9194                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         9194                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     80596000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     80596000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     80596000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     80596000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     80596000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     80596000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.412991                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.412991                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.412991                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.412991                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.412991                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.412991                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8766.151838                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8766.151838                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8766.151838                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8766.151838                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8766.151838                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8766.151838                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1620901                       # number of replacements
system.cpu.dcache.tagsinuse                511.997778                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 20018690                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1621413                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  12.346447                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               38749000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997778                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     11981580                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11981580                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8034928                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8034928                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      20016508                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20016508                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20016508                       # number of overall hits
system.cpu.dcache.overall_hits::total        20016508                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1308145                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1308145                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315486                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315486                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1623631                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1623631                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1623631                       # number of overall misses
system.cpu.dcache.overall_misses::total       1623631                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18313636000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18313636000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   8702717500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   8702717500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  27016353500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  27016353500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  27016353500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  27016353500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13289725                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13289725                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8350414                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8350414                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21640139                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21640139                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21640139                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21640139                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098433                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098433                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037781                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037781                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.075029                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.075029                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.075029                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.075029                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16639.466418                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16639.466418                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1538028                       # number of writebacks
system.cpu.dcache.writebacks::total           1538028                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308145                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1308145                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315486                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       315486                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1623631                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1623631                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1623631                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1623631                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15697346000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  15697346000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8071745500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8071745500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23769091500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23769091500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23769091500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23769091500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94147176000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94147176000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2469978500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2469978500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96617154500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96617154500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098433                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098433                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037781                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037781                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075029                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.075029                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075029                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.075029                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 87015                       # number of replacements
system.cpu.l2cache.tagsinuse             64709.520704                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3488531                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                151765                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.986400                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50328.696692                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.140121                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3391.684309                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  10988.999582                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.767955                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.051753                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.167679                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.987389                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6912                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3076                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       778529                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1278877                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2067394                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1542259                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1542259                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          324                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          324                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       199770                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       199770                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6912                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         3076                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       778529                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1478647                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2267164                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6912                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         3076                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       778529                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1478647                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2267164                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12907                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28433                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        41345                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1340                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1340                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113530                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113530                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12907                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141963                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154875                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12907                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141963                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154875                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       345000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    711631000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1599594500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2311570500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16623000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16623000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5723743500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5723743500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       345000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    711631000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7323338000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8035314000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       345000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    711631000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7323338000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8035314000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6912                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3081                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       791436                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1307310                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2108739                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1542259                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1542259                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1664                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1664                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       313300                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       313300                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6912                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         3081                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       791436                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1620610                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2422039                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6912                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         3081                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       791436                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1620610                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2422039                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001623                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016308                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021749                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019607                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.805288                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.805288                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.362368                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.362368                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001623                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016308                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087598                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063944                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001623                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016308                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087598                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063944                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        80353                       # number of writebacks
system.cpu.l2cache.writebacks::total            80353                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12907                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28433                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        41345                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1340                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1340                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113530                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113530                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12907                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141963                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154875                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12907                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141963                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154875                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       280010                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    544173395                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1230976255                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1775429660                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14316322                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14316322                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4249333352                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4249333352                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       280010                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    544173395                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5480309607                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6024763012                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       280010                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    544173395                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5480309607                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6024763012                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86592298500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86592298500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2307004500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2307004500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88899303000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88899303000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001623                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016308                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021749                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019607                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.805288                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.805288                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.362368                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.362368                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001623                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016308                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087598                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063944                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001623                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016308                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087598                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063944                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        56002                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        56002                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        56002                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------