blob: a4ae62a223b87a25a21ca4a38e5416b6533102d5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
|
---------- Begin Simulation Statistics ----------
sim_seconds 5.191766 # Number of seconds simulated
sim_ticks 5191766314000 # Number of ticks simulated
final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 787684 # Simulator instruction rate (inst/s)
host_op_rate 1511929 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29598304712 # Simulator tick rate (ticks/s)
host_mem_usage 358992 # Number of bytes of host memory used
host_seconds 175.41 # Real time elapsed on the host
sim_insts 138165780 # Number of instructions simulated
sim_ops 265203824 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory
system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8080768 # Number of bytes written to this memory
system.physmem.bytes_written::total 8080768 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 45173 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139677 # Number of read requests responded to by this memory
system.physmem.num_reads::total 197687 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 126262 # Number of write requests responded to by this memory
system.physmem.num_writes::total 126262 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 556857 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 158183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1721828 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2436929 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 158183 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 158183 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1556458 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1556458 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 86221 # number of replacements
system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use
system.l2c.total_refs 3490237 # Total number of references to valid blocks.
system.l2c.sampled_refs 150947 # Sample count of references to valid blocks.
system.l2c.avg_refs 23.122268 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1541329 # number of Writeback hits
system.l2c.Writeback_hits::total 1541329 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 200451 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits
system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 6306 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 2757 # number of overall hits
system.l2c.overall_hits::cpu.inst 777565 # number of overall hits
system.l2c.overall_hits::cpu.data 1479802 # number of overall hits
system.l2c.overall_hits::total 2266430 # number of overall hits
system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 12833 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 28373 # number of ReadReq misses
system.l2c.ReadReq_misses::total 41211 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 1346 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 112235 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 112235 # number of ReadExReq misses
system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 12833 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 140608 # number of demand (read+write) misses
system.l2c.demand_misses::total 153446 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu.inst 12833 # number of overall misses
system.l2c.overall_misses::cpu.data 140608 # number of overall misses
system.l2c.overall_misses::total 153446 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst 667948500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 1489806000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2158014500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 32975000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 32975000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 5839097000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 5839097000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst 667948500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 7328903000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 7997111500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst 667948500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 7328903000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 7997111500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1541329 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1541329 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 312686 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 6306 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 2762 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 790398 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001810 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.016236 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.021696 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.019557 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.808408 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.808408 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.358938 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.358938 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.001810 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.016236 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.086773 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.063411 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.001810 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.016236 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.086773 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.063411 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52049.286994 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.877207 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52365.011769 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24498.514116 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 24498.514116 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52025.633715 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52025.633715 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52049.286994 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52122.944640 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52116.780496 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52049.286994 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52122.944640 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52116.780496 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 79595 # number of writebacks
system.l2c.writebacks::total 79595 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst 12833 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 28373 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 41211 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 1346 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1346 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 112235 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 112235 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst 12833 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 140608 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 153446 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst 12833 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 140608 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 153446 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 513944000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1149325000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1663469000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 54216000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 54216000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4492274000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4492274000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst 513944000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 5641599000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6155743000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst 513944000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 5641599000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6155743000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56050191064 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 56050191064 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1204378000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1204378000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 57254569064 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 57254569064 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021696 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.019557 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.808408 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.808408 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358938 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.358938 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.063411 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.063411 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40048.624640 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.700983 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40364.684186 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40279.346211 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40279.346211 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40025.606985 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40025.606985 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 47504 # number of replacements
system.iocache.tagsinuse 0.108710 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47520 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 5048944307000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.108710 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.006794 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.006794 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses
system.iocache.ReadReq_misses::total 839 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses
system.iocache.demand_misses::total 47559 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses
system.iocache.overall_misses::total 47559 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128944932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 128944932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7159405160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 7159405160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 7288350092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 7288350092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 7288350092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 7288350092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153688.834327 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 153688.834327 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 153240.692637 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 153240.692637 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 153248.598415 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 153248.598415 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85286000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 85286000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4729709976 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4729709976 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4814995976 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4814995976 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101651.966627 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 101651.966627 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 101235.230651 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 101235.230651 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.numCycles 10383532628 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 138165780 # Number of instructions committed
system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls
system.cpu.num_int_insts 249613019 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read
system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 23180616 # number of memory refs
system.cpu.num_load_insts 14822216 # Number of load instructions
system.cpu.num_store_insts 8358400 # Number of store instructions
system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles
system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles
system.cpu.not_idle_fraction 0.058907 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.941093 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.icache.replacements 789892 # number of replacements
system.cpu.icache.tagsinuse 510.351457 # Cycle average of tags in use
system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 790404 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.351457 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996780 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996780 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits
system.cpu.icache.overall_hits::total 158472876 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 790411 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 790411 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 790411 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 790411 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 790411 # number of overall misses
system.cpu.icache.overall_misses::total 790411 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004963 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.004963 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.004963 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.004963 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.004963 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.004963 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004963 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.004963 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.004963 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 3403 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 3.070913 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 8040 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 3415 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.354319 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070913 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191932 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.191932 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8060 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 8060 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8062 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 8062 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8062 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 8062 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4266 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4266 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4266 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4266 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4266 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4266 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50418000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50418000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50418000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 50418000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50418000 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 50418000 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12326 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12326 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12328 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12328 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12328 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12328 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346098 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346098 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346042 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.346042 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346042 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.346042 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11818.565401 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11818.565401 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11818.565401 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11818.565401 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 726 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 726 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4266 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4266 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4266 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 4266 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4266 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 4266 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37620000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37620000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37620000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37620000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37620000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37620000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346098 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346098 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346042 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346042 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8818.565401 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 7529 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 5.053120 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 13331 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 7543 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.767334 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053120 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315820 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.315820 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13332 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13332 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13332 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13332 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13332 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13332 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8729 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8729 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8729 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8729 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8729 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8729 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112265000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112265000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112265000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 112265000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112265000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 112265000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22061 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 22061 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22061 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 22061 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22061 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 22061 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395676 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395676 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395676 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395676 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395676 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395676 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12861.152480 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12861.152480 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12861.152480 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12861.152480 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 2916 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2916 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8729 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8729 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8729 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8729 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8729 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8729 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 86078000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 86078000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 86078000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 86078000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 86078000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 86078000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395676 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395676 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395676 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9861.152480 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1620698 # number of replacements
system.cpu.dcache.tagsinuse 511.997463 # Cycle average of tags in use
system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997463 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits
system.cpu.dcache.overall_hits::total 20022635 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 314872 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 314872 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1623422 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1623422 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1623422 # number of overall misses
system.cpu.dcache.overall_misses::total 1623422 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872663500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 19872663500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327755500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9327755500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 29200419000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 29200419000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 29200419000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 29200419000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13297693 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13297693 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8348364 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8348364 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21646057 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21646057 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21646057 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21646057 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098404 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098404 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037717 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037717 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.074999 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.074999 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074999 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074999 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17986.955333 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17986.955333 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1537687 # number of writebacks
system.cpu.dcache.writebacks::total 1537687 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308550 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1308550 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314872 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 314872 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1623422 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1623422 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1623422 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1623422 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75924400500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75924400500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1366040500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1366040500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77290441000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 77290441000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098404 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098404 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037717 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037717 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.074999 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074999 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|