path: root/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.187336                       # Number of seconds simulated
sim_ticks                                5187335906000                       # Number of ticks simulated
final_tick                               5187335906000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 633010                       # Simulator instruction rate (inst/s)
host_op_rate                                  1220249                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            25590316667                       # Simulator tick rate (ticks/s)
host_mem_usage                                 632708                       # Number of bytes of host memory used
host_seconds                                   202.71                       # Real time elapsed on the host
sim_insts                                   128315489                       # Number of instructions simulated
sim_ops                                     247353048                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2850304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            824512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9026304                       # Number of bytes read from this memory
system.physmem.bytes_read::total             12701440                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       824512                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          824512                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8120576                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8120576                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        44536                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              12883                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             141036                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                198460                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          126884                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               126884                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       549474                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               158947                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1740065                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2448548                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          158947                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             158947                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1565462                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1565462                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1565462                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       549474                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              158947                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1740065                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4014010                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        198460                       # Total number of read requests seen
system.physmem.writeReqs                       126884                       # Total number of write requests seen
system.physmem.cpureqs                         326965                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     12701440                       # Total number of bytes read from memory
system.physmem.bytesWritten                   8120576                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               12701440                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                8120576                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      110                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               1615                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 12387                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 12046                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 12118                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 12449                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 12193                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 12119                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 12473                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 12536                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 12592                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 12290                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                12456                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                12641                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                12408                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12254                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                12740                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                12648                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  7793                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  7533                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  7699                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  7988                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  7862                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  7739                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  7964                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  8103                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8131                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  7898                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 7933                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 8107                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 7973                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 7879                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8152                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 8130                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           6                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5187335842500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  198460                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 126884                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    155340                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      8720                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6686                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3417                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3378                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2810                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      2218                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      2141                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2080                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      2004                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1172                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1032                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      958                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      968                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                     1114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                     1055                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      518                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      325                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      5338                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      5455                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      5485                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      5501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      5506                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      5508                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      5508                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     5517                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      179                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
system.physmem.totQLat                     4133329999                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                7970683749                       # Sum of mem lat for all requests
system.physmem.totBusLat                    991750000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2845603750                       # Total cycles spent in bank access
system.physmem.avgQLat                       20838.57                       # Average queueing delay per request
system.physmem.avgBankLat                    14346.38                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  40184.94                       # Average memory access latency
system.physmem.avgRdBW                           2.45                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.45                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.57                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        12.90                       # Average write queue length over time
system.physmem.readRowHits                     174211                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     94671                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.61                       # Row buffer hit rate for writes
system.physmem.avgGap                     15944157.08                       # Average gap between requests
system.iocache.replacements                     47504                       # number of replacements
system.iocache.tagsinuse                     0.157150                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47520                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              5044705088000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.157150                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.009822                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.009822                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          837                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              837                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47557                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47557                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47557                       # number of overall misses
system.iocache.overall_misses::total            47557                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    139731143                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    139731143                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10765565415                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10765565415                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10905296558                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10905296558                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10905296558                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10905296558                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          837                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            837                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47557                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47557                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47557                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47557                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166942.823178                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 166942.823178                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 230427.341931                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 230427.341931                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 229310.018672                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 229310.018672                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 229310.018672                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 229310.018672                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        177808                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16153                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.007739                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46669                       # number of writebacks
system.iocache.writebacks::total                46669                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          837                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          837                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47557                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47557                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47557                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47557                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96185423                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     96185423                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   8334760316                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   8334760316                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8430945739                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8430945739                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8430945739                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8430945739                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114916.873357                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 114916.873357                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 178398.123202                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 178398.123202                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 177280.857476                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 177280.857476                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                      10374671812                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   128315489                       # Number of instructions committed
system.cpu.committedOps                     247353048                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             232087369                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                     2299349                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     23166071                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    232087369                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads           567244076                       # number of times the integer registers were read
system.cpu.num_int_register_writes          293343891                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                      22240299                       # number of memory refs
system.cpu.num_load_insts                    13876403                       # Number of load instructions
system.cpu.num_store_insts                    8363896                       # Number of store instructions
system.cpu.num_idle_cycles               9773542516.998116                       # Number of idle cycles
system.cpu.num_busy_cycles               601129295.001884                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.057942                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.942058                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.icache.replacements                 790572                       # number of replacements
system.cpu.icache.tagsinuse                510.408986                       # Cycle average of tags in use
system.cpu.icache.total_refs                144555062                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 791084                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                 182.730357                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle           160005789000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.408986                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996893                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996893                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    144555062                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       144555062                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     144555062                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        144555062                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    144555062                       # number of overall hits
system.cpu.icache.overall_hits::total       144555062                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       791091                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        791091                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       791091                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         791091                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       791091                       # number of overall misses
system.cpu.icache.overall_misses::total        791091                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  10944017000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  10944017000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  10944017000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  10944017000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  10944017000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  10944017000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    145346153                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    145346153                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    145346153                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    145346153                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    145346153                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    145346153                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005443                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.005443                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.005443                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.005443                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.005443                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.005443                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.081035                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13834.081035                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.081035                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13834.081035                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.081035                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13834.081035                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791091                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       791091                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       791091                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       791091                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       791091                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       791091                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9361835000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   9361835000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9361835000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   9361835000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9361835000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   9361835000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005443                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005443                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005443                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.005443                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005443                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.005443                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.081035                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.081035                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.081035                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.081035                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.081035                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.081035                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         3538                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        3.071073                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs           7817                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         3549                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.202592                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5161021529000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.071073                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191942                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.191942                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7819                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7819                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7821                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7821                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7821                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7821                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4399                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4399                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4399                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4399                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4399                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4399                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     43289000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     43289000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     43289000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     43289000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     43289000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     43289000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12218                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12218                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12220                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12220                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12220                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12220                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.360043                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.360043                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.359984                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.359984                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.359984                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.359984                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9840.645601                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9840.645601                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9840.645601                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9840.645601                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9840.645601                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9840.645601                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          650                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          650                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4399                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4399                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4399                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         4399                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4399                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         4399                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     34491000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     34491000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     34491000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     34491000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     34491000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     34491000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.360043                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.360043                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.359984                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.359984                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.359984                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.359984                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7840.645601                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7840.645601                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7840.645601                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7840.645601                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7840.645601                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7840.645601                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements         7602                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse        5.053533                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs          13277                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs         7616                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.743304                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5155312372000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.053533                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315846                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.315846                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13278                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        13278                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13278                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        13278                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13278                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        13278                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8808                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         8808                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8808                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         8808                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8808                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         8808                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     93210000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     93210000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     93210000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total     93210000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     93210000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total     93210000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22086                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        22086                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22086                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        22086                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22086                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        22086                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.398805                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.398805                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.398805                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.398805                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.398805                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.398805                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10582.425068                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10582.425068                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10582.425068                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10582.425068                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10582.425068                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10582.425068                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         2984                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         2984                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8808                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8808                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8808                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total         8808                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8808                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total         8808                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     75594000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     75594000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     75594000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     75594000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     75594000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     75594000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.398805                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.398805                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.398805                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.398805                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.398805                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.398805                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8582.425068                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8582.425068                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8582.425068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8582.425068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8582.425068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8582.425068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1620743                       # number of replacements
system.cpu.dcache.tagsinuse                511.997667                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 20031616                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1621255                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  12.355623                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               39012000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997667                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     11991279                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11991279                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8038109                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8038109                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      20029388                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20029388                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20029388                       # number of overall hits
system.cpu.dcache.overall_hits::total        20029388                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1307954                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1307954                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315546                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315546                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      1623500                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1623500                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1623500                       # number of overall misses
system.cpu.dcache.overall_misses::total       1623500                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  18389416000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  18389416000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   8586143000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   8586143000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  26975559000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  26975559000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  26975559000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  26975559000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13299233                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13299233                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8353655                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8353655                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21652888                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21652888                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21652888                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21652888                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098348                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.098348                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037773                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037773                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.074978                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.074978                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074978                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074978                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14059.680998                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14059.680998                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27210.432076                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27210.432076                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16615.681552                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16615.681552                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16615.681552                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16615.681552                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1538215                       # number of writebacks
system.cpu.dcache.writebacks::total           1538215                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1307954                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1307954                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315546                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       315546                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1623500                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1623500                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1623500                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1623500                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15773508000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  15773508000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7955051000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   7955051000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23728559000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23728559000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23728559000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  23728559000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94200596500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94200596500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2522793500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2522793500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96723390000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  96723390000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098348                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098348                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037773                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037773                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074978                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.074978                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074978                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.074978                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12059.680998                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12059.680998                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25210.432076                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25210.432076                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14615.681552                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14615.681552                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14615.681552                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14615.681552                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                 87004                       # number of replacements
system.cpu.l2cache.tagsinuse             64771.472210                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3487444                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                151687                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.991054                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50378.956222                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.140585                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3347.055983                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11045.319419                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.768722                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.051072                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.168538                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.988334                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6442                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2817                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       778194                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1278591                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2066044                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1541849                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1541849                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          308                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          308                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       199895                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       199895                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6442                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2817                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       778194                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1478486                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2265939                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6442                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2817                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       778194                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1478486                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2265939                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        12884                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        28512                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        41401                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1385                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1385                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       113419                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       113419                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        12884                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       141931                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        154820                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        12884                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       141931                       # number of overall misses
system.cpu.l2cache.overall_misses::total       154820                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       345000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    788791000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1678791500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2467927500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     15947000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     15947000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5604900000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5604900000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       345000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    788791000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7283691500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8072827500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       345000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    788791000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7283691500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8072827500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6442                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2822                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       791078                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1307103                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2107445                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1541849                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1541849                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1693                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1693                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       313314                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       313314                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6442                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2822                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       791078                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1620417                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2420759                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6442                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2822                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       791078                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1620417                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2420759                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001772                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016287                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021813                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.019645                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.818074                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818074                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361998                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.361998                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001772                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016287                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087589                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063955                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001772                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016287                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087589                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063955                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61222.524061                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58880.173260                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 59610.335499                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11514.079422                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11514.079422                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49417.646073                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49417.646073                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61222.524061                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51318.538586                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52143.311588                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61222.524061                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51318.538586                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52143.311588                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        80215                       # number of writebacks
system.cpu.l2cache.writebacks::total            80215                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12884                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28512                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        41401                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1385                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1385                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113419                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       113419                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        12884                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       141931                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154820                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        12884                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       141931                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       154820                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       281255                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    628701625                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1324271586                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1953254466                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14803865                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14803865                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4210880830                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4210880830                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       281255                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    628701625                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5535152416                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6164135296                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       281255                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    628701625                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5535152416                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6164135296                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86642612000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86642612000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2356974000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2356974000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  88999586000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  88999586000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001772                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016287                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021813                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019645                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.818074                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818074                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361998                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361998                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001772                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016287                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087589                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.063955                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001772                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016287                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087589                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.063955                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48797.083592                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46446.113426                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47178.919978                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10688.711191                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10688.711191                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37126.767385                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37126.767385                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48797.083592                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38998.896760                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39814.851415                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        56251                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48797.083592                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38998.896760                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39814.851415                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------